1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2012-2013, Xilinx, Michal Simek
4 *
5 * (C) Copyright 2012
6 * Joe Hershberger <joe.hershberger@ni.com>
7 */
8
9 #include <common.h>
10 #include <console.h>
11 #include <cpu_func.h>
12 #include <log.h>
13 #include <asm/cache.h>
14 #include <asm/io.h>
15 #include <fs.h>
16 #include <zynqpl.h>
17 #include <linux/delay.h>
18 #include <linux/sizes.h>
19 #include <asm/arch/hardware.h>
20 #include <asm/arch/sys_proto.h>
21
22 #define DEVCFG_CTRL_PCFG_PROG_B 0x40000000
23 #define DEVCFG_CTRL_PCFG_AES_EFUSE_MASK 0x00001000
24 #define DEVCFG_CTRL_PCAP_RATE_EN_MASK 0x02000000
25 #define DEVCFG_CTRL_PCFG_AES_EN_MASK 0x00000E00
26 #define DEVCFG_ISR_FATAL_ERROR_MASK 0x00740040
27 #define DEVCFG_ISR_ERROR_FLAGS_MASK 0x00340840
28 #define DEVCFG_ISR_RX_FIFO_OV 0x00040000
29 #define DEVCFG_ISR_DMA_DONE 0x00002000
30 #define DEVCFG_ISR_PCFG_DONE 0x00000004
31 #define DEVCFG_STATUS_DMA_CMD_Q_F 0x80000000
32 #define DEVCFG_STATUS_DMA_CMD_Q_E 0x40000000
33 #define DEVCFG_STATUS_DMA_DONE_CNT_MASK 0x30000000
34 #define DEVCFG_STATUS_PCFG_INIT 0x00000010
35 #define DEVCFG_MCTRL_PCAP_LPBK 0x00000010
36 #define DEVCFG_MCTRL_RFIFO_FLUSH 0x00000002
37 #define DEVCFG_MCTRL_WFIFO_FLUSH 0x00000001
38
39 #ifndef CONFIG_SYS_FPGA_WAIT
40 #define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */
41 #endif
42
43 #ifndef CONFIG_SYS_FPGA_PROG_TIME
44 #define CONFIG_SYS_FPGA_PROG_TIME (CONFIG_SYS_HZ * 4) /* 4 s */
45 #endif
46
47 #define DUMMY_WORD 0xffffffff
48
49 /* Xilinx binary format header */
50 static const u32 bin_format[] = {
51 DUMMY_WORD, /* Dummy words */
52 DUMMY_WORD,
53 DUMMY_WORD,
54 DUMMY_WORD,
55 DUMMY_WORD,
56 DUMMY_WORD,
57 DUMMY_WORD,
58 DUMMY_WORD,
59 0x000000bb, /* Sync word */
60 0x11220044, /* Sync word */
61 DUMMY_WORD,
62 DUMMY_WORD,
63 0xaa995566, /* Sync word */
64 };
65
66 #define SWAP_NO 1
67 #define SWAP_DONE 2
68
69 /*
70 * Load the whole word from unaligned buffer
71 * Keep in your mind that it is byte loading on little-endian system
72 */
load_word(const void * buf,u32 swap)73 static u32 load_word(const void *buf, u32 swap)
74 {
75 u32 word = 0;
76 u8 *bitc = (u8 *)buf;
77 int p;
78
79 if (swap == SWAP_NO) {
80 for (p = 0; p < 4; p++) {
81 word <<= 8;
82 word |= bitc[p];
83 }
84 } else {
85 for (p = 3; p >= 0; p--) {
86 word <<= 8;
87 word |= bitc[p];
88 }
89 }
90
91 return word;
92 }
93
check_header(const void * buf)94 static u32 check_header(const void *buf)
95 {
96 u32 i, pattern;
97 int swap = SWAP_NO;
98 u32 *test = (u32 *)buf;
99
100 debug("%s: Let's check bitstream header\n", __func__);
101
102 /* Checking that passing bin is not a bitstream */
103 for (i = 0; i < ARRAY_SIZE(bin_format); i++) {
104 pattern = load_word(&test[i], swap);
105
106 /*
107 * Bitstreams in binary format are swapped
108 * compare to regular bistream.
109 * Do not swap dummy word but if swap is done assume
110 * that parsing buffer is binary format
111 */
112 if ((__swab32(pattern) != DUMMY_WORD) &&
113 (__swab32(pattern) == bin_format[i])) {
114 pattern = __swab32(pattern);
115 swap = SWAP_DONE;
116 debug("%s: data swapped - let's swap\n", __func__);
117 }
118
119 debug("%s: %d/%x: pattern %x/%x bin_format\n", __func__, i,
120 (u32)&test[i], pattern, bin_format[i]);
121 if (pattern != bin_format[i]) {
122 debug("%s: Bitstream is not recognized\n", __func__);
123 return 0;
124 }
125 }
126 debug("%s: Found bitstream header at %x %s swapinng\n", __func__,
127 (u32)buf, swap == SWAP_NO ? "without" : "with");
128
129 return swap;
130 }
131
check_data(u8 * buf,size_t bsize,u32 * swap)132 static void *check_data(u8 *buf, size_t bsize, u32 *swap)
133 {
134 u32 word, p = 0; /* possition */
135
136 /* Because buf doesn't need to be aligned let's read it by chars */
137 for (p = 0; p < bsize; p++) {
138 word = load_word(&buf[p], SWAP_NO);
139 debug("%s: word %x %x/%x\n", __func__, word, p, (u32)&buf[p]);
140
141 /* Find the first bitstream dummy word */
142 if (word == DUMMY_WORD) {
143 debug("%s: Found dummy word at position %x/%x\n",
144 __func__, p, (u32)&buf[p]);
145 *swap = check_header(&buf[p]);
146 if (*swap) {
147 /* FIXME add full bitstream checking here */
148 return &buf[p];
149 }
150 }
151 /* Loop can be huge - support CTRL + C */
152 if (ctrlc())
153 return NULL;
154 }
155 return NULL;
156 }
157
zynq_dma_transfer(u32 srcbuf,u32 srclen,u32 dstbuf,u32 dstlen)158 static int zynq_dma_transfer(u32 srcbuf, u32 srclen, u32 dstbuf, u32 dstlen)
159 {
160 unsigned long ts;
161 u32 isr_status;
162
163 /* Set up the transfer */
164 writel((u32)srcbuf, &devcfg_base->dma_src_addr);
165 writel(dstbuf, &devcfg_base->dma_dst_addr);
166 writel(srclen, &devcfg_base->dma_src_len);
167 writel(dstlen, &devcfg_base->dma_dst_len);
168
169 isr_status = readl(&devcfg_base->int_sts);
170
171 /* Polling the PCAP_INIT status for Set */
172 ts = get_timer(0);
173 while (!(isr_status & DEVCFG_ISR_DMA_DONE)) {
174 if (isr_status & DEVCFG_ISR_ERROR_FLAGS_MASK) {
175 debug("%s: Error: isr = 0x%08X\n", __func__,
176 isr_status);
177 debug("%s: Write count = 0x%08X\n", __func__,
178 readl(&devcfg_base->write_count));
179 debug("%s: Read count = 0x%08X\n", __func__,
180 readl(&devcfg_base->read_count));
181
182 return FPGA_FAIL;
183 }
184 if (get_timer(ts) > CONFIG_SYS_FPGA_PROG_TIME) {
185 printf("%s: Timeout wait for DMA to complete\n",
186 __func__);
187 return FPGA_FAIL;
188 }
189 isr_status = readl(&devcfg_base->int_sts);
190 }
191
192 debug("%s: DMA transfer is done\n", __func__);
193
194 /* Clear out the DMA status */
195 writel(DEVCFG_ISR_DMA_DONE, &devcfg_base->int_sts);
196
197 return FPGA_SUCCESS;
198 }
199
zynq_dma_xfer_init(bitstream_type bstype)200 static int zynq_dma_xfer_init(bitstream_type bstype)
201 {
202 u32 status, control, isr_status;
203 unsigned long ts;
204
205 /* Clear loopback bit */
206 clrbits_le32(&devcfg_base->mctrl, DEVCFG_MCTRL_PCAP_LPBK);
207
208 if (bstype != BIT_PARTIAL && bstype != BIT_NONE) {
209 zynq_slcr_devcfg_disable();
210
211 /* Setting PCFG_PROG_B signal to high */
212 control = readl(&devcfg_base->ctrl);
213 writel(control | DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl);
214
215 /*
216 * Delay is required if AES efuse is selected as
217 * key source.
218 */
219 if (control & DEVCFG_CTRL_PCFG_AES_EFUSE_MASK)
220 mdelay(5);
221
222 /* Setting PCFG_PROG_B signal to low */
223 writel(control & ~DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl);
224
225 /*
226 * Delay is required if AES efuse is selected as
227 * key source.
228 */
229 if (control & DEVCFG_CTRL_PCFG_AES_EFUSE_MASK)
230 mdelay(5);
231
232 /* Polling the PCAP_INIT status for Reset */
233 ts = get_timer(0);
234 while (readl(&devcfg_base->status) & DEVCFG_STATUS_PCFG_INIT) {
235 if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
236 printf("%s: Timeout wait for INIT to clear\n",
237 __func__);
238 return FPGA_FAIL;
239 }
240 }
241
242 /* Setting PCFG_PROG_B signal to high */
243 writel(control | DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl);
244
245 /* Polling the PCAP_INIT status for Set */
246 ts = get_timer(0);
247 while (!(readl(&devcfg_base->status) &
248 DEVCFG_STATUS_PCFG_INIT)) {
249 if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
250 printf("%s: Timeout wait for INIT to set\n",
251 __func__);
252 return FPGA_FAIL;
253 }
254 }
255 }
256
257 isr_status = readl(&devcfg_base->int_sts);
258
259 /* Clear it all, so if Boot ROM comes back, it can proceed */
260 writel(0xFFFFFFFF, &devcfg_base->int_sts);
261
262 if (isr_status & DEVCFG_ISR_FATAL_ERROR_MASK) {
263 debug("%s: Fatal errors in PCAP 0x%X\n", __func__, isr_status);
264
265 /* If RX FIFO overflow, need to flush RX FIFO first */
266 if (isr_status & DEVCFG_ISR_RX_FIFO_OV) {
267 writel(DEVCFG_MCTRL_RFIFO_FLUSH, &devcfg_base->mctrl);
268 writel(0xFFFFFFFF, &devcfg_base->int_sts);
269 }
270 return FPGA_FAIL;
271 }
272
273 status = readl(&devcfg_base->status);
274
275 debug("%s: Status = 0x%08X\n", __func__, status);
276
277 if (status & DEVCFG_STATUS_DMA_CMD_Q_F) {
278 debug("%s: Error: device busy\n", __func__);
279 return FPGA_FAIL;
280 }
281
282 debug("%s: Device ready\n", __func__);
283
284 if (!(status & DEVCFG_STATUS_DMA_CMD_Q_E)) {
285 if (!(readl(&devcfg_base->int_sts) & DEVCFG_ISR_DMA_DONE)) {
286 /* Error state, transfer cannot occur */
287 debug("%s: ISR indicates error\n", __func__);
288 return FPGA_FAIL;
289 } else {
290 /* Clear out the status */
291 writel(DEVCFG_ISR_DMA_DONE, &devcfg_base->int_sts);
292 }
293 }
294
295 if (status & DEVCFG_STATUS_DMA_DONE_CNT_MASK) {
296 /* Clear the count of completed DMA transfers */
297 writel(DEVCFG_STATUS_DMA_DONE_CNT_MASK, &devcfg_base->status);
298 }
299
300 return FPGA_SUCCESS;
301 }
302
zynq_align_dma_buffer(u32 * buf,u32 len,u32 swap)303 static u32 *zynq_align_dma_buffer(u32 *buf, u32 len, u32 swap)
304 {
305 u32 *new_buf;
306 u32 i;
307
308 if ((u32)buf != ALIGN((u32)buf, ARCH_DMA_MINALIGN)) {
309 new_buf = (u32 *)ALIGN((u32)buf, ARCH_DMA_MINALIGN);
310
311 /*
312 * This might be dangerous but permits to flash if
313 * ARCH_DMA_MINALIGN is greater than header size
314 */
315 if (new_buf > buf) {
316 debug("%s: Aligned buffer is after buffer start\n",
317 __func__);
318 new_buf = (u32 *)((u32)new_buf - ARCH_DMA_MINALIGN);
319 }
320 printf("%s: Align buffer at %x to %x(swap %d)\n", __func__,
321 (u32)buf, (u32)new_buf, swap);
322
323 for (i = 0; i < (len/4); i++)
324 new_buf[i] = load_word(&buf[i], swap);
325
326 buf = new_buf;
327 } else if (swap != SWAP_DONE) {
328 /* For bitstream which are aligned */
329 u32 *new_buf = (u32 *)buf;
330
331 printf("%s: Bitstream is not swapped(%d) - swap it\n", __func__,
332 swap);
333
334 for (i = 0; i < (len/4); i++)
335 new_buf[i] = load_word(&buf[i], swap);
336 }
337
338 return buf;
339 }
340
zynq_validate_bitstream(xilinx_desc * desc,const void * buf,size_t bsize,u32 blocksize,u32 * swap,bitstream_type * bstype)341 static int zynq_validate_bitstream(xilinx_desc *desc, const void *buf,
342 size_t bsize, u32 blocksize, u32 *swap,
343 bitstream_type *bstype)
344 {
345 u32 *buf_start;
346 u32 diff;
347
348 buf_start = check_data((u8 *)buf, blocksize, swap);
349
350 if (!buf_start)
351 return FPGA_FAIL;
352
353 /* Check if data is postpone from start */
354 diff = (u32)buf_start - (u32)buf;
355 if (diff) {
356 printf("%s: Bitstream is not validated yet (diff %x)\n",
357 __func__, diff);
358 return FPGA_FAIL;
359 }
360
361 if ((u32)buf < SZ_1M) {
362 printf("%s: Bitstream has to be placed up to 1MB (%x)\n",
363 __func__, (u32)buf);
364 return FPGA_FAIL;
365 }
366
367 if (zynq_dma_xfer_init(*bstype))
368 return FPGA_FAIL;
369
370 return 0;
371 }
372
zynq_load(xilinx_desc * desc,const void * buf,size_t bsize,bitstream_type bstype)373 static int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize,
374 bitstream_type bstype)
375 {
376 unsigned long ts; /* Timestamp */
377 u32 isr_status, swap;
378
379 /*
380 * send bsize inplace of blocksize as it was not a bitstream
381 * in chunks
382 */
383 if (zynq_validate_bitstream(desc, buf, bsize, bsize, &swap,
384 &bstype))
385 return FPGA_FAIL;
386
387 buf = zynq_align_dma_buffer((u32 *)buf, bsize, swap);
388
389 debug("%s: Source = 0x%08X\n", __func__, (u32)buf);
390 debug("%s: Size = %zu\n", __func__, bsize);
391
392 /* flush(clean & invalidate) d-cache range buf */
393 flush_dcache_range((u32)buf, (u32)buf +
394 roundup(bsize, ARCH_DMA_MINALIGN));
395
396 if (zynq_dma_transfer((u32)buf | 1, bsize >> 2, 0xffffffff, 0))
397 return FPGA_FAIL;
398
399 isr_status = readl(&devcfg_base->int_sts);
400 /* Check FPGA configuration completion */
401 ts = get_timer(0);
402 while (!(isr_status & DEVCFG_ISR_PCFG_DONE)) {
403 if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
404 printf("%s: Timeout wait for FPGA to config\n",
405 __func__);
406 return FPGA_FAIL;
407 }
408 isr_status = readl(&devcfg_base->int_sts);
409 }
410
411 debug("%s: FPGA config done\n", __func__);
412
413 if (bstype != BIT_PARTIAL)
414 zynq_slcr_devcfg_enable();
415
416 puts("INFO:post config was not run, please run manually if needed\n");
417
418 return FPGA_SUCCESS;
419 }
420
421 #if defined(CONFIG_CMD_FPGA_LOADFS) && !defined(CONFIG_SPL_BUILD)
zynq_loadfs(xilinx_desc * desc,const void * buf,size_t bsize,fpga_fs_info * fsinfo)422 static int zynq_loadfs(xilinx_desc *desc, const void *buf, size_t bsize,
423 fpga_fs_info *fsinfo)
424 {
425 unsigned long ts; /* Timestamp */
426 u32 isr_status, swap;
427 u32 partialbit = 0;
428 loff_t blocksize, actread;
429 loff_t pos = 0;
430 int fstype;
431 char *interface, *dev_part;
432 const char *filename;
433
434 blocksize = fsinfo->blocksize;
435 interface = fsinfo->interface;
436 dev_part = fsinfo->dev_part;
437 filename = fsinfo->filename;
438 fstype = fsinfo->fstype;
439
440 if (fs_set_blk_dev(interface, dev_part, fstype))
441 return FPGA_FAIL;
442
443 if (fs_read(filename, (u32) buf, pos, blocksize, &actread) < 0)
444 return FPGA_FAIL;
445
446 if (zynq_validate_bitstream(desc, buf, bsize, blocksize, &swap,
447 &partialbit))
448 return FPGA_FAIL;
449
450 dcache_disable();
451
452 do {
453 buf = zynq_align_dma_buffer((u32 *)buf, blocksize, swap);
454
455 if (zynq_dma_transfer((u32)buf | 1, blocksize >> 2,
456 0xffffffff, 0))
457 return FPGA_FAIL;
458
459 bsize -= blocksize;
460 pos += blocksize;
461
462 if (fs_set_blk_dev(interface, dev_part, fstype))
463 return FPGA_FAIL;
464
465 if (bsize > blocksize) {
466 if (fs_read(filename, (u32) buf, pos, blocksize, &actread) < 0)
467 return FPGA_FAIL;
468 } else {
469 if (fs_read(filename, (u32) buf, pos, bsize, &actread) < 0)
470 return FPGA_FAIL;
471 }
472 } while (bsize > blocksize);
473
474 buf = zynq_align_dma_buffer((u32 *)buf, blocksize, swap);
475
476 if (zynq_dma_transfer((u32)buf | 1, bsize >> 2, 0xffffffff, 0))
477 return FPGA_FAIL;
478
479 dcache_enable();
480
481 isr_status = readl(&devcfg_base->int_sts);
482
483 /* Check FPGA configuration completion */
484 ts = get_timer(0);
485 while (!(isr_status & DEVCFG_ISR_PCFG_DONE)) {
486 if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
487 printf("%s: Timeout wait for FPGA to config\n",
488 __func__);
489 return FPGA_FAIL;
490 }
491 isr_status = readl(&devcfg_base->int_sts);
492 }
493
494 debug("%s: FPGA config done\n", __func__);
495
496 if (!partialbit)
497 zynq_slcr_devcfg_enable();
498
499 return FPGA_SUCCESS;
500 }
501 #endif
502
503 struct xilinx_fpga_op zynq_op = {
504 .load = zynq_load,
505 #if defined(CONFIG_CMD_FPGA_LOADFS) && !defined(CONFIG_SPL_BUILD)
506 .loadfs = zynq_loadfs,
507 #endif
508 };
509
510 #ifdef CONFIG_CMD_ZYNQ_AES
511 /*
512 * Load the encrypted image from src addr and decrypt the image and
513 * place it back the decrypted image into dstaddr.
514 */
zynq_decrypt_load(u32 srcaddr,u32 srclen,u32 dstaddr,u32 dstlen,u8 bstype)515 int zynq_decrypt_load(u32 srcaddr, u32 srclen, u32 dstaddr, u32 dstlen,
516 u8 bstype)
517 {
518 u32 isr_status, ts;
519
520 if (srcaddr < SZ_1M || dstaddr < SZ_1M) {
521 printf("%s: src and dst addr should be > 1M\n",
522 __func__);
523 return FPGA_FAIL;
524 }
525
526 /* Check AES engine is enabled */
527 if (!(readl(&devcfg_base->ctrl) &
528 DEVCFG_CTRL_PCFG_AES_EN_MASK)) {
529 printf("%s: AES engine is not enabled\n", __func__);
530 return FPGA_FAIL;
531 }
532
533 if (zynq_dma_xfer_init(bstype)) {
534 printf("%s: zynq_dma_xfer_init FAIL\n", __func__);
535 return FPGA_FAIL;
536 }
537
538 writel((readl(&devcfg_base->ctrl) | DEVCFG_CTRL_PCAP_RATE_EN_MASK),
539 &devcfg_base->ctrl);
540
541 debug("%s: Source = 0x%08X\n", __func__, (u32)srcaddr);
542 debug("%s: Size = %zu\n", __func__, srclen);
543
544 /* flush(clean & invalidate) d-cache range buf */
545 flush_dcache_range((u32)srcaddr, (u32)srcaddr +
546 roundup(srclen << 2, ARCH_DMA_MINALIGN));
547 /*
548 * Flush destination address range only if image is not
549 * bitstream.
550 */
551 if (bstype == BIT_NONE && dstaddr != 0xFFFFFFFF)
552 flush_dcache_range((u32)dstaddr, (u32)dstaddr +
553 roundup(dstlen << 2, ARCH_DMA_MINALIGN));
554
555 if (zynq_dma_transfer(srcaddr | 1, srclen, dstaddr | 1, dstlen))
556 return FPGA_FAIL;
557
558 if (bstype == BIT_FULL) {
559 isr_status = readl(&devcfg_base->int_sts);
560 /* Check FPGA configuration completion */
561 ts = get_timer(0);
562 while (!(isr_status & DEVCFG_ISR_PCFG_DONE)) {
563 if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
564 printf("%s: Timeout wait for FPGA to config\n",
565 __func__);
566 return FPGA_FAIL;
567 }
568 isr_status = readl(&devcfg_base->int_sts);
569 }
570 printf("%s: FPGA config done\n", __func__);
571 zynq_slcr_devcfg_enable();
572 }
573
574 return FPGA_SUCCESS;
575 }
576 #endif
577