1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2019 NXP
4 * Copyright 2013 Freescale Semiconductor, Inc.
5 */
6
7 #include <common.h>
8 #include <clk.h>
9 #include <dm.h>
10 #include <fsl_lpuart.h>
11 #include <log.h>
12 #include <watchdog.h>
13 #include <asm/global_data.h>
14 #include <asm/io.h>
15 #include <serial.h>
16 #include <dm/device_compat.h>
17 #include <linux/bitops.h>
18 #include <linux/compiler.h>
19 #include <asm/arch/imx-regs.h>
20 #include <asm/arch/clock.h>
21
22 #define US1_TDRE (1 << 7)
23 #define US1_RDRF (1 << 5)
24 #define US1_OR (1 << 3)
25 #define UC2_TE (1 << 3)
26 #define UC2_RE (1 << 2)
27 #define CFIFO_TXFLUSH (1 << 7)
28 #define CFIFO_RXFLUSH (1 << 6)
29 #define SFIFO_RXOF (1 << 2)
30 #define SFIFO_RXUF (1 << 0)
31
32 #define STAT_LBKDIF (1 << 31)
33 #define STAT_RXEDGIF (1 << 30)
34 #define STAT_TDRE (1 << 23)
35 #define STAT_RDRF (1 << 21)
36 #define STAT_IDLE (1 << 20)
37 #define STAT_OR (1 << 19)
38 #define STAT_NF (1 << 18)
39 #define STAT_FE (1 << 17)
40 #define STAT_PF (1 << 16)
41 #define STAT_MA1F (1 << 15)
42 #define STAT_MA2F (1 << 14)
43 #define STAT_FLAGS (STAT_LBKDIF | STAT_RXEDGIF | STAT_IDLE | STAT_OR | \
44 STAT_NF | STAT_FE | STAT_PF | STAT_MA1F | STAT_MA2F)
45
46 #define CTRL_TE (1 << 19)
47 #define CTRL_RE (1 << 18)
48
49 #define FIFO_RXFLUSH BIT(14)
50 #define FIFO_TXFLUSH BIT(15)
51 #define FIFO_TXSIZE_MASK 0x70
52 #define FIFO_TXSIZE_OFF 4
53 #define FIFO_RXSIZE_MASK 0x7
54 #define FIFO_RXSIZE_OFF 0
55 #define FIFO_TXFE 0x80
56 #if defined(CONFIG_ARCH_IMX8) || defined(CONFIG_ARCH_IMXRT)
57 #define FIFO_RXFE 0x08
58 #else
59 #define FIFO_RXFE 0x40
60 #endif
61
62 #define WATER_TXWATER_OFF 0
63 #define WATER_RXWATER_OFF 16
64
65 DECLARE_GLOBAL_DATA_PTR;
66
67 #define LPUART_FLAG_REGMAP_32BIT_REG BIT(0)
68 #define LPUART_FLAG_REGMAP_ENDIAN_BIG BIT(1)
69
70 enum lpuart_devtype {
71 DEV_VF610 = 1,
72 DEV_LS1021A,
73 DEV_MX7ULP,
74 DEV_IMX8,
75 DEV_IMXRT,
76 };
77
78 struct lpuart_serial_plat {
79 void *reg;
80 enum lpuart_devtype devtype;
81 ulong flags;
82 };
83
lpuart_read32(u32 flags,u32 * addr,u32 * val)84 static void lpuart_read32(u32 flags, u32 *addr, u32 *val)
85 {
86 if (flags & LPUART_FLAG_REGMAP_32BIT_REG) {
87 if (flags & LPUART_FLAG_REGMAP_ENDIAN_BIG)
88 *(u32 *)val = in_be32(addr);
89 else
90 *(u32 *)val = in_le32(addr);
91 }
92 }
93
lpuart_write32(u32 flags,u32 * addr,u32 val)94 static void lpuart_write32(u32 flags, u32 *addr, u32 val)
95 {
96 if (flags & LPUART_FLAG_REGMAP_32BIT_REG) {
97 if (flags & LPUART_FLAG_REGMAP_ENDIAN_BIG)
98 out_be32(addr, val);
99 else
100 out_le32(addr, val);
101 }
102 }
103
104
105 #ifndef CONFIG_SYS_CLK_FREQ
106 #define CONFIG_SYS_CLK_FREQ 0
107 #endif
108
get_lpuart_clk(void)109 u32 __weak get_lpuart_clk(void)
110 {
111 return CONFIG_SYS_CLK_FREQ;
112 }
113
114 #if CONFIG_IS_ENABLED(CLK)
get_lpuart_clk_rate(struct udevice * dev,u32 * clk)115 static int get_lpuart_clk_rate(struct udevice *dev, u32 *clk)
116 {
117 struct clk per_clk;
118 ulong rate;
119 int ret;
120
121 ret = clk_get_by_name(dev, "per", &per_clk);
122 if (ret) {
123 dev_err(dev, "Failed to get per clk: %d\n", ret);
124 return ret;
125 }
126
127 rate = clk_get_rate(&per_clk);
128 if ((long)rate <= 0) {
129 dev_err(dev, "Failed to get per clk rate: %ld\n", (long)rate);
130 return ret;
131 }
132 *clk = rate;
133 return 0;
134 }
135 #else
get_lpuart_clk_rate(struct udevice * dev,u32 * clk)136 static inline int get_lpuart_clk_rate(struct udevice *dev, u32 *clk)
137 { return -ENOSYS; }
138 #endif
139
is_lpuart32(struct udevice * dev)140 static bool is_lpuart32(struct udevice *dev)
141 {
142 struct lpuart_serial_plat *plat = dev_get_plat(dev);
143
144 return plat->flags & LPUART_FLAG_REGMAP_32BIT_REG;
145 }
146
_lpuart_serial_setbrg(struct udevice * dev,int baudrate)147 static void _lpuart_serial_setbrg(struct udevice *dev,
148 int baudrate)
149 {
150 struct lpuart_serial_plat *plat = dev_get_plat(dev);
151 struct lpuart_fsl *base = plat->reg;
152 u32 clk;
153 u16 sbr;
154 int ret;
155
156 if (CONFIG_IS_ENABLED(CLK)) {
157 ret = get_lpuart_clk_rate(dev, &clk);
158 if (ret)
159 return;
160 } else {
161 clk = get_lpuart_clk();
162 }
163
164 sbr = (u16)(clk / (16 * baudrate));
165
166 /* place adjustment later - n/32 BRFA */
167 __raw_writeb(sbr >> 8, &base->ubdh);
168 __raw_writeb(sbr & 0xff, &base->ubdl);
169 }
170
_lpuart_serial_getc(struct lpuart_serial_plat * plat)171 static int _lpuart_serial_getc(struct lpuart_serial_plat *plat)
172 {
173 struct lpuart_fsl *base = plat->reg;
174 while (!(__raw_readb(&base->us1) & (US1_RDRF | US1_OR)))
175 WATCHDOG_RESET();
176
177 barrier();
178
179 return __raw_readb(&base->ud);
180 }
181
_lpuart_serial_putc(struct lpuart_serial_plat * plat,const char c)182 static void _lpuart_serial_putc(struct lpuart_serial_plat *plat,
183 const char c)
184 {
185 struct lpuart_fsl *base = plat->reg;
186
187 while (!(__raw_readb(&base->us1) & US1_TDRE))
188 WATCHDOG_RESET();
189
190 __raw_writeb(c, &base->ud);
191 }
192
193 /* Test whether a character is in the RX buffer */
_lpuart_serial_tstc(struct lpuart_serial_plat * plat)194 static int _lpuart_serial_tstc(struct lpuart_serial_plat *plat)
195 {
196 struct lpuart_fsl *base = plat->reg;
197
198 if (__raw_readb(&base->urcfifo) == 0)
199 return 0;
200
201 return 1;
202 }
203
204 /*
205 * Initialise the serial port with the given baudrate. The settings
206 * are always 8 data bits, no parity, 1 stop bit, no start bits.
207 */
_lpuart_serial_init(struct udevice * dev)208 static int _lpuart_serial_init(struct udevice *dev)
209 {
210 struct lpuart_serial_plat *plat = dev_get_plat(dev);
211 struct lpuart_fsl *base = (struct lpuart_fsl *)plat->reg;
212 u8 ctrl;
213
214 ctrl = __raw_readb(&base->uc2);
215 ctrl &= ~UC2_RE;
216 ctrl &= ~UC2_TE;
217 __raw_writeb(ctrl, &base->uc2);
218
219 __raw_writeb(0, &base->umodem);
220 __raw_writeb(0, &base->uc1);
221
222 /* Disable FIFO and flush buffer */
223 __raw_writeb(0x0, &base->upfifo);
224 __raw_writeb(0x0, &base->utwfifo);
225 __raw_writeb(0x1, &base->urwfifo);
226 __raw_writeb(CFIFO_TXFLUSH | CFIFO_RXFLUSH, &base->ucfifo);
227
228 /* provide data bits, parity, stop bit, etc */
229 _lpuart_serial_setbrg(dev, gd->baudrate);
230
231 __raw_writeb(UC2_RE | UC2_TE, &base->uc2);
232
233 return 0;
234 }
235
_lpuart32_serial_setbrg_7ulp(struct udevice * dev,int baudrate)236 static void _lpuart32_serial_setbrg_7ulp(struct udevice *dev,
237 int baudrate)
238 {
239 struct lpuart_serial_plat *plat = dev_get_plat(dev);
240 struct lpuart_fsl_reg32 *base = plat->reg;
241 u32 sbr, osr, baud_diff, tmp_osr, tmp_sbr, tmp_diff, tmp;
242 u32 clk;
243 int ret;
244
245 if (CONFIG_IS_ENABLED(CLK)) {
246 ret = get_lpuart_clk_rate(dev, &clk);
247 if (ret)
248 return;
249 } else {
250 clk = get_lpuart_clk();
251 }
252
253 baud_diff = baudrate;
254 osr = 0;
255 sbr = 0;
256
257 for (tmp_osr = 4; tmp_osr <= 32; tmp_osr++) {
258 tmp_sbr = (clk / (baudrate * tmp_osr));
259
260 if (tmp_sbr == 0)
261 tmp_sbr = 1;
262
263 /*calculate difference in actual buad w/ current values */
264 tmp_diff = (clk / (tmp_osr * tmp_sbr));
265 tmp_diff = tmp_diff - baudrate;
266
267 /* select best values between sbr and sbr+1 */
268 if (tmp_diff > (baudrate - (clk / (tmp_osr * (tmp_sbr + 1))))) {
269 tmp_diff = baudrate - (clk / (tmp_osr * (tmp_sbr + 1)));
270 tmp_sbr++;
271 }
272
273 if (tmp_diff <= baud_diff) {
274 baud_diff = tmp_diff;
275 osr = tmp_osr;
276 sbr = tmp_sbr;
277 }
278 }
279
280 /*
281 * TODO: handle buadrate outside acceptable rate
282 * if (baudDiff > ((config->baudRate_Bps / 100) * 3))
283 * {
284 * Unacceptable baud rate difference of more than 3%
285 * return kStatus_LPUART_BaudrateNotSupport;
286 * }
287 */
288 tmp = in_le32(&base->baud);
289
290 if ((osr > 3) && (osr < 8))
291 tmp |= LPUART_BAUD_BOTHEDGE_MASK;
292
293 tmp &= ~LPUART_BAUD_OSR_MASK;
294 tmp |= LPUART_BAUD_OSR(osr-1);
295
296 tmp &= ~LPUART_BAUD_SBR_MASK;
297 tmp |= LPUART_BAUD_SBR(sbr);
298
299 /* explicitly disable 10 bit mode & set 1 stop bit */
300 tmp &= ~(LPUART_BAUD_M10_MASK | LPUART_BAUD_SBNS_MASK);
301
302 out_le32(&base->baud, tmp);
303 }
304
_lpuart32_serial_setbrg(struct udevice * dev,int baudrate)305 static void _lpuart32_serial_setbrg(struct udevice *dev,
306 int baudrate)
307 {
308 struct lpuart_serial_plat *plat = dev_get_plat(dev);
309 struct lpuart_fsl_reg32 *base = plat->reg;
310 u32 clk;
311 u32 sbr;
312 int ret;
313
314 if (CONFIG_IS_ENABLED(CLK)) {
315 ret = get_lpuart_clk_rate(dev, &clk);
316 if (ret)
317 return;
318 } else {
319 clk = get_lpuart_clk();
320 }
321
322 sbr = (clk / (16 * baudrate));
323
324 /* place adjustment later - n/32 BRFA */
325 lpuart_write32(plat->flags, &base->baud, sbr);
326 }
327
_lpuart32_serial_getc(struct lpuart_serial_plat * plat)328 static int _lpuart32_serial_getc(struct lpuart_serial_plat *plat)
329 {
330 struct lpuart_fsl_reg32 *base = plat->reg;
331 u32 stat, val;
332
333 lpuart_read32(plat->flags, &base->stat, &stat);
334 while ((stat & STAT_RDRF) == 0) {
335 lpuart_write32(plat->flags, &base->stat, STAT_FLAGS);
336 WATCHDOG_RESET();
337 lpuart_read32(plat->flags, &base->stat, &stat);
338 }
339
340 lpuart_read32(plat->flags, &base->data, &val);
341
342 lpuart_read32(plat->flags, &base->stat, &stat);
343 if (stat & STAT_OR)
344 lpuart_write32(plat->flags, &base->stat, STAT_OR);
345
346 return val & 0x3ff;
347 }
348
_lpuart32_serial_putc(struct lpuart_serial_plat * plat,const char c)349 static void _lpuart32_serial_putc(struct lpuart_serial_plat *plat,
350 const char c)
351 {
352 struct lpuart_fsl_reg32 *base = plat->reg;
353 u32 stat;
354
355 if (c == '\n')
356 serial_putc('\r');
357
358 while (true) {
359 lpuart_read32(plat->flags, &base->stat, &stat);
360
361 if ((stat & STAT_TDRE))
362 break;
363
364 WATCHDOG_RESET();
365 }
366
367 lpuart_write32(plat->flags, &base->data, c);
368 }
369
370 /* Test whether a character is in the RX buffer */
_lpuart32_serial_tstc(struct lpuart_serial_plat * plat)371 static int _lpuart32_serial_tstc(struct lpuart_serial_plat *plat)
372 {
373 struct lpuart_fsl_reg32 *base = plat->reg;
374 u32 water;
375
376 lpuart_read32(plat->flags, &base->water, &water);
377
378 if ((water >> 24) == 0)
379 return 0;
380
381 return 1;
382 }
383
384 /*
385 * Initialise the serial port with the given baudrate. The settings
386 * are always 8 data bits, no parity, 1 stop bit, no start bits.
387 */
_lpuart32_serial_init(struct udevice * dev)388 static int _lpuart32_serial_init(struct udevice *dev)
389 {
390 struct lpuart_serial_plat *plat = dev_get_plat(dev);
391 struct lpuart_fsl_reg32 *base = (struct lpuart_fsl_reg32 *)plat->reg;
392 u32 val, tx_fifo_size;
393
394 lpuart_read32(plat->flags, &base->ctrl, &val);
395 val &= ~CTRL_RE;
396 val &= ~CTRL_TE;
397 lpuart_write32(plat->flags, &base->ctrl, val);
398
399 lpuart_write32(plat->flags, &base->modir, 0);
400
401 lpuart_read32(plat->flags, &base->fifo, &val);
402 tx_fifo_size = (val & FIFO_TXSIZE_MASK) >> FIFO_TXSIZE_OFF;
403 /* Set the TX water to half of FIFO size */
404 if (tx_fifo_size > 1)
405 tx_fifo_size = tx_fifo_size >> 1;
406
407 /* Set RX water to 0, to be triggered by any receive data */
408 lpuart_write32(plat->flags, &base->water,
409 (tx_fifo_size << WATER_TXWATER_OFF));
410
411 /* Enable TX and RX FIFO */
412 val |= (FIFO_TXFE | FIFO_RXFE | FIFO_TXFLUSH | FIFO_RXFLUSH);
413 lpuart_write32(plat->flags, &base->fifo, val);
414
415 lpuart_write32(plat->flags, &base->match, 0);
416
417 if (plat->devtype == DEV_MX7ULP || plat->devtype == DEV_IMX8 ||
418 plat->devtype == DEV_IMXRT) {
419 _lpuart32_serial_setbrg_7ulp(dev, gd->baudrate);
420 } else {
421 /* provide data bits, parity, stop bit, etc */
422 _lpuart32_serial_setbrg(dev, gd->baudrate);
423 }
424
425 lpuart_write32(plat->flags, &base->ctrl, CTRL_RE | CTRL_TE);
426
427 return 0;
428 }
429
lpuart_serial_setbrg(struct udevice * dev,int baudrate)430 static int lpuart_serial_setbrg(struct udevice *dev, int baudrate)
431 {
432 struct lpuart_serial_plat *plat = dev_get_plat(dev);
433
434 if (is_lpuart32(dev)) {
435 if (plat->devtype == DEV_MX7ULP || plat->devtype == DEV_IMX8 ||
436 plat->devtype == DEV_IMXRT)
437 _lpuart32_serial_setbrg_7ulp(dev, baudrate);
438 else
439 _lpuart32_serial_setbrg(dev, baudrate);
440 } else {
441 _lpuart_serial_setbrg(dev, baudrate);
442 }
443
444 return 0;
445 }
446
lpuart_serial_getc(struct udevice * dev)447 static int lpuart_serial_getc(struct udevice *dev)
448 {
449 struct lpuart_serial_plat *plat = dev_get_plat(dev);
450
451 if (is_lpuart32(dev))
452 return _lpuart32_serial_getc(plat);
453
454 return _lpuart_serial_getc(plat);
455 }
456
lpuart_serial_putc(struct udevice * dev,const char c)457 static int lpuart_serial_putc(struct udevice *dev, const char c)
458 {
459 struct lpuart_serial_plat *plat = dev_get_plat(dev);
460
461 if (is_lpuart32(dev))
462 _lpuart32_serial_putc(plat, c);
463 else
464 _lpuart_serial_putc(plat, c);
465
466 return 0;
467 }
468
lpuart_serial_pending(struct udevice * dev,bool input)469 static int lpuart_serial_pending(struct udevice *dev, bool input)
470 {
471 struct lpuart_serial_plat *plat = dev_get_plat(dev);
472 struct lpuart_fsl *reg = plat->reg;
473 struct lpuart_fsl_reg32 *reg32 = plat->reg;
474 u32 stat;
475
476 if (is_lpuart32(dev)) {
477 if (input) {
478 return _lpuart32_serial_tstc(plat);
479 } else {
480 lpuart_read32(plat->flags, ®32->stat, &stat);
481 return stat & STAT_TDRE ? 0 : 1;
482 }
483 }
484
485 if (input)
486 return _lpuart_serial_tstc(plat);
487 else
488 return __raw_readb(®->us1) & US1_TDRE ? 0 : 1;
489 }
490
lpuart_serial_probe(struct udevice * dev)491 static int lpuart_serial_probe(struct udevice *dev)
492 {
493 #if CONFIG_IS_ENABLED(CLK)
494 struct clk per_clk;
495 int ret;
496
497 ret = clk_get_by_name(dev, "per", &per_clk);
498 if (!ret) {
499 ret = clk_enable(&per_clk);
500 if (ret) {
501 dev_err(dev, "Failed to get per clk: %d\n", ret);
502 return ret;
503 }
504 } else {
505 debug("%s: Failed to get per clk: %d\n", __func__, ret);
506 }
507 #endif
508
509 if (is_lpuart32(dev))
510 return _lpuart32_serial_init(dev);
511 else
512 return _lpuart_serial_init(dev);
513 }
514
lpuart_serial_of_to_plat(struct udevice * dev)515 static int lpuart_serial_of_to_plat(struct udevice *dev)
516 {
517 struct lpuart_serial_plat *plat = dev_get_plat(dev);
518 const void *blob = gd->fdt_blob;
519 int node = dev_of_offset(dev);
520 fdt_addr_t addr;
521
522 addr = dev_read_addr(dev);
523 if (addr == FDT_ADDR_T_NONE)
524 return -EINVAL;
525
526 plat->reg = (void *)addr;
527 plat->flags = dev_get_driver_data(dev);
528
529 if (fdtdec_get_bool(blob, node, "little-endian"))
530 plat->flags &= ~LPUART_FLAG_REGMAP_ENDIAN_BIG;
531
532 if (!fdt_node_check_compatible(blob, node, "fsl,ls1021a-lpuart"))
533 plat->devtype = DEV_LS1021A;
534 else if (!fdt_node_check_compatible(blob, node, "fsl,imx7ulp-lpuart"))
535 plat->devtype = DEV_MX7ULP;
536 else if (!fdt_node_check_compatible(blob, node, "fsl,vf610-lpuart"))
537 plat->devtype = DEV_VF610;
538 else if (!fdt_node_check_compatible(blob, node, "fsl,imx8qm-lpuart"))
539 plat->devtype = DEV_IMX8;
540 else if (!fdt_node_check_compatible(blob, node, "fsl,imxrt-lpuart"))
541 plat->devtype = DEV_IMXRT;
542
543 return 0;
544 }
545
546 static const struct dm_serial_ops lpuart_serial_ops = {
547 .putc = lpuart_serial_putc,
548 .pending = lpuart_serial_pending,
549 .getc = lpuart_serial_getc,
550 .setbrg = lpuart_serial_setbrg,
551 };
552
553 static const struct udevice_id lpuart_serial_ids[] = {
554 { .compatible = "fsl,ls1021a-lpuart", .data =
555 LPUART_FLAG_REGMAP_32BIT_REG | LPUART_FLAG_REGMAP_ENDIAN_BIG },
556 { .compatible = "fsl,imx7ulp-lpuart",
557 .data = LPUART_FLAG_REGMAP_32BIT_REG },
558 { .compatible = "fsl,vf610-lpuart"},
559 { .compatible = "fsl,imx8qm-lpuart",
560 .data = LPUART_FLAG_REGMAP_32BIT_REG },
561 { .compatible = "fsl,imxrt-lpuart",
562 .data = LPUART_FLAG_REGMAP_32BIT_REG },
563 { }
564 };
565
566 U_BOOT_DRIVER(serial_lpuart) = {
567 .name = "serial_lpuart",
568 .id = UCLASS_SERIAL,
569 .of_match = lpuart_serial_ids,
570 .of_to_plat = lpuart_serial_of_to_plat,
571 .plat_auto = sizeof(struct lpuart_serial_plat),
572 .probe = lpuart_serial_probe,
573 .ops = &lpuart_serial_ops,
574 };
575