1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
4 */
5
6/dts-v1/;
7
8#include "k3-j7200.dtsi"
9
10/ {
11	memory@80000000 {
12		device_type = "memory";
13		/* 4G RAM */
14		reg = <0x00 0x80000000 0x00 0x80000000>,
15		      <0x08 0x80000000 0x00 0x80000000>;
16	};
17
18	reserved_memory: reserved-memory {
19		#address-cells = <2>;
20		#size-cells = <2>;
21		ranges;
22
23		secure_ddr: optee@9e800000 {
24			reg = <0x00 0x9e800000 0x00 0x01800000>;
25			alignment = <0x1000>;
26			no-map;
27		};
28	};
29};
30
31&wkup_pmx0 {
32	mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-pins-default {
33		pinctrl-single,pins = <
34			J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* (B6) MCU_OSPI0_CLK.MCU_HYPERBUS0_CK */
35			J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* (C8) MCU_OSPI0_LBCLKO.MCU_HYPERBUS0_CKn */
36			J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 1) /* (D6) MCU_OSPI0_CSn0.MCU_HYPERBUS0_CSn0 */
37			J721E_WKUP_IOPAD(0x30, PIN_OUTPUT, 1) /* (D7) MCU_OSPI0_CSn1.MCU_HYPERBUS0_RESETn */
38			J721E_WKUP_IOPAD(0x8, PIN_INPUT, 1) /* (B7) MCU_OSPI0_DQS.MCU_HYPERBUS0_RWDS */
39			J721E_WKUP_IOPAD(0xc, PIN_INPUT, 1) /* (D8) MCU_OSPI0_D0.MCU_HYPERBUS0_DQ0 */
40			J721E_WKUP_IOPAD(0x10, PIN_INPUT, 1) /* (C7) MCU_OSPI0_D1.MCU_HYPERBUS0_DQ1 */
41			J721E_WKUP_IOPAD(0x14, PIN_INPUT, 1) /* (C5) MCU_OSPI0_D2.MCU_HYPERBUS0_DQ2 */
42			J721E_WKUP_IOPAD(0x18, PIN_INPUT, 1) /* (A5) MCU_OSPI0_D3.MCU_HYPERBUS0_DQ3 */
43			J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 1) /* (A6) MCU_OSPI0_D4.MCU_HYPERBUS0_DQ4 */
44			J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* (B8) MCU_OSPI0_D5.MCU_HYPERBUS0_DQ5 */
45			J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* (A8) MCU_OSPI0_D6.MCU_HYPERBUS0_DQ6 */
46			J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (A7) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */
47		>;
48	};
49};
50
51&main_pmx0 {
52	main_i2c0_pins_default: main-i2c0-pins-default {
53		pinctrl-single,pins = <
54			J721E_IOPAD(0xd4, PIN_INPUT_PULLUP, 0) /* (V3) I2C0_SCL */
55			J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA */
56		>;
57	};
58};
59
60&hbmc {
61	/* OSPI and HBMC are muxed inside FSS, Bootloader will enable
62	 * appropriate node based on board detection
63	 */
64	status = "disabled";
65	pinctrl-names = "default";
66	pinctrl-0 = <&mcu_fss0_hpb0_pins_default>;
67	ranges = <0x00 0x00 0x05 0x00000000 0x4000000>, /* 64MB Flash on CS0 */
68		 <0x01 0x00 0x05 0x04000000 0x800000>; /* 8MB RAM on CS1 */
69
70	flash@0,0 {
71		compatible = "cypress,hyperflash", "cfi-flash";
72		reg = <0x00 0x00 0x4000000>;
73	};
74};
75
76&mailbox0_cluster0 {
77	interrupts = <436>;
78
79	mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
80		ti,mbox-rx = <0 0 0>;
81		ti,mbox-tx = <1 0 0>;
82	};
83
84	mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
85		ti,mbox-rx = <2 0 0>;
86		ti,mbox-tx = <3 0 0>;
87	};
88};
89
90&mailbox0_cluster1 {
91	interrupts = <432>;
92
93	mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
94		ti,mbox-rx = <0 0 0>;
95		ti,mbox-tx = <1 0 0>;
96	};
97
98	mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
99		ti,mbox-rx = <2 0 0>;
100		ti,mbox-tx = <3 0 0>;
101	};
102};
103
104&mailbox0_cluster2 {
105	status = "disabled";
106};
107
108&mailbox0_cluster3 {
109	status = "disabled";
110};
111
112&mailbox0_cluster4 {
113	status = "disabled";
114};
115
116&mailbox0_cluster5 {
117	status = "disabled";
118};
119
120&mailbox0_cluster6 {
121	status = "disabled";
122};
123
124&mailbox0_cluster7 {
125	status = "disabled";
126};
127
128&mailbox0_cluster8 {
129	status = "disabled";
130};
131
132&mailbox0_cluster9 {
133	status = "disabled";
134};
135
136&mailbox0_cluster10 {
137	status = "disabled";
138};
139
140&mailbox0_cluster11 {
141	status = "disabled";
142};
143
144&main_i2c0 {
145	pinctrl-names = "default";
146	pinctrl-0 = <&main_i2c0_pins_default>;
147	clock-frequency = <400000>;
148
149	exp_som: gpio@21 {
150		compatible = "ti,tca6408";
151		reg = <0x21>;
152		gpio-controller;
153		#gpio-cells = <2>;
154		gpio-line-names = "USB2.0_MUX_SEL", "CANUART_MUX1_SEL0",
155				  "CANUART_MUX2_SEL0", "CANUART_MUX_SEL1",
156				  "UART/LIN_MUX_SEL", "TRC_D17/AUDIO_REFCLK_SEL",
157				  "GPIO_LIN_EN", "CAN_STB";
158	};
159};
160