1/*
2 * Copyright (C) 2018 MediaTek Inc.
3 * Author: Ryder Lee <ryder.lee@mediatek.com>
4 *
5 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 */
7
8#include <dt-bindings/clock/mt7623-clk.h>
9#include <dt-bindings/gpio/gpio.h>
10#include <dt-bindings/interrupt-controller/irq.h>
11#include <dt-bindings/interrupt-controller/arm-gic.h>
12#include <dt-bindings/phy/phy.h>
13#include <dt-bindings/power/mt7623-power.h>
14#include <dt-bindings/reset/mt7623-reset.h>
15#include "skeleton.dtsi"
16
17/ {
18	compatible = "mediatek,mt7623";
19	interrupt-parent = <&sysirq>;
20	#address-cells = <1>;
21	#size-cells = <1>;
22
23	cpus {
24		#address-cells = <1>;
25		#size-cells = <0>;
26		enable-method = "mediatek,mt6589-smp";
27
28		cpu0: cpu@0 {
29			device_type = "cpu";
30			compatible = "arm,cortex-a7";
31			reg = <0x0>;
32			clocks = <&infracfg CLK_INFRA_CPUSEL>,
33				 <&apmixedsys CLK_APMIXED_MAINPLL>;
34			clock-names = "cpu", "intermediate";
35			clock-frequency = <1300000000>;
36		};
37
38		cpu1: cpu@1 {
39			device_type = "cpu";
40			compatible = "arm,cortex-a7";
41			reg = <0x1>;
42			clocks = <&infracfg CLK_INFRA_CPUSEL>,
43				 <&apmixedsys CLK_APMIXED_MAINPLL>;
44			clock-names = "cpu", "intermediate";
45			clock-frequency = <1300000000>;
46		};
47
48		cpu2: cpu@2 {
49			device_type = "cpu";
50			compatible = "arm,cortex-a7";
51			reg = <0x2>;
52			clocks = <&infracfg CLK_INFRA_CPUSEL>,
53				 <&apmixedsys CLK_APMIXED_MAINPLL>;
54			clock-names = "cpu", "intermediate";
55			clock-frequency = <1300000000>;
56		};
57
58		cpu3: cpu@3 {
59			device_type = "cpu";
60			compatible = "arm,cortex-a7";
61			reg = <0x3>;
62			clocks = <&infracfg CLK_INFRA_CPUSEL>,
63				 <&apmixedsys CLK_APMIXED_MAINPLL>;
64			clock-names = "cpu", "intermediate";
65			clock-frequency = <1300000000>;
66		};
67	};
68
69	system_clk: dummy13m {
70		compatible = "fixed-clock";
71		clock-frequency = <13000000>;
72		#clock-cells = <0>;
73	};
74
75	rtc32k: oscillator-1 {
76		compatible = "fixed-clock";
77		#clock-cells = <0>;
78		clock-frequency = <32000>;
79		clock-output-names = "rtc32k";
80	};
81
82	clk26m: oscillator-0 {
83		compatible = "fixed-clock";
84		#clock-cells = <0>;
85		clock-frequency = <26000000>;
86		clock-output-names = "clk26m";
87	};
88
89	timer {
90		compatible = "arm,armv7-timer";
91		interrupt-parent = <&gic>;
92		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
93			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
94			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
95			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
96		clock-frequency = <13000000>;
97		arm,cpu-registers-not-fw-configured;
98	};
99
100	topckgen: clock-controller@10000000 {
101		compatible = "mediatek,mt7623-topckgen";
102		reg = <0x10000000 0x1000>;
103		#clock-cells = <1>;
104	};
105
106	infracfg: syscon@10001000 {
107		compatible = "mediatek,mt7623-infracfg", "syscon";
108		reg = <0x10001000 0x1000>;
109		#clock-cells = <1>;
110	};
111
112	pericfg: syscon@10003000 {
113		compatible = "mediatek,mt7623-pericfg", "syscon";
114		reg = <0x10003000 0x1000>;
115		#clock-cells = <1>;
116	};
117
118	pinctrl: pinctrl@10005000 {
119		compatible = "mediatek,mt7623-pinctrl";
120		reg = <0x10005000 0x1000>;
121
122		gpio: gpio-controller {
123			gpio-controller;
124			#gpio-cells = <2>;
125		};
126	};
127
128	scpsys: scpsys@10006000 {
129		compatible = "mediatek,mt7623-scpsys";
130		#power-domain-cells = <1>;
131		reg = <0x10006000 0x1000>;
132		infracfg = <&infracfg>;
133		clocks = <&topckgen CLK_TOP_MM_SEL>,
134			 <&topckgen CLK_TOP_MFG_SEL>,
135			 <&topckgen CLK_TOP_ETHIF_SEL>;
136		clock-names = "mm", "mfg", "ethif";
137	};
138
139	watchdog: watchdog@10007000 {
140		compatible = "mediatek,wdt";
141		reg = <0x10007000 0x100>;
142	};
143
144	wdt-reboot {
145		compatible = "wdt-reboot";
146		wdt = <&watchdog>;
147	};
148
149	timer0: timer@10008000 {
150		compatible = "mediatek,timer";
151		reg = <0x10008000 0x80>;
152		interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
153		clocks = <&system_clk>;
154		clock-names = "system-clk";
155	};
156
157	sysirq: interrupt-controller@10200100 {
158		compatible = "mediatek,sysirq";
159		interrupt-controller;
160		#interrupt-cells = <3>;
161		interrupt-parent = <&gic>;
162		reg = <0x10200100 0x1c>;
163	};
164
165	apmixedsys: clock-controller@10209000 {
166		compatible = "mediatek,mt7623-apmixedsys";
167		reg = <0x10209000 0x1000>;
168		#clock-cells = <1>;
169	};
170
171	gic: interrupt-controller@10211000 {
172		compatible = "arm,cortex-a7-gic";
173		interrupt-controller;
174		#interrupt-cells = <3>;
175		interrupt-parent = <&gic>;
176		reg = <0x10211000 0x1000>,
177		      <0x10212000 0x1000>,
178		      <0x10214000 0x2000>,
179		      <0x10216000 0x2000>;
180	};
181
182	uart0: serial@11002000 {
183		compatible = "mediatek,hsuart";
184		reg = <0x11002000 0x400>;
185		reg-shift = <2>;
186		interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
187		clocks = <&topckgen CLK_TOP_UART_SEL>,
188			 <&pericfg CLK_PERI_UART0>;
189		clock-names = "baud", "bus";
190		status = "disabled";
191	};
192
193	uart1: serial@11003000 {
194		compatible = "mediatek,hsuart";
195		reg = <0x11003000 0x400>;
196		reg-shift = <2>;
197		interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
198		clocks = <&topckgen CLK_TOP_UART_SEL>,
199			 <&pericfg CLK_PERI_UART1>;
200		clock-names = "baud", "bus";
201		status = "disabled";
202	};
203
204	uart2: serial@11004000 {
205		compatible = "mediatek,hsuart";
206		reg = <0x11004000 0x400>;
207		reg-shift = <2>;
208		interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
209		clocks = <&topckgen CLK_TOP_UART_SEL>,
210			 <&pericfg CLK_PERI_UART2>;
211		clock-names = "baud", "bus";
212		status = "disabled";
213	};
214
215	uart3: serial@11005000 {
216		compatible = "mediatek,hsuart";
217		reg = <0x11005000 0x400>;
218		reg-shift = <2>;
219		interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
220		clocks = <&topckgen CLK_TOP_UART_SEL>,
221			 <&pericfg CLK_PERI_UART3>;
222		clock-names = "baud", "bus";
223		status = "disabled";
224	};
225
226	mmc0: mmc@11230000 {
227		compatible = "mediatek,mt7623-mmc";
228		reg = <0x11230000 0x1000>;
229		interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;
230		clocks = <&pericfg CLK_PERI_MSDC30_0>,
231			 <&topckgen CLK_TOP_MSDC30_0_SEL>;
232		clock-names = "source", "hclk";
233		status = "disabled";
234	};
235
236	mmc1: mmc@11240000 {
237		compatible = "mediatek,mt7623-mmc";
238		reg = <0x11240000 0x1000>;
239		interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_LOW>;
240		clocks = <&pericfg CLK_PERI_MSDC30_1>,
241			 <&topckgen CLK_TOP_MSDC30_1_SEL>;
242		clock-names = "source", "hclk";
243		status = "disabled";
244	};
245
246	hifsys: syscon@1a000000 {
247		compatible = "mediatek,mt7623-hifsys", "syscon";
248		reg = <0x1a000000 0x1000>;
249		#clock-cells = <1>;
250		#reset-cells = <1>;
251	};
252
253	pcie: pcie@1a140000 {
254		compatible = "mediatek,mt7623-pcie";
255		device_type = "pci";
256		reg = <0x1a140000 0x1000>, /* PCIe shared registers */
257		      <0x1a142000 0x1000>, /* Port0 registers */
258		      <0x1a143000 0x1000>, /* Port1 registers */
259		      <0x1a144000 0x1000>; /* Port2 registers */
260		reg-names = "subsys", "port0", "port1", "port2";
261		#address-cells = <3>;
262		#size-cells = <2>;
263		#interrupt-cells = <1>;
264		interrupt-map-mask = <0xf800 0 0 0>;
265		interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
266				<0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,
267				<0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
268		clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
269			 <&hifsys CLK_HIFSYS_PCIE0>,
270			 <&hifsys CLK_HIFSYS_PCIE1>,
271			 <&hifsys CLK_HIFSYS_PCIE2>;
272		clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2";
273		resets = <&hifsys HIFSYS_PCIE0_RST>,
274			 <&hifsys HIFSYS_PCIE1_RST>,
275			 <&hifsys HIFSYS_PCIE2_RST>;
276		reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2";
277		phys = <&pcie0_port PHY_TYPE_PCIE>,
278		       <&pcie1_port PHY_TYPE_PCIE>,
279		       <&u3port1 PHY_TYPE_PCIE>;
280		phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2";
281		power-domains = <&scpsys MT7623_POWER_DOMAIN_HIF>;
282		bus-range = <0x00 0xff>;
283		status = "disabled";
284		ranges = <0x81000000 0 0x1a160000 0x1a160000 0 0x00010000
285			  0x83000000 0 0x60000000 0x60000000 0 0x10000000>;
286
287		pcie@0,0 {
288			reg = <0x0000 0 0 0 0>;
289			#address-cells = <3>;
290			#size-cells = <2>;
291			#interrupt-cells = <1>;
292			interrupt-map-mask = <0 0 0 0>;
293			interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
294			ranges;
295			status = "disabled";
296		};
297
298		pcie@1,0 {
299			reg = <0x0800 0 0 0 0>;
300			#address-cells = <3>;
301			#size-cells = <2>;
302			#interrupt-cells = <1>;
303			interrupt-map-mask = <0 0 0 0>;
304			interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
305			ranges;
306			status = "disabled";
307		};
308
309		pcie@2,0 {
310			reg = <0x1000 0 0 0 0>;
311			#address-cells = <3>;
312			#size-cells = <2>;
313			#interrupt-cells = <1>;
314			interrupt-map-mask = <0 0 0 0>;
315			interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
316			ranges;
317			status = "disabled";
318		};
319	};
320
321	pcie0_phy: pcie-phy@1a149000 {
322		compatible = "mediatek,generic-tphy-v1";
323		reg = <0x1a149000 0x0700>;
324		#address-cells = <1>;
325		#size-cells = <1>;
326		ranges;
327		status = "disabled";
328
329		pcie0_port: pcie-phy@1a149900 {
330			reg = <0x1a149900 0x0700>;
331			clocks = <&clk26m>;
332			clock-names = "ref";
333			#phy-cells = <1>;
334			status = "okay";
335		};
336	};
337
338	pcie1_phy: pcie-phy@1a14a000 {
339		compatible = "mediatek,generic-tphy-v1";
340		reg = <0x1a14a000 0x0700>;
341		#address-cells = <1>;
342		#size-cells = <1>;
343		ranges;
344		status = "disabled";
345
346		pcie1_port: pcie-phy@1a14a900 {
347			reg = <0x1a14a900 0x0700>;
348			clocks = <&clk26m>;
349			clock-names = "ref";
350			#phy-cells = <1>;
351			status = "okay";
352		};
353	};
354
355	usb1: usb@1a1c0000 {
356		compatible = "mediatek,mt7623-xhci", "mediatek,mtk-xhci";
357		reg = <0x1a1c0000 0x1000>, <0x1a1c4700 0x0100>;
358		reg-names = "mac", "ippc";
359		power-domains = <&scpsys MT7623_POWER_DOMAIN_HIF>;
360		clocks = <&hifsys CLK_HIFSYS_USB0PHY>, <&topckgen CLK_TOP_ETHIF_SEL>;
361		clock-names = "sys_ck", "ref_ck";
362		phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>;
363		status = "disabled";
364	};
365
366	u3phy1: usb-phy@1a1c4000 {
367		compatible = "mediatek,mt7623-tphy", "mediatek,generic-tphy-v1";
368
369		reg = <0x1a1c4000 0x0700>;
370		#address-cells = <1>;
371		#size-cells = <1>;
372		ranges;
373		status = "disabled";
374
375		u2port0: usb-phy@1a1c4800 {
376			reg = <0x1a1c4800 0x0100>;
377			#phy-cells = <1>;
378			clocks = <&topckgen CLK_TOP_USB_PHY48M>;
379			clock-names = "ref";
380		};
381
382		u3port0: usb-phy@1a1c4900 {
383			reg = <0x1a1c4900 0x0700>;
384			#phy-cells = <1>;
385			clocks = <&clk26m>;
386			clock-names = "ref";
387		};
388	};
389
390	usb2: usb@1a240000 {
391		compatible = "mediatek,mt7623-xhci", "mediatek,mtk-xhci";
392		reg = <0x1a240000 0x1000>, <0x1a244700 0x0100>;
393		reg-names = "mac", "ippc";
394		power-domains = <&scpsys MT7623_POWER_DOMAIN_HIF>;
395		clocks = <&hifsys CLK_HIFSYS_USB1PHY>, <&topckgen CLK_TOP_ETHIF_SEL>;
396		clock-names = "sys_ck", "ref_ck";
397		phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>;
398		status = "disabled";
399	};
400
401	u3phy2: usb-phy@1a244000 {
402		compatible = "mediatek,generic-tphy-v1";
403		reg = <0x1a244000 0x0700>;
404		#address-cells = <1>;
405		#size-cells = <1>;
406		ranges;
407		status = "disabled";
408
409		u2port1: usb-phy@1a244800 {
410			reg = <0x1a244800 0x0100>;
411			clocks = <&topckgen CLK_TOP_USB_PHY48M>;
412			clock-names = "ref";
413			#phy-cells = <1>;
414			status = "okay";
415		};
416
417		u3port1: usb-phy@1a244900 {
418			reg = <0x1a244900 0x0700>;
419			clocks = <&clk26m>;
420			clock-names = "ref";
421			#phy-cells = <1>;
422			status = "okay";
423		};
424	};
425
426	ethsys: syscon@1b000000 {
427		compatible = "mediatek,mt7623-ethsys", "syscon";
428		reg = <0x1b000000 0x1000>;
429		#clock-cells = <1>;
430		#reset-cells = <1>;
431	};
432
433	eth: ethernet@1b100000 {
434		compatible = "mediatek,mt7623-eth", "syscon";
435		reg = <0x1b100000 0x20000>;
436		clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
437			 <&ethsys CLK_ETHSYS_ESW>,
438			 <&ethsys CLK_ETHSYS_GP1>,
439			 <&ethsys CLK_ETHSYS_GP2>,
440			 <&apmixedsys CLK_APMIXED_TRGPLL>;
441		clock-names = "ethif", "esw", "gp1", "gp2", "trgpll";
442		power-domains = <&scpsys MT7623_POWER_DOMAIN_ETH>;
443		resets = <&ethsys ETHSYS_FE_RST>,
444			 <&ethsys ETHSYS_MCM_RST>;
445		reset-names = "fe", "mcm";
446		mediatek,ethsys = <&ethsys>;
447		status = "disabled";
448	};
449
450	pwm: pwm@11006000 {
451		compatible = "mediatek,mt7623-pwm";
452		reg = <0x11006000 0x1000>;
453		#clock-cells = <1>;
454		#pwm-cells = <2>;
455		clocks = <&topckgen CLK_TOP_PWM_SEL>,
456			 <&pericfg CLK_PERI_PWM>,
457			 <&pericfg CLK_PERI_PWM1>,
458			 <&pericfg CLK_PERI_PWM2>,
459			 <&pericfg CLK_PERI_PWM3>,
460			 <&pericfg CLK_PERI_PWM4>,
461			 <&pericfg CLK_PERI_PWM5>;
462		clock-names = "top", "main", "pwm1", "pwm2", "pwm3", "pwm4",
463			      "pwm5";
464		status = "disabled";
465	};
466};
467