1// SPDX-License-Identifier: GPL-2.0+
2
3#include <stm32f7-u-boot.dtsi>
4/{
5	chosen {
6		bootargs = "root=/dev/ram rdinit=/linuxrc";
7	};
8
9	aliases {
10		/* Aliases for gpios so as to use sequence */
11		gpio0 = &gpioa;
12		gpio1 = &gpiob;
13		gpio2 = &gpioc;
14		gpio3 = &gpiod;
15		gpio4 = &gpioe;
16		gpio5 = &gpiof;
17		gpio6 = &gpiog;
18		gpio7 = &gpioh;
19		gpio8 = &gpioi;
20		gpio9 = &gpioj;
21		gpio10 = &gpiok;
22		mmc0 = &sdio1;
23		spi0 = &qspi;
24	};
25
26	backlight: backlight {
27		compatible = "gpio-backlight";
28		gpios = <&gpiok 3 0>;
29		status = "okay";
30	};
31
32	button1 {
33		compatible = "st,button1";
34		button-gpio = <&gpioi 11 0>;
35	};
36
37	led1 {
38		compatible = "st,led1";
39		led-gpio = <&gpioi 1 0>;
40	};
41
42	panel-rgb@0 {
43		compatible = "simple-panel";
44		backlight = <&backlight>;
45		enable-gpios = <&gpioi 12 0>;
46		status = "okay";
47
48		display-timings {
49			timing@0 {
50				clock-frequency = <9000000>;
51				hactive = <480>;
52				vactive = <272>;
53				hfront-porch = <2>;
54				hback-porch = <2>;
55				hsync-len = <41>;
56				vfront-porch = <2>;
57				vback-porch = <2>;
58				vsync-len = <10>;
59				hsync-active = <0>;
60				vsync-active = <0>;
61				de-active = <0>;
62				pixelclk-active = <1>;
63			};
64		};
65	};
66
67	soc {
68		ltdc: display-controller@40016800 {
69			compatible = "st,stm32-ltdc";
70			reg = <0x40016800 0x200>;
71			resets = <&rcc STM32F7_APB2_RESET(LTDC)>;
72			clocks = <&rcc 0 STM32F7_APB2_CLOCK(LTDC)>;
73			pinctrl-0 = <&ltdc_pins>;
74
75			status = "okay";
76			u-boot,dm-pre-reloc;
77		};
78	};
79};
80
81&fmc {
82	/* Memory configuration from sdram datasheet MT48LC_4M32_B2B5-6A */
83	bank1: bank@0 {
84		u-boot,dm-pre-reloc;
85		st,sdram-control = /bits/ 8 <NO_COL_8
86					     NO_ROW_12
87					     MWIDTH_16
88					     BANKS_4
89					     CAS_3
90					     SDCLK_2
91					     RD_BURST_EN
92					     RD_PIPE_DL_0>;
93		st,sdram-timing = /bits/ 8 <TMRD_2
94					    TXSR_6
95					    TRAS_4
96					    TRC_6
97					    TWR_2
98					    TRP_2
99					    TRCD_2>;
100		/* refcount = (64msec/total_row_sdram)*freq - 20 */
101		st,sdram-refcount = < 1542 >;
102	};
103};
104
105&pinctrl {
106	ethernet_mii: mii@0 {
107		pins {
108			pinmux = <STM32_PINMUX('G',13, AF11)>, /* ETH_RMII_TXD0 */
109				 <STM32_PINMUX('G',14, AF11)>, /* ETH_RMII_TXD1 */
110				 <STM32_PINMUX('G',11, AF11)>, /* ETH_RMII_TX_EN */
111				 <STM32_PINMUX('A', 2, AF11)>, /* ETH_MDIO */
112				 <STM32_PINMUX('C', 1, AF11)>, /* ETH_MDC */
113				 <STM32_PINMUX('A', 1, AF11)>, /* ETH_RMII_REF_CLK */
114				 <STM32_PINMUX('A', 7, AF11)>, /* ETH_RMII_CRS_DV */
115				 <STM32_PINMUX('C', 4, AF11)>, /* ETH_RMII_RXD0 */
116				 <STM32_PINMUX('C', 5, AF11)>; /* ETH_RMII_RXD1 */
117			slew-rate = <2>;
118		};
119	};
120
121	fmc_pins: fmc@0 {
122		pins {
123			pinmux = <STM32_PINMUX('D',10, AF12)>, /* D15 */
124				 <STM32_PINMUX('D', 9, AF12)>, /* D14 */
125				 <STM32_PINMUX('D', 8, AF12)>, /* D13 */
126				 <STM32_PINMUX('E',15, AF12)>, /* D12 */
127				 <STM32_PINMUX('E',14, AF12)>, /* D11 */
128				 <STM32_PINMUX('E',13, AF12)>, /* D10 */
129				 <STM32_PINMUX('E',12, AF12)>, /* D9 */
130				 <STM32_PINMUX('E',11, AF12)>, /* D8 */
131				 <STM32_PINMUX('E',10, AF12)>, /* D7 */
132				 <STM32_PINMUX('E', 9, AF12)>, /* D6 */
133				 <STM32_PINMUX('E', 8, AF12)>, /* D5 */
134				 <STM32_PINMUX('E', 7, AF12)>, /* D4 */
135				 <STM32_PINMUX('D', 1, AF12)>, /* D3 */
136				 <STM32_PINMUX('D', 0, AF12)>, /* D2 */
137				 <STM32_PINMUX('D',15, AF12)>, /* D1 */
138				 <STM32_PINMUX('D',14, AF12)>, /* D0 */
139
140				 <STM32_PINMUX('E', 1, AF12)>, /* NBL1 */
141				 <STM32_PINMUX('E', 0, AF12)>, /* NBL0 */
142
143				 <STM32_PINMUX('G', 5, AF12)>, /* BA1 */
144				 <STM32_PINMUX('G', 4, AF12)>, /* BA0 */
145
146				 <STM32_PINMUX('G', 1, AF12)>, /* A11 */
147				 <STM32_PINMUX('G', 0, AF12)>, /* A10 */
148				 <STM32_PINMUX('F',15, AF12)>, /* A9 */
149				 <STM32_PINMUX('F',14, AF12)>, /* A8 */
150				 <STM32_PINMUX('F',13, AF12)>, /* A7 */
151				 <STM32_PINMUX('F',12, AF12)>, /* A6 */
152				 <STM32_PINMUX('F', 5, AF12)>, /* A5 */
153				 <STM32_PINMUX('F', 4, AF12)>, /* A4 */
154				 <STM32_PINMUX('F', 3, AF12)>, /* A3 */
155				 <STM32_PINMUX('F', 2, AF12)>, /* A2 */
156				 <STM32_PINMUX('F', 1, AF12)>, /* A1 */
157				 <STM32_PINMUX('F', 0, AF12)>, /* A0 */
158
159				 <STM32_PINMUX('H', 3, AF12)>, /* SDNE0 */
160				 <STM32_PINMUX('H', 5, AF12)>, /* SDNWE */
161				 <STM32_PINMUX('F',11, AF12)>, /* SDNRAS */
162				 <STM32_PINMUX('G',15, AF12)>, /* SDNCAS */
163				 <STM32_PINMUX('C', 3, AF12)>, /* SDCKE0 */
164				 <STM32_PINMUX('G', 8, AF12)>; /* SDCLK> */
165			slew-rate = <2>;
166		};
167	};
168
169	ltdc_pins: ltdc@0 {
170		pins {
171			pinmux = <STM32_PINMUX('E', 4, AF14)>, /* B0 */
172				 <STM32_PINMUX('G',12, AF14)>, /* B4 */
173				 <STM32_PINMUX('I', 9, AF14)>, /* VSYNC */
174				 <STM32_PINMUX('I',10, AF14)>, /* HSYNC */
175				 <STM32_PINMUX('I',14, AF14)>, /* CLK */
176				 <STM32_PINMUX('I',15, AF14)>, /* R0 */
177				 <STM32_PINMUX('J', 0, AF14)>, /* R1 */
178				 <STM32_PINMUX('J', 1, AF14)>, /* R2 */
179				 <STM32_PINMUX('J', 2, AF14)>, /* R3 */
180				 <STM32_PINMUX('J', 3, AF14)>, /* R4 */
181				 <STM32_PINMUX('J', 4, AF14)>, /* R5 */
182				 <STM32_PINMUX('J', 5, AF14)>, /* R6 */
183				 <STM32_PINMUX('J', 6, AF14)>, /* R7 */
184				 <STM32_PINMUX('J', 7, AF14)>, /* G0 */
185				 <STM32_PINMUX('J', 8, AF14)>, /* G1 */
186				 <STM32_PINMUX('J', 9, AF14)>, /* G2 */
187				 <STM32_PINMUX('J',10, AF14)>, /* G3 */
188				 <STM32_PINMUX('J',11, AF14)>, /* G4 */
189				 <STM32_PINMUX('J',13, AF14)>, /* B1 */
190				 <STM32_PINMUX('J',14, AF14)>, /* B2 */
191				 <STM32_PINMUX('J',15, AF14)>, /* B3 */
192				 <STM32_PINMUX('K', 0, AF14)>, /* G5 */
193				 <STM32_PINMUX('K', 1, AF14)>, /* G6 */
194				 <STM32_PINMUX('K', 2, AF14)>, /* G7 */
195				 <STM32_PINMUX('K', 4, AF14)>, /* B5 */
196				 <STM32_PINMUX('K', 5, AF14)>, /* B6 */
197				 <STM32_PINMUX('K', 6, AF14)>, /* B7 */
198				 <STM32_PINMUX('K', 7, AF14)>; /* DE */
199			slew-rate = <2>;
200		};
201	};
202
203	qspi_pins: qspi@0 {
204		pins {
205			pinmux = <STM32_PINMUX('B', 2, AF9)>, /* CLK */
206				 <STM32_PINMUX('B', 6, AF10)>, /* BK1_NCS */
207				 <STM32_PINMUX('D',11, AF9)>, /* BK1_IO0 */
208				 <STM32_PINMUX('D',12, AF9)>, /* BK1_IO1 */
209				 <STM32_PINMUX('D',13, AF9)>, /* BK1_IO3 */
210				 <STM32_PINMUX('E', 2, AF9)>; /* BK1_IO2 */
211			slew-rate = <2>;
212		};
213	};
214
215	usart1_pins_b: usart1-1	{
216		u-boot,dm-pre-reloc;
217		pins1 {
218			u-boot,dm-pre-reloc;
219		};
220		pins2 {
221			u-boot,dm-pre-reloc;
222		};
223	};
224};
225
226&pwrcfg {
227	u-boot,dm-pre-reloc;
228};
229
230&qspi {
231	reg = <0xA0001000 0x1000>, <0x90000000 0x1000000>;
232	qflash0: n25q128a@0 {
233		#address-cells = <1>;
234		#size-cells = <1>;
235		compatible = "jedec,spi-nor";
236		spi-max-frequency = <108000000>;
237		spi-tx-bus-width = <4>;
238		spi-rx-bus-width = <4>;
239		reg = <0>;
240	};
241};
242