1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Xilinx CSE QSPI board DTS
4 *
5 * Copyright (C) 2015 - 2017 Xilinx, Inc.
6 */
7/dts-v1/;
8
9/ {
10	#address-cells = <1>;
11	#size-cells = <1>;
12	model = "Zynq CSE QSPI Board";
13	compatible = "xlnx,zynq-cse-qspi", "xlnx,zynq-7000";
14
15	aliases {
16		spi0 = &qspi;
17		serial0 = &dcc;
18	};
19
20	memory@fffc0000 {
21		device_type = "memory";
22		reg = <0xFFFC0000 0x40000>;
23	};
24
25	chosen {
26		stdout-path = "serial0:115200n8";
27	};
28
29	dcc: dcc {
30		compatible = "arm,dcc";
31		status = "disabled";
32		u-boot,dm-pre-reloc;
33	};
34
35	amba: amba {
36		u-boot,dm-pre-reloc;
37		compatible = "simple-bus";
38		#address-cells = <1>;
39		#size-cells = <1>;
40		interrupt-parent = <&intc>;
41		ranges;
42
43		intc: interrupt-controller@f8f01000 {
44			compatible = "arm,cortex-a9-gic";
45			#interrupt-cells = <3>;
46			interrupt-controller;
47			reg = <0xF8F01000 0x1000>,
48			      <0xF8F00100 0x100>;
49		};
50
51		qspi: spi@e000d000 {
52			clock-names = "ref_clk", "pclk";
53			clocks = <&clkc 10>, <&clkc 43>;
54			compatible = "xlnx,zynq-qspi-1.0";
55			status = "okay";
56			interrupt-parent = <&intc>;
57			interrupts = <0 19 4>;
58			reg = <0xe000d000 0x1000>;
59			#address-cells = <1>;
60			#size-cells = <0>;
61			num-cs = <1>;
62			flash0: flash@0 {
63				compatible = "n25q128a11";
64				reg = <0x0>;
65				spi-tx-bus-width = <1>;
66				spi-rx-bus-width = <4>;
67				spi-max-frequency = <50000000>;
68				#address-cells = <1>;
69				#size-cells = <1>;
70				partition@0 {
71					label = "qspi-fsbl-uboot";
72					reg = <0x0 0x100000>;
73				};
74				partition@100000 {
75					label = "qspi-linux";
76					reg = <0x100000 0x500000>;
77				};
78				partition@600000 {
79					label = "qspi-device-tree";
80					reg = <0x600000 0x20000>;
81				};
82				partition@620000 {
83					label = "qspi-rootfs";
84					reg = <0x620000 0x5E0000>;
85				};
86				partition@c00000 {
87					label = "qspi-bitstream";
88					reg = <0xC00000 0x400000>;
89				};
90			};
91		};
92
93		slcr: slcr@f8000000 {
94			u-boot,dm-pre-reloc;
95			#address-cells = <1>;
96			#size-cells = <1>;
97			compatible = "xlnx,zynq-slcr", "syscon", "simple-bus";
98			reg = <0xF8000000 0x1000>;
99			ranges;
100			clkc: clkc@100 {
101				#clock-cells = <1>;
102				compatible = "xlnx,ps7-clkc";
103				fclk-enable = <0xf>;
104				u-boot,dm-pre-reloc;
105				clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
106						"cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
107						"dci", "lqspi", "smc", "pcap", "gem0", "gem1",
108						"fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
109						"sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",
110						"dma", "usb0_aper", "usb1_aper", "gem0_aper",
111						"gem1_aper", "sdio0_aper", "sdio1_aper",
112						"spi0_aper", "spi1_aper", "can0_aper", "can1_aper",
113						"i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",
114						"gpio_aper", "lqspi_aper", "smc_aper", "swdt",
115						"dbg_trc", "dbg_apb";
116				reg = <0x100 0x100>;
117			};
118		};
119	};
120
121};
122
123&dcc {
124	status = "okay";
125};
126