1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * SPL specific code for Compulab CM-T335 board
4 *
5 * Board functions for Compulab CM-T335 board
6 *
7 * Copyright (C) 2013, Compulab Ltd - http://compulab.co.il/
8 *
9 * Author: Ilya Ledvich <ilya@compulab.co.il>
10 */
11
12 #include <common.h>
13 #include <cpu_func.h>
14 #include <errno.h>
15 #include <init.h>
16 #include <log.h>
17
18 #include <asm/arch/ddr_defs.h>
19 #include <asm/arch/clock.h>
20 #include <asm/arch/clocks_am33xx.h>
21 #include <asm/arch/sys_proto.h>
22 #include <asm/arch/hardware_am33xx.h>
23 #include <linux/sizes.h>
24
25 const struct ctrl_ioregs ioregs = {
26 .cm0ioctl = MT41J128MJT125_IOCTRL_VALUE,
27 .cm1ioctl = MT41J128MJT125_IOCTRL_VALUE,
28 .cm2ioctl = MT41J128MJT125_IOCTRL_VALUE,
29 .dt0ioctl = MT41J128MJT125_IOCTRL_VALUE,
30 .dt1ioctl = MT41J128MJT125_IOCTRL_VALUE,
31 };
32
33 static const struct ddr_data ddr3_data = {
34 .datardsratio0 = MT41J128MJT125_RD_DQS,
35 .datawdsratio0 = MT41J128MJT125_WR_DQS,
36 .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE,
37 .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA,
38 };
39
40 static const struct cmd_control ddr3_cmd_ctrl_data = {
41 .cmd0csratio = MT41J128MJT125_RATIO,
42 .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT,
43
44 .cmd1csratio = MT41J128MJT125_RATIO,
45 .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT,
46
47 .cmd2csratio = MT41J128MJT125_RATIO,
48 .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT,
49 };
50
51 static struct emif_regs ddr3_emif_reg_data = {
52 .sdram_config = MT41J128MJT125_EMIF_SDCFG,
53 .ref_ctrl = MT41J128MJT125_EMIF_SDREF,
54 .sdram_tim1 = MT41J128MJT125_EMIF_TIM1,
55 .sdram_tim2 = MT41J128MJT125_EMIF_TIM2,
56 .sdram_tim3 = MT41J128MJT125_EMIF_TIM3,
57 .zq_config = MT41J128MJT125_ZQ_CFG,
58 .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY |
59 PHY_EN_DYN_PWRDN,
60 };
61
62 const struct dpll_params dpll_ddr = {
63 /* M N M2 M3 M4 M5 M6 */
64 303, (V_OSCK/1000000) - 1, 1, -1, -1, -1, -1};
65
am33xx_spl_board_init(void)66 void am33xx_spl_board_init(void)
67 {
68 struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
69
70 /* Get the frequency */
71 dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
72
73 /* Set CORE Frequencies to OPP100 */
74 do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
75
76 /* Set MPU Frequency to what we detected now that voltages are set */
77 do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
78 }
79
get_dpll_ddr_params(void)80 const struct dpll_params *get_dpll_ddr_params(void)
81 {
82 return &dpll_ddr;
83 }
84
probe_sdram_size(long size)85 static void probe_sdram_size(long size)
86 {
87 switch (size) {
88 case SZ_512M:
89 ddr3_emif_reg_data.sdram_config = MT41J256MJT125_EMIF_SDCFG;
90 break;
91 case SZ_256M:
92 ddr3_emif_reg_data.sdram_config = MT41J128MJT125_EMIF_SDCFG;
93 break;
94 case SZ_128M:
95 ddr3_emif_reg_data.sdram_config = MT41J64MJT125_EMIF_SDCFG;
96 break;
97 default:
98 puts("Failed configuring DRAM, resetting...\n\n");
99 reset_cpu();
100 }
101 debug("%s: setting DRAM size to %ldM\n", __func__, size >> 20);
102 config_ddr(303, &ioregs, &ddr3_data,
103 &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
104 }
105
sdram_init(void)106 void sdram_init(void)
107 {
108 long size = SZ_1G;
109
110 do {
111 size = size / 2;
112 probe_sdram_size(size);
113 } while (get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, size) < size);
114
115 return;
116 }
117