1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2018-2020 NXP
4 */
5
6 #include <common.h>
7 #include <clock_legacy.h>
8 #include <dm.h>
9 #include <init.h>
10 #include <asm/global_data.h>
11 #include <dm/platform_data/serial_pl01x.h>
12 #include <i2c.h>
13 #include <malloc.h>
14 #include <errno.h>
15 #include <netdev.h>
16 #include <fsl_ddr.h>
17 #include <fsl_sec.h>
18 #include <asm/io.h>
19 #include <fdt_support.h>
20 #include <linux/bitops.h>
21 #include <linux/libfdt.h>
22 #include <linux/delay.h>
23 #include <fsl-mc/fsl_mc.h>
24 #include <env_internal.h>
25 #include <efi_loader.h>
26 #include <asm/arch/mmu.h>
27 #include <hwconfig.h>
28 #include <asm/arch/clock.h>
29 #include <asm/arch/config.h>
30 #include <asm/arch/fsl_serdes.h>
31 #include <asm/arch/soc.h>
32 #include "../common/qixis.h"
33 #include "../common/vid.h"
34 #include <fsl_immap.h>
35 #include <asm/arch-fsl-layerscape/fsl_icid.h>
36 #include "lx2160a.h"
37
38 #ifdef CONFIG_EMC2305
39 #include "../common/emc2305.h"
40 #endif
41
42 #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
43 #define CFG_MUX_I2C_SDHC(reg, value) ((reg & 0x3f) | value)
44 #define SET_CFG_MUX1_SDHC1_SDHC(reg) (reg & 0x3f)
45 #define SET_CFG_MUX2_SDHC1_SPI(reg, value) ((reg & 0xcf) | value)
46 #define SET_CFG_MUX3_SDHC1_SPI(reg, value) ((reg & 0xf8) | value)
47 #define SET_CFG_MUX_SDHC2_DSPI(reg, value) ((reg & 0xf8) | value)
48 #define SET_CFG_MUX1_SDHC1_DSPI(reg, value) ((reg & 0x3f) | value)
49 #define SDHC1_BASE_PMUX_DSPI 2
50 #define SDHC2_BASE_PMUX_DSPI 2
51 #define IIC5_PMUX_SPI3 3
52 #endif /* CONFIG_TARGET_LX2160AQDS or CONFIG_TARGET_LX2162AQDS */
53
54 DECLARE_GLOBAL_DATA_PTR;
55
56 static struct pl01x_serial_plat serial0 = {
57 #if CONFIG_CONS_INDEX == 0
58 .base = CONFIG_SYS_SERIAL0,
59 #elif CONFIG_CONS_INDEX == 1
60 .base = CONFIG_SYS_SERIAL1,
61 #else
62 #error "Unsupported console index value."
63 #endif
64 .type = TYPE_PL011,
65 };
66
67 U_BOOT_DRVINFO(nxp_serial0) = {
68 .name = "serial_pl01x",
69 .plat = &serial0,
70 };
71
72 static struct pl01x_serial_plat serial1 = {
73 .base = CONFIG_SYS_SERIAL1,
74 .type = TYPE_PL011,
75 };
76
77 U_BOOT_DRVINFO(nxp_serial1) = {
78 .name = "serial_pl01x",
79 .plat = &serial1,
80 };
81
select_i2c_ch_pca9547(u8 ch)82 int select_i2c_ch_pca9547(u8 ch)
83 {
84 int ret;
85
86 #if !CONFIG_IS_ENABLED(DM_I2C)
87 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
88 #else
89 struct udevice *dev;
90
91 ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
92 if (!ret)
93 ret = dm_i2c_write(dev, 0, &ch, 1);
94 #endif
95 if (ret) {
96 puts("PCA: failed to select proper channel\n");
97 return ret;
98 }
99
100 return 0;
101 }
102
uart_get_clock(void)103 static void uart_get_clock(void)
104 {
105 serial0.clock = get_serial_clock();
106 serial1.clock = get_serial_clock();
107 }
108
board_early_init_f(void)109 int board_early_init_f(void)
110 {
111 #ifdef CONFIG_SYS_I2C_EARLY_INIT
112 i2c_early_init_f();
113 #endif
114 /* get required clock for UART IP */
115 uart_get_clock();
116
117 #ifdef CONFIG_EMC2305
118 select_i2c_ch_pca9547(I2C_MUX_CH_EMC2305);
119 emc2305_init(I2C_EMC2305_ADDR);
120 set_fan_speed(I2C_EMC2305_PWM, I2C_EMC2305_ADDR);
121 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
122 #endif
123
124 fsl_lsch3_early_init_f();
125 return 0;
126 }
127
128 #ifdef CONFIG_OF_BOARD_FIXUP
board_fix_fdt(void * fdt)129 int board_fix_fdt(void *fdt)
130 {
131 char *reg_names, *reg_name;
132 int names_len, old_name_len, new_name_len, remaining_names_len;
133 struct str_map {
134 char *old_str;
135 char *new_str;
136 } reg_names_map[] = {
137 { "ccsr", "dbi" },
138 { "pf_ctrl", "ctrl" }
139 };
140 int off = -1, i = 0;
141
142 if (IS_SVR_REV(get_svr(), 1, 0))
143 return 0;
144
145 off = fdt_node_offset_by_compatible(fdt, -1, "fsl,lx2160a-pcie");
146 while (off != -FDT_ERR_NOTFOUND) {
147 fdt_setprop(fdt, off, "compatible", "fsl,ls-pcie",
148 strlen("fsl,ls-pcie") + 1);
149
150 reg_names = (char *)fdt_getprop(fdt, off, "reg-names",
151 &names_len);
152 if (!reg_names)
153 continue;
154
155 reg_name = reg_names;
156 remaining_names_len = names_len - (reg_name - reg_names);
157 i = 0;
158 while ((i < ARRAY_SIZE(reg_names_map)) && remaining_names_len) {
159 old_name_len = strlen(reg_names_map[i].old_str);
160 new_name_len = strlen(reg_names_map[i].new_str);
161 if (memcmp(reg_name, reg_names_map[i].old_str,
162 old_name_len) == 0) {
163 /* first only leave required bytes for new_str
164 * and copy rest of the string after it
165 */
166 memcpy(reg_name + new_name_len,
167 reg_name + old_name_len,
168 remaining_names_len - old_name_len);
169 /* Now copy new_str */
170 memcpy(reg_name, reg_names_map[i].new_str,
171 new_name_len);
172 names_len -= old_name_len;
173 names_len += new_name_len;
174 i++;
175 }
176
177 reg_name = memchr(reg_name, '\0', remaining_names_len);
178 if (!reg_name)
179 break;
180
181 reg_name += 1;
182
183 remaining_names_len = names_len -
184 (reg_name - reg_names);
185 }
186
187 fdt_setprop(fdt, off, "reg-names", reg_names, names_len);
188 off = fdt_node_offset_by_compatible(fdt, off,
189 "fsl,lx2160a-pcie");
190 }
191
192 return 0;
193 }
194 #endif
195
196 #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
esdhc_dspi_status_fixup(void * blob)197 void esdhc_dspi_status_fixup(void *blob)
198 {
199 const char esdhc0_path[] = "/soc/esdhc@2140000";
200 const char esdhc1_path[] = "/soc/esdhc@2150000";
201 const char dspi0_path[] = "/soc/spi@2100000";
202 const char dspi1_path[] = "/soc/spi@2110000";
203 const char dspi2_path[] = "/soc/spi@2120000";
204
205 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
206 u32 sdhc1_base_pmux;
207 u32 sdhc2_base_pmux;
208 u32 iic5_pmux;
209
210 /* Check RCW field sdhc1_base_pmux to enable/disable
211 * esdhc0/dspi0 DT node
212 */
213 sdhc1_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
214 & FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK;
215 sdhc1_base_pmux >>= FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT;
216
217 if (sdhc1_base_pmux == SDHC1_BASE_PMUX_DSPI) {
218 do_fixup_by_path(blob, dspi0_path, "status", "okay",
219 sizeof("okay"), 1);
220 do_fixup_by_path(blob, esdhc0_path, "status", "disabled",
221 sizeof("disabled"), 1);
222 } else {
223 do_fixup_by_path(blob, esdhc0_path, "status", "okay",
224 sizeof("okay"), 1);
225 do_fixup_by_path(blob, dspi0_path, "status", "disabled",
226 sizeof("disabled"), 1);
227 }
228
229 /* Check RCW field sdhc2_base_pmux to enable/disable
230 * esdhc1/dspi1 DT node
231 */
232 sdhc2_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR13_REGSR - 1])
233 & FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK;
234 sdhc2_base_pmux >>= FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT;
235
236 if (sdhc2_base_pmux == SDHC2_BASE_PMUX_DSPI) {
237 do_fixup_by_path(blob, dspi1_path, "status", "okay",
238 sizeof("okay"), 1);
239 do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
240 sizeof("disabled"), 1);
241 } else {
242 do_fixup_by_path(blob, esdhc1_path, "status", "okay",
243 sizeof("okay"), 1);
244 do_fixup_by_path(blob, dspi1_path, "status", "disabled",
245 sizeof("disabled"), 1);
246 }
247
248 /* Check RCW field IIC5 to enable dspi2 DT node */
249 iic5_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
250 & FSL_CHASSIS3_IIC5_PMUX_MASK;
251 iic5_pmux >>= FSL_CHASSIS3_IIC5_PMUX_SHIFT;
252
253 if (iic5_pmux == IIC5_PMUX_SPI3)
254 do_fixup_by_path(blob, dspi2_path, "status", "okay",
255 sizeof("okay"), 1);
256 else
257 do_fixup_by_path(blob, dspi2_path, "status", "disabled",
258 sizeof("disabled"), 1);
259 }
260 #endif
261
esdhc_status_fixup(void * blob,const char * compat)262 int esdhc_status_fixup(void *blob, const char *compat)
263 {
264 #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
265 /* Enable esdhc and dspi DT nodes based on RCW fields */
266 esdhc_dspi_status_fixup(blob);
267 #else
268 /* Enable both esdhc DT nodes for LX2160ARDB */
269 do_fixup_by_compat(blob, compat, "status", "okay",
270 sizeof("okay"), 1);
271 #endif
272 return 0;
273 }
274
275 #if defined(CONFIG_VID)
i2c_multiplexer_select_vid_channel(u8 channel)276 int i2c_multiplexer_select_vid_channel(u8 channel)
277 {
278 return select_i2c_ch_pca9547(channel);
279 }
280
init_func_vid(void)281 int init_func_vid(void)
282 {
283 int set_vid;
284
285 if (IS_SVR_REV(get_svr(), 1, 0))
286 set_vid = adjust_vdd(800);
287 else
288 set_vid = adjust_vdd(0);
289
290 if (set_vid < 0)
291 printf("core voltage not adjusted\n");
292
293 return 0;
294 }
295 #endif
296
checkboard(void)297 int checkboard(void)
298 {
299 enum boot_src src = get_boot_src();
300 char buf[64];
301 u8 sw;
302 #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
303 int clock;
304 static const char *const freq[] = {"100", "125", "156.25",
305 "161.13", "322.26", "", "", "",
306 "", "", "", "", "", "", "",
307 "100 separate SSCG"};
308 #endif
309
310 cpu_name(buf);
311 #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
312 printf("Board: %s-QDS, ", buf);
313 #else
314 printf("Board: %s-RDB, ", buf);
315 #endif
316
317 sw = QIXIS_READ(arch);
318 printf("Board version: %c, boot from ", (sw & 0xf) - 1 + 'A');
319
320 if (src == BOOT_SOURCE_SD_MMC) {
321 puts("SD\n");
322 } else if (src == BOOT_SOURCE_SD_MMC2) {
323 puts("eMMC\n");
324 } else {
325 sw = QIXIS_READ(brdcfg[0]);
326 sw = (sw >> QIXIS_XMAP_SHIFT) & QIXIS_XMAP_MASK;
327 switch (sw) {
328 case 0:
329 case 4:
330 puts("FlexSPI DEV#0\n");
331 break;
332 case 1:
333 puts("FlexSPI DEV#1\n");
334 break;
335 case 2:
336 case 3:
337 puts("FlexSPI EMU\n");
338 break;
339 default:
340 printf("invalid setting, xmap: %d\n", sw);
341 break;
342 }
343 }
344 #if defined(CONFIG_TARGET_LX2160ARDB)
345 printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
346
347 puts("SERDES1 Reference: Clock1 = 161.13MHz Clock2 = 161.13MHz\n");
348 puts("SERDES2 Reference: Clock1 = 100MHz Clock2 = 100MHz\n");
349 puts("SERDES3 Reference: Clock1 = 100MHz Clock2 = 100MHz\n");
350 #else
351 printf("FPGA: v%d (%s), build %d",
352 (int)QIXIS_READ(scver), qixis_read_tag(buf),
353 (int)qixis_read_minor());
354 /* the timestamp string contains "\n" at the end */
355 printf(" on %s", qixis_read_time(buf));
356
357 puts("SERDES1 Reference : ");
358 sw = QIXIS_READ(brdcfg[2]);
359 clock = sw >> 4;
360 printf("Clock1 = %sMHz ", freq[clock]);
361 #if defined(CONFIG_TARGET_LX2160AQDS)
362 clock = sw & 0x0f;
363 printf("Clock2 = %sMHz", freq[clock]);
364 #endif
365 sw = QIXIS_READ(brdcfg[3]);
366 puts("\nSERDES2 Reference : ");
367 clock = sw >> 4;
368 printf("Clock1 = %sMHz ", freq[clock]);
369 clock = sw & 0x0f;
370 printf("Clock2 = %sMHz\n", freq[clock]);
371 #if defined(CONFIG_TARGET_LX2160AQDS)
372 sw = QIXIS_READ(brdcfg[12]);
373 puts("SERDES3 Reference : ");
374 clock = sw >> 4;
375 printf("Clock1 = %sMHz Clock2 = %sMHz\n", freq[clock], freq[clock]);
376 #endif
377 #endif
378 return 0;
379 }
380
381 #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
382 /*
383 * implementation of CONFIG_ESDHC_DETECT_QUIRK Macro.
384 */
qixis_esdhc_detect_quirk(void)385 u8 qixis_esdhc_detect_quirk(void)
386 {
387 /*
388 * SDHC1 Card ID:
389 * Specifies the type of card installed in the SDHC1 adapter slot.
390 * 000= (reserved)
391 * 001= eMMC V4.5 adapter is installed.
392 * 010= SD/MMC 3.3V adapter is installed.
393 * 011= eMMC V4.4 adapter is installed.
394 * 100= eMMC V5.0 adapter is installed.
395 * 101= MMC card/Legacy (3.3V) adapter is installed.
396 * 110= SDCard V2/V3 adapter installed.
397 * 111= no adapter is installed.
398 */
399 return ((QIXIS_READ(sdhc1) & QIXIS_SDID_MASK) !=
400 QIXIS_ESDHC_NO_ADAPTER);
401 }
402
esdhc_adapter_card_ident(void)403 static void esdhc_adapter_card_ident(void)
404 {
405 u8 card_id, val;
406
407 val = QIXIS_READ(sdhc1);
408 card_id = val & QIXIS_SDID_MASK;
409
410 switch (card_id) {
411 case QIXIS_ESDHC_ADAPTER_TYPE_SD:
412 /* Power cycle to card */
413 val &= ~QIXIS_SDHC1_S1V3;
414 QIXIS_WRITE(sdhc1, val);
415 mdelay(1);
416 val |= QIXIS_SDHC1_S1V3;
417 QIXIS_WRITE(sdhc1, val);
418 /* Route to SDHC1_VS */
419 val = QIXIS_READ(brdcfg[11]);
420 val |= QIXIS_SDHC1_VS;
421 QIXIS_WRITE(brdcfg[11], val);
422 break;
423 default:
424 break;
425 }
426 }
427
config_board_mux(void)428 int config_board_mux(void)
429 {
430 u8 reg11, reg5, reg13;
431 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
432 u32 sdhc1_base_pmux;
433 u32 sdhc2_base_pmux;
434 u32 iic5_pmux;
435
436 /* Routes {I2C2_SCL, I2C2_SDA} to SDHC1 as {SDHC1_CD_B, SDHC1_WP}.
437 * Routes {I2C3_SCL, I2C3_SDA} to CAN transceiver as {CAN1_TX,CAN1_RX}.
438 * Routes {I2C4_SCL, I2C4_SDA} to CAN transceiver as {CAN2_TX,CAN2_RX}.
439 * Qixis and remote systems are isolated from the I2C1 bus.
440 * Processor connections are still available.
441 * SPI2 CS2_B controls EN25S64 SPI memory device.
442 * SPI3 CS2_B controls EN25S64 SPI memory device.
443 * EC2 connects to PHY #2 using RGMII protocol.
444 * CLK_OUT connects to FPGA for clock measurement.
445 */
446
447 reg5 = QIXIS_READ(brdcfg[5]);
448 reg5 = CFG_MUX_I2C_SDHC(reg5, 0x40);
449 QIXIS_WRITE(brdcfg[5], reg5);
450
451 /* Check RCW field sdhc1_base_pmux
452 * esdhc0 : sdhc1_base_pmux = 0
453 * dspi0 : sdhc1_base_pmux = 2
454 */
455 sdhc1_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
456 & FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK;
457 sdhc1_base_pmux >>= FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT;
458
459 if (sdhc1_base_pmux == SDHC1_BASE_PMUX_DSPI) {
460 reg11 = QIXIS_READ(brdcfg[11]);
461 reg11 = SET_CFG_MUX1_SDHC1_DSPI(reg11, 0x40);
462 QIXIS_WRITE(brdcfg[11], reg11);
463 } else {
464 /* - Routes {SDHC1_CMD, SDHC1_CLK } to SDHC1 adapter slot.
465 * {SDHC1_DAT3, SDHC1_DAT2} to SDHC1 adapter slot.
466 * {SDHC1_DAT1, SDHC1_DAT0} to SDHC1 adapter slot.
467 */
468 reg11 = QIXIS_READ(brdcfg[11]);
469 reg11 = SET_CFG_MUX1_SDHC1_SDHC(reg11);
470 QIXIS_WRITE(brdcfg[11], reg11);
471 }
472
473 /* Check RCW field sdhc2_base_pmux
474 * esdhc1 : sdhc2_base_pmux = 0 (default)
475 * dspi1 : sdhc2_base_pmux = 2
476 */
477 sdhc2_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR13_REGSR - 1])
478 & FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK;
479 sdhc2_base_pmux >>= FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT;
480
481 if (sdhc2_base_pmux == SDHC2_BASE_PMUX_DSPI) {
482 reg13 = QIXIS_READ(brdcfg[13]);
483 reg13 = SET_CFG_MUX_SDHC2_DSPI(reg13, 0x01);
484 QIXIS_WRITE(brdcfg[13], reg13);
485 } else {
486 reg13 = QIXIS_READ(brdcfg[13]);
487 reg13 = SET_CFG_MUX_SDHC2_DSPI(reg13, 0x00);
488 QIXIS_WRITE(brdcfg[13], reg13);
489 }
490
491 /* Check RCW field IIC5 to enable dspi2 DT nodei
492 * dspi2: IIC5 = 3
493 */
494 iic5_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
495 & FSL_CHASSIS3_IIC5_PMUX_MASK;
496 iic5_pmux >>= FSL_CHASSIS3_IIC5_PMUX_SHIFT;
497
498 if (iic5_pmux == IIC5_PMUX_SPI3) {
499 /* - Routes {SDHC1_DAT4} to SPI3 devices as {SPI3_M_CS0_B}. */
500 reg11 = QIXIS_READ(brdcfg[11]);
501 reg11 = SET_CFG_MUX2_SDHC1_SPI(reg11, 0x10);
502 QIXIS_WRITE(brdcfg[11], reg11);
503
504 /* - Routes {SDHC1_DAT5, SDHC1_DAT6} nowhere.
505 * {SDHC1_DAT7, SDHC1_DS } to {nothing, SPI3_M0_CLK }.
506 * {I2C5_SCL, I2C5_SDA } to {SPI3_M0_MOSI, SPI3_M0_MISO}.
507 */
508 reg11 = QIXIS_READ(brdcfg[11]);
509 reg11 = SET_CFG_MUX3_SDHC1_SPI(reg11, 0x01);
510 QIXIS_WRITE(brdcfg[11], reg11);
511 } else {
512 /*
513 * If {SDHC1_DAT4} has been configured to route to SDHC1_VS,
514 * do not change it.
515 * Otherwise route {SDHC1_DAT4} to SDHC1 adapter slot.
516 */
517 reg11 = QIXIS_READ(brdcfg[11]);
518 if ((reg11 & 0x30) != 0x30) {
519 reg11 = SET_CFG_MUX2_SDHC1_SPI(reg11, 0x00);
520 QIXIS_WRITE(brdcfg[11], reg11);
521 }
522
523 /* - Routes {SDHC1_DAT5, SDHC1_DAT6} to SDHC1 adapter slot.
524 * {SDHC1_DAT7, SDHC1_DS } to SDHC1 adapter slot.
525 * {I2C5_SCL, I2C5_SDA } to SDHC1 adapter slot.
526 */
527 reg11 = QIXIS_READ(brdcfg[11]);
528 reg11 = SET_CFG_MUX3_SDHC1_SPI(reg11, 0x00);
529 QIXIS_WRITE(brdcfg[11], reg11);
530 }
531
532 return 0;
533 }
534
board_early_init_r(void)535 int board_early_init_r(void)
536 {
537 esdhc_adapter_card_ident();
538 return 0;
539 }
540 #elif defined(CONFIG_TARGET_LX2160ARDB)
config_board_mux(void)541 int config_board_mux(void)
542 {
543 u8 brdcfg;
544
545 brdcfg = QIXIS_READ(brdcfg[4]);
546 /* The BRDCFG4 register controls general board configuration.
547 *|-------------------------------------------|
548 *|Field | Function |
549 *|-------------------------------------------|
550 *|5 | CAN I/O Enable (net CFG_CAN_EN_B):|
551 *|CAN_EN | 0= CAN transceivers are disabled. |
552 *| | 1= CAN transceivers are enabled. |
553 *|-------------------------------------------|
554 */
555 brdcfg |= BIT_MASK(5);
556 QIXIS_WRITE(brdcfg[4], brdcfg);
557
558 return 0;
559 }
560 #else
config_board_mux(void)561 int config_board_mux(void)
562 {
563 return 0;
564 }
565 #endif
566
get_board_sys_clk(void)567 unsigned long get_board_sys_clk(void)
568 {
569 #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
570 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
571
572 switch (sysclk_conf & 0x03) {
573 case QIXIS_SYSCLK_100:
574 return 100000000;
575 case QIXIS_SYSCLK_125:
576 return 125000000;
577 case QIXIS_SYSCLK_133:
578 return 133333333;
579 }
580 return 100000000;
581 #else
582 return 100000000;
583 #endif
584 }
585
get_board_ddr_clk(void)586 unsigned long get_board_ddr_clk(void)
587 {
588 #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
589 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
590
591 switch ((ddrclk_conf & 0x30) >> 4) {
592 case QIXIS_DDRCLK_100:
593 return 100000000;
594 case QIXIS_DDRCLK_125:
595 return 125000000;
596 case QIXIS_DDRCLK_133:
597 return 133333333;
598 }
599 return 100000000;
600 #else
601 return 100000000;
602 #endif
603 }
604
board_init(void)605 int board_init(void)
606 {
607 #if defined(CONFIG_FSL_MC_ENET) && defined(CONFIG_TARGET_LX2160ARDB)
608 u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
609 #endif
610 #ifdef CONFIG_ENV_IS_NOWHERE
611 gd->env_addr = (ulong)&default_environment[0];
612 #endif
613
614 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
615
616 #if defined(CONFIG_FSL_MC_ENET) && defined(CONFIG_TARGET_LX2160ARDB)
617 /* invert AQR107 IRQ pins polarity */
618 out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR107_IRQ_MASK);
619 #endif
620
621 #ifdef CONFIG_FSL_CAAM
622 sec_init();
623 #endif
624
625 #if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH)
626 pci_init();
627 #endif
628 return 0;
629 }
630
detail_board_ddr_info(void)631 void detail_board_ddr_info(void)
632 {
633 int i;
634 u64 ddr_size = 0;
635
636 puts("\nDDR ");
637 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
638 ddr_size += gd->bd->bi_dram[i].size;
639 print_size(ddr_size, "");
640 print_ddr_info(0);
641 }
642
643 #ifdef CONFIG_MISC_INIT_R
misc_init_r(void)644 int misc_init_r(void)
645 {
646 config_board_mux();
647
648 return 0;
649 }
650 #endif
651
652 #ifdef CONFIG_VID
soc_get_fuse_vid(int vid_index)653 u16 soc_get_fuse_vid(int vid_index)
654 {
655 static const u16 vdd[32] = {
656 8250,
657 7875,
658 7750,
659 0, /* reserved */
660 0, /* reserved */
661 0, /* reserved */
662 0, /* reserved */
663 0, /* reserved */
664 0, /* reserved */
665 0, /* reserved */
666 0, /* reserved */
667 0, /* reserved */
668 0, /* reserved */
669 0, /* reserved */
670 0, /* reserved */
671 0, /* reserved */
672 8000,
673 8125,
674 8250,
675 0, /* reserved */
676 8500,
677 0, /* reserved */
678 0, /* reserved */
679 0, /* reserved */
680 0, /* reserved */
681 0, /* reserved */
682 0, /* reserved */
683 0, /* reserved */
684 0, /* reserved */
685 0, /* reserved */
686 0, /* reserved */
687 0, /* reserved */
688 };
689
690 return vdd[vid_index];
691 };
692 #endif
693
694 #ifdef CONFIG_FSL_MC_ENET
695 extern int fdt_fixup_board_phy(void *fdt);
696
fdt_fixup_board_enet(void * fdt)697 void fdt_fixup_board_enet(void *fdt)
698 {
699 int offset;
700
701 offset = fdt_path_offset(fdt, "/soc/fsl-mc");
702
703 if (offset < 0)
704 offset = fdt_path_offset(fdt, "/fsl-mc");
705
706 if (offset < 0) {
707 printf("%s: fsl-mc node not found in device tree (error %d)\n",
708 __func__, offset);
709 return;
710 }
711
712 if (get_mc_boot_status() == 0 &&
713 (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0)) {
714 fdt_status_okay(fdt, offset);
715 #ifndef CONFIG_DM_ETH
716 fdt_fixup_board_phy(fdt);
717 #endif
718 } else {
719 fdt_status_fail(fdt, offset);
720 }
721 }
722
board_quiesce_devices(void)723 void board_quiesce_devices(void)
724 {
725 fsl_mc_ldpaa_exit(gd->bd);
726 }
727 #endif
728
729 #ifdef CONFIG_OF_BOARD_SETUP
ft_board_setup(void * blob,struct bd_info * bd)730 int ft_board_setup(void *blob, struct bd_info *bd)
731 {
732 int i;
733 u16 mc_memory_bank = 0;
734
735 u64 *base;
736 u64 *size;
737 u64 mc_memory_base = 0;
738 u64 mc_memory_size = 0;
739 u16 total_memory_banks;
740
741 ft_cpu_setup(blob, bd);
742
743 fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size);
744
745 if (mc_memory_base != 0)
746 mc_memory_bank++;
747
748 total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank;
749
750 base = calloc(total_memory_banks, sizeof(u64));
751 size = calloc(total_memory_banks, sizeof(u64));
752
753 /* fixup DT for the three GPP DDR banks */
754 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
755 base[i] = gd->bd->bi_dram[i].start;
756 size[i] = gd->bd->bi_dram[i].size;
757 }
758
759 #ifdef CONFIG_RESV_RAM
760 /* reduce size if reserved memory is within this bank */
761 if (gd->arch.resv_ram >= base[0] &&
762 gd->arch.resv_ram < base[0] + size[0])
763 size[0] = gd->arch.resv_ram - base[0];
764 else if (gd->arch.resv_ram >= base[1] &&
765 gd->arch.resv_ram < base[1] + size[1])
766 size[1] = gd->arch.resv_ram - base[1];
767 else if (gd->arch.resv_ram >= base[2] &&
768 gd->arch.resv_ram < base[2] + size[2])
769 size[2] = gd->arch.resv_ram - base[2];
770 #endif
771
772 if (mc_memory_base != 0) {
773 for (i = 0; i <= total_memory_banks; i++) {
774 if (base[i] == 0 && size[i] == 0) {
775 base[i] = mc_memory_base;
776 size[i] = mc_memory_size;
777 break;
778 }
779 }
780 }
781
782 fdt_fixup_memory_banks(blob, base, size, total_memory_banks);
783
784 #ifdef CONFIG_USB
785 fsl_fdt_fixup_dr_usb(blob, bd);
786 #endif
787
788 #ifdef CONFIG_FSL_MC_ENET
789 fdt_fsl_mc_fixup_iommu_map_entry(blob);
790 fdt_fixup_board_enet(blob);
791 #endif
792 fdt_fixup_icid(blob);
793
794 return 0;
795 }
796 #endif
797
qixis_dump_switch(void)798 void qixis_dump_switch(void)
799 {
800 int i, nr_of_cfgsw;
801
802 QIXIS_WRITE(cms[0], 0x00);
803 nr_of_cfgsw = QIXIS_READ(cms[1]);
804
805 puts("DIP switch settings dump:\n");
806 for (i = 1; i <= nr_of_cfgsw; i++) {
807 QIXIS_WRITE(cms[0], i);
808 printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
809 }
810 }
811