1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2011,2012 Freescale Semiconductor, Inc.
4 */
5
6 #include <common.h>
7 #include <command.h>
8 #include <env.h>
9 #include <fdt_support.h>
10 #include <image.h>
11 #include <init.h>
12 #include <netdev.h>
13 #include <asm/global_data.h>
14 #include <linux/compiler.h>
15 #include <asm/mmu.h>
16 #include <asm/processor.h>
17 #include <asm/cache.h>
18 #include <asm/immap_85xx.h>
19 #include <asm/fsl_law.h>
20 #include <asm/fsl_serdes.h>
21 #include <asm/fsl_liodn.h>
22 #include <fm_eth.h>
23
24 extern void pci_of_setup(void *blob, struct bd_info *bd);
25
26 #include "cpld.h"
27
28 DECLARE_GLOBAL_DATA_PTR;
29
checkboard(void)30 int checkboard(void)
31 {
32 u8 sw;
33 struct cpu_type *cpu = gd->arch.cpu;
34 unsigned int i;
35
36 printf("Board: %sRDB, ", cpu->name);
37 printf("CPLD version: %d.%d ", CPLD_READ(cpld_ver),
38 CPLD_READ(cpld_ver_sub));
39
40 sw = CPLD_READ(fbank_sel);
41 printf("vBank: %d\n", sw & 0x1);
42
43 /*
44 * Display the actual SERDES reference clocks as configured by the
45 * dip switches on the board. Note that the SWx registers could
46 * technically be set to force the reference clocks to match the
47 * values that the SERDES expects (or vice versa). For now, however,
48 * we just display both values and hope the user notices when they
49 * don't match.
50 */
51 puts("SERDES Reference Clocks: ");
52 sw = in_8(&CPLD_SW(2)) >> 2;
53 for (i = 0; i < 2; i++) {
54 static const char * const freq[][3] = {{"0", "100", "125"},
55 {"100", "156.25", "125"}
56 };
57 unsigned int clock = (sw >> (2 * i)) & 3;
58
59 printf("Bank%u=%sMhz ", i+1, freq[i][clock]);
60 }
61 puts("\n");
62
63 return 0;
64 }
65
board_early_init_f(void)66 int board_early_init_f(void)
67 {
68 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
69
70 /* board only uses the DDR_MCK0/1, so disable the DDR_MCK2/3 */
71 setbits_be32(&gur->ddrclkdr, 0x000f000f);
72
73 return 0;
74 }
75
76 #define CPLD_LANE_A_SEL 0x1
77 #define CPLD_LANE_G_SEL 0x2
78 #define CPLD_LANE_C_SEL 0x4
79 #define CPLD_LANE_D_SEL 0x8
80
board_config_lanes_mux(void)81 void board_config_lanes_mux(void)
82 {
83 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
84 int srds_prtcl = (in_be32(&gur->rcwsr[4]) &
85 FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
86
87 u8 mux = 0;
88 switch (srds_prtcl) {
89 case 0x2:
90 case 0x5:
91 case 0x9:
92 case 0xa:
93 case 0xf:
94 break;
95 case 0x8:
96 mux |= CPLD_LANE_C_SEL | CPLD_LANE_D_SEL;
97 break;
98 case 0x14:
99 mux |= CPLD_LANE_A_SEL;
100 break;
101 case 0x17:
102 mux |= CPLD_LANE_G_SEL;
103 break;
104 case 0x16:
105 case 0x19:
106 case 0x1a:
107 mux |= CPLD_LANE_G_SEL | CPLD_LANE_C_SEL | CPLD_LANE_D_SEL;
108 break;
109 case 0x1c:
110 mux |= CPLD_LANE_G_SEL | CPLD_LANE_A_SEL;
111 break;
112 default:
113 printf("Fman:Unsupported SerDes Protocol 0x%02x\n", srds_prtcl);
114 break;
115 }
116 CPLD_WRITE(serdes_mux, mux);
117 }
118
board_early_init_r(void)119 int board_early_init_r(void)
120 {
121 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
122 int flash_esel = find_tlb_idx((void *)flashbase, 1);
123
124 /*
125 * Remap Boot flash + PROMJET region to caching-inhibited
126 * so that flash can be erased properly.
127 */
128
129 /* Flush d-cache and invalidate i-cache of any FLASH data */
130 flush_dcache();
131 invalidate_icache();
132
133 if (flash_esel == -1) {
134 /* very unlikely unless something is messed up */
135 puts("Error: Could not find TLB for FLASH BASE\n");
136 flash_esel = 2; /* give our best effort to continue */
137 } else {
138 /* invalidate existing TLB entry for flash + promjet */
139 disable_tlb(flash_esel);
140 }
141
142 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
143 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
144 0, flash_esel, BOOKE_PAGESZ_256M, 1);
145
146 board_config_lanes_mux();
147
148 return 0;
149 }
150
get_board_sys_clk(unsigned long dummy)151 unsigned long get_board_sys_clk(unsigned long dummy)
152 {
153 u8 sysclk_conf = CPLD_READ(sysclk_sw1);
154
155 switch (sysclk_conf & 0x7) {
156 case CPLD_SYSCLK_83:
157 return 83333333;
158 case CPLD_SYSCLK_100:
159 return 100000000;
160 default:
161 return 66666666;
162 }
163 }
164
165 #define NUM_SRDS_BANKS 2
166
misc_init_r(void)167 int misc_init_r(void)
168 {
169 serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
170 u32 actual[NUM_SRDS_BANKS];
171 unsigned int i;
172 u8 sw;
173 static const int freq[][3] = {
174 {0, SRDS_PLLCR0_RFCK_SEL_100, SRDS_PLLCR0_RFCK_SEL_125},
175 {SRDS_PLLCR0_RFCK_SEL_100, SRDS_PLLCR0_RFCK_SEL_156_25,
176 SRDS_PLLCR0_RFCK_SEL_125}
177 };
178
179 sw = in_8(&CPLD_SW(2)) >> 2;
180 for (i = 0; i < NUM_SRDS_BANKS; i++) {
181 unsigned int clock = (sw >> (2 * i)) & 3;
182 if (clock == 0x3) {
183 printf("Warning: SDREFCLK%u switch setting of '11' is "
184 "unsupported\n", i + 1);
185 break;
186 }
187 if (i == 0 && clock == 0)
188 puts("Warning: SDREFCLK1 switch setting of"
189 "'00' is unsupported\n");
190 else
191 actual[i] = freq[i][clock];
192
193 /*
194 * PC board uses a different CPLD with PB board, this CPLD
195 * has cpld_ver_sub = 1, and pcba_ver = 5. But CPLD on PB
196 * board has cpld_ver_sub = 0, and pcba_ver = 4.
197 */
198 if ((i == 1) && (CPLD_READ(cpld_ver_sub) == 1) &&
199 (CPLD_READ(pcba_ver) == 5)) {
200 /* PC board bank2 frequency */
201 actual[i] = freq[i-1][clock];
202 }
203 }
204
205 for (i = 0; i < NUM_SRDS_BANKS; i++) {
206 u32 expected = in_be32(®s->bank[i].pllcr0);
207 expected &= SRDS_PLLCR0_RFCK_SEL_MASK;
208 if (expected != actual[i]) {
209 printf("Warning: SERDES bank %u expects reference clock"
210 " %sMHz, but actual is %sMHz\n", i + 1,
211 serdes_clock_to_string(expected),
212 serdes_clock_to_string(actual[i]));
213 }
214 }
215
216 return 0;
217 }
218
ft_board_setup(void * blob,struct bd_info * bd)219 int ft_board_setup(void *blob, struct bd_info *bd)
220 {
221 phys_addr_t base;
222 phys_size_t size;
223
224 ft_cpu_setup(blob, bd);
225
226 base = env_get_bootm_low();
227 size = env_get_bootm_size();
228
229 fdt_fixup_memory(blob, (u64)base, (u64)size);
230
231 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
232 fsl_fdt_fixup_dr_usb(blob, bd);
233 #endif
234
235 #ifdef CONFIG_PCI
236 pci_of_setup(blob, bd);
237 #endif
238
239 fdt_fixup_liodn(blob);
240 #ifdef CONFIG_SYS_DPAA_FMAN
241 #ifndef CONFIG_DM_ETH
242 fdt_fixup_fman_ethernet(blob);
243 #endif
244 #endif
245
246 return 0;
247 }
248