1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2017 STMicroelectronics
4 */
5
6 #define LOG_CATEGORY UCLASS_I2C
7
8 #include <common.h>
9 #include <clk.h>
10 #include <dm.h>
11 #include <i2c.h>
12 #include <log.h>
13 #include <regmap.h>
14 #include <reset.h>
15 #include <syscon.h>
16 #include <dm/device.h>
17 #include <dm/device_compat.h>
18 #include <linux/bitops.h>
19 #include <linux/delay.h>
20 #include <linux/err.h>
21 #include <linux/io.h>
22
23 /* STM32 I2C registers */
24 struct stm32_i2c_regs {
25 u32 cr1; /* I2C control register 1 */
26 u32 cr2; /* I2C control register 2 */
27 u32 oar1; /* I2C own address 1 register */
28 u32 oar2; /* I2C own address 2 register */
29 u32 timingr; /* I2C timing register */
30 u32 timeoutr; /* I2C timeout register */
31 u32 isr; /* I2C interrupt and status register */
32 u32 icr; /* I2C interrupt clear register */
33 u32 pecr; /* I2C packet error checking register */
34 u32 rxdr; /* I2C receive data register */
35 u32 txdr; /* I2C transmit data register */
36 };
37
38 #define STM32_I2C_CR1 0x00
39 #define STM32_I2C_CR2 0x04
40 #define STM32_I2C_TIMINGR 0x10
41 #define STM32_I2C_ISR 0x18
42 #define STM32_I2C_ICR 0x1C
43 #define STM32_I2C_RXDR 0x24
44 #define STM32_I2C_TXDR 0x28
45
46 /* STM32 I2C control 1 */
47 #define STM32_I2C_CR1_ANFOFF BIT(12)
48 #define STM32_I2C_CR1_ERRIE BIT(7)
49 #define STM32_I2C_CR1_TCIE BIT(6)
50 #define STM32_I2C_CR1_STOPIE BIT(5)
51 #define STM32_I2C_CR1_NACKIE BIT(4)
52 #define STM32_I2C_CR1_ADDRIE BIT(3)
53 #define STM32_I2C_CR1_RXIE BIT(2)
54 #define STM32_I2C_CR1_TXIE BIT(1)
55 #define STM32_I2C_CR1_PE BIT(0)
56
57 /* STM32 I2C control 2 */
58 #define STM32_I2C_CR2_AUTOEND BIT(25)
59 #define STM32_I2C_CR2_RELOAD BIT(24)
60 #define STM32_I2C_CR2_NBYTES_MASK GENMASK(23, 16)
61 #define STM32_I2C_CR2_NBYTES(n) ((n & 0xff) << 16)
62 #define STM32_I2C_CR2_NACK BIT(15)
63 #define STM32_I2C_CR2_STOP BIT(14)
64 #define STM32_I2C_CR2_START BIT(13)
65 #define STM32_I2C_CR2_HEAD10R BIT(12)
66 #define STM32_I2C_CR2_ADD10 BIT(11)
67 #define STM32_I2C_CR2_RD_WRN BIT(10)
68 #define STM32_I2C_CR2_SADD10_MASK GENMASK(9, 0)
69 #define STM32_I2C_CR2_SADD10(n) (n & STM32_I2C_CR2_SADD10_MASK)
70 #define STM32_I2C_CR2_SADD7_MASK GENMASK(7, 1)
71 #define STM32_I2C_CR2_SADD7(n) ((n & 0x7f) << 1)
72 #define STM32_I2C_CR2_RESET_MASK (STM32_I2C_CR2_HEAD10R \
73 | STM32_I2C_CR2_NBYTES_MASK \
74 | STM32_I2C_CR2_SADD7_MASK \
75 | STM32_I2C_CR2_RELOAD \
76 | STM32_I2C_CR2_RD_WRN)
77
78 /* STM32 I2C Interrupt Status */
79 #define STM32_I2C_ISR_BUSY BIT(15)
80 #define STM32_I2C_ISR_ARLO BIT(9)
81 #define STM32_I2C_ISR_BERR BIT(8)
82 #define STM32_I2C_ISR_TCR BIT(7)
83 #define STM32_I2C_ISR_TC BIT(6)
84 #define STM32_I2C_ISR_STOPF BIT(5)
85 #define STM32_I2C_ISR_NACKF BIT(4)
86 #define STM32_I2C_ISR_ADDR BIT(3)
87 #define STM32_I2C_ISR_RXNE BIT(2)
88 #define STM32_I2C_ISR_TXIS BIT(1)
89 #define STM32_I2C_ISR_TXE BIT(0)
90 #define STM32_I2C_ISR_ERRORS (STM32_I2C_ISR_BERR \
91 | STM32_I2C_ISR_ARLO)
92
93 /* STM32 I2C Interrupt Clear */
94 #define STM32_I2C_ICR_ARLOCF BIT(9)
95 #define STM32_I2C_ICR_BERRCF BIT(8)
96 #define STM32_I2C_ICR_STOPCF BIT(5)
97 #define STM32_I2C_ICR_NACKCF BIT(4)
98
99 /* STM32 I2C Timing */
100 #define STM32_I2C_TIMINGR_PRESC(n) ((n & 0xf) << 28)
101 #define STM32_I2C_TIMINGR_SCLDEL(n) ((n & 0xf) << 20)
102 #define STM32_I2C_TIMINGR_SDADEL(n) ((n & 0xf) << 16)
103 #define STM32_I2C_TIMINGR_SCLH(n) ((n & 0xff) << 8)
104 #define STM32_I2C_TIMINGR_SCLL(n) (n & 0xff)
105
106 #define STM32_I2C_MAX_LEN 0xff
107
108 #define STM32_I2C_DNF_DEFAULT 0
109 #define STM32_I2C_DNF_MAX 16
110
111 #define STM32_I2C_ANALOG_FILTER_ENABLE 1
112 #define STM32_I2C_ANALOG_FILTER_DELAY_MIN 50 /* ns */
113 #define STM32_I2C_ANALOG_FILTER_DELAY_MAX 260 /* ns */
114
115 #define STM32_I2C_RISE_TIME_DEFAULT 25 /* ns */
116 #define STM32_I2C_FALL_TIME_DEFAULT 10 /* ns */
117
118 #define STM32_PRESC_MAX BIT(4)
119 #define STM32_SCLDEL_MAX BIT(4)
120 #define STM32_SDADEL_MAX BIT(4)
121 #define STM32_SCLH_MAX BIT(8)
122 #define STM32_SCLL_MAX BIT(8)
123
124 #define STM32_NSEC_PER_SEC 1000000000L
125
126 /**
127 * struct stm32_i2c_spec - private i2c specification timing
128 * @rate: I2C bus speed (Hz)
129 * @rate_min: 80% of I2C bus speed (Hz)
130 * @rate_max: 120% of I2C bus speed (Hz)
131 * @fall_max: Max fall time of both SDA and SCL signals (ns)
132 * @rise_max: Max rise time of both SDA and SCL signals (ns)
133 * @hddat_min: Min data hold time (ns)
134 * @vddat_max: Max data valid time (ns)
135 * @sudat_min: Min data setup time (ns)
136 * @l_min: Min low period of the SCL clock (ns)
137 * @h_min: Min high period of the SCL clock (ns)
138 */
139
140 struct stm32_i2c_spec {
141 u32 rate;
142 u32 rate_min;
143 u32 rate_max;
144 u32 fall_max;
145 u32 rise_max;
146 u32 hddat_min;
147 u32 vddat_max;
148 u32 sudat_min;
149 u32 l_min;
150 u32 h_min;
151 };
152
153 /**
154 * struct stm32_i2c_setup - private I2C timing setup parameters
155 * @speed_freq: I2C speed frequency (Hz)
156 * @clock_src: I2C clock source frequency (Hz)
157 * @rise_time: Rise time (ns)
158 * @fall_time: Fall time (ns)
159 * @dnf: Digital filter coefficient (0-16)
160 * @analog_filter: Analog filter delay (On/Off)
161 * @fmp_clr_offset: Fast Mode Plus clear register offset from set register
162 */
163 struct stm32_i2c_setup {
164 u32 speed_freq;
165 u32 clock_src;
166 u32 rise_time;
167 u32 fall_time;
168 u8 dnf;
169 bool analog_filter;
170 u32 fmp_clr_offset;
171 };
172
173 /**
174 * struct stm32_i2c_timings - private I2C output parameters
175 * @prec: Prescaler value
176 * @scldel: Data setup time
177 * @sdadel: Data hold time
178 * @sclh: SCL high period (master mode)
179 * @sclh: SCL low period (master mode)
180 */
181 struct stm32_i2c_timings {
182 struct list_head node;
183 u8 presc;
184 u8 scldel;
185 u8 sdadel;
186 u8 sclh;
187 u8 scll;
188 };
189
190 /**
191 * struct stm32_i2c_priv - private data of the controller
192 * @regs: I2C registers address
193 * @clk: hw i2c clock
194 * @setup: I2C timing setup parameters
195 * @speed: I2C clock frequency of the controller. Standard, Fast or Fast+
196 * @regmap: holds SYSCFG phandle for Fast Mode Plus bit
197 * @regmap_sreg: register address for setting Fast Mode Plus bits
198 * @regmap_creg: register address for clearing Fast Mode Plus bits
199 * @regmap_mask: mask for Fast Mode Plus bits
200 */
201 struct stm32_i2c_priv {
202 struct stm32_i2c_regs *regs;
203 struct clk clk;
204 struct stm32_i2c_setup *setup;
205 u32 speed;
206 struct regmap *regmap;
207 u32 regmap_sreg;
208 u32 regmap_creg;
209 u32 regmap_mask;
210 };
211
212 static const struct stm32_i2c_spec i2c_specs[] = {
213 /* Standard speed - 100 KHz */
214 [IC_SPEED_MODE_STANDARD] = {
215 .rate = I2C_SPEED_STANDARD_RATE,
216 .rate_min = 8000,
217 .rate_max = 120000,
218 .fall_max = 300,
219 .rise_max = 1000,
220 .hddat_min = 0,
221 .vddat_max = 3450,
222 .sudat_min = 250,
223 .l_min = 4700,
224 .h_min = 4000,
225 },
226 /* Fast speed - 400 KHz */
227 [IC_SPEED_MODE_FAST] = {
228 .rate = I2C_SPEED_FAST_RATE,
229 .rate_min = 320000,
230 .rate_max = 480000,
231 .fall_max = 300,
232 .rise_max = 300,
233 .hddat_min = 0,
234 .vddat_max = 900,
235 .sudat_min = 100,
236 .l_min = 1300,
237 .h_min = 600,
238 },
239 /* Fast Plus Speed - 1 MHz */
240 [IC_SPEED_MODE_FAST_PLUS] = {
241 .rate = I2C_SPEED_FAST_PLUS_RATE,
242 .rate_min = 800000,
243 .rate_max = 1200000,
244 .fall_max = 100,
245 .rise_max = 120,
246 .hddat_min = 0,
247 .vddat_max = 450,
248 .sudat_min = 50,
249 .l_min = 500,
250 .h_min = 260,
251 },
252 };
253
254 static const struct stm32_i2c_setup stm32f7_setup = {
255 .rise_time = STM32_I2C_RISE_TIME_DEFAULT,
256 .fall_time = STM32_I2C_FALL_TIME_DEFAULT,
257 .dnf = STM32_I2C_DNF_DEFAULT,
258 .analog_filter = STM32_I2C_ANALOG_FILTER_ENABLE,
259 };
260
261 static const struct stm32_i2c_setup stm32mp15_setup = {
262 .rise_time = STM32_I2C_RISE_TIME_DEFAULT,
263 .fall_time = STM32_I2C_FALL_TIME_DEFAULT,
264 .dnf = STM32_I2C_DNF_DEFAULT,
265 .analog_filter = STM32_I2C_ANALOG_FILTER_ENABLE,
266 .fmp_clr_offset = 0x40,
267 };
268
stm32_i2c_check_device_busy(struct stm32_i2c_priv * i2c_priv)269 static int stm32_i2c_check_device_busy(struct stm32_i2c_priv *i2c_priv)
270 {
271 struct stm32_i2c_regs *regs = i2c_priv->regs;
272 u32 status = readl(®s->isr);
273
274 if (status & STM32_I2C_ISR_BUSY)
275 return -EBUSY;
276
277 return 0;
278 }
279
stm32_i2c_message_start(struct stm32_i2c_priv * i2c_priv,struct i2c_msg * msg,bool stop)280 static void stm32_i2c_message_start(struct stm32_i2c_priv *i2c_priv,
281 struct i2c_msg *msg, bool stop)
282 {
283 struct stm32_i2c_regs *regs = i2c_priv->regs;
284 u32 cr2 = readl(®s->cr2);
285
286 /* Set transfer direction */
287 cr2 &= ~STM32_I2C_CR2_RD_WRN;
288 if (msg->flags & I2C_M_RD)
289 cr2 |= STM32_I2C_CR2_RD_WRN;
290
291 /* Set slave address */
292 cr2 &= ~(STM32_I2C_CR2_HEAD10R | STM32_I2C_CR2_ADD10);
293 if (msg->flags & I2C_M_TEN) {
294 cr2 &= ~STM32_I2C_CR2_SADD10_MASK;
295 cr2 |= STM32_I2C_CR2_SADD10(msg->addr);
296 cr2 |= STM32_I2C_CR2_ADD10;
297 } else {
298 cr2 &= ~STM32_I2C_CR2_SADD7_MASK;
299 cr2 |= STM32_I2C_CR2_SADD7(msg->addr);
300 }
301
302 /* Set nb bytes to transfer and reload or autoend bits */
303 cr2 &= ~(STM32_I2C_CR2_NBYTES_MASK | STM32_I2C_CR2_RELOAD |
304 STM32_I2C_CR2_AUTOEND);
305 if (msg->len > STM32_I2C_MAX_LEN) {
306 cr2 |= STM32_I2C_CR2_NBYTES(STM32_I2C_MAX_LEN);
307 cr2 |= STM32_I2C_CR2_RELOAD;
308 } else {
309 cr2 |= STM32_I2C_CR2_NBYTES(msg->len);
310 }
311
312 /* Write configurations register */
313 writel(cr2, ®s->cr2);
314
315 /* START/ReSTART generation */
316 setbits_le32(®s->cr2, STM32_I2C_CR2_START);
317 }
318
319 /*
320 * RELOAD mode must be selected if total number of data bytes to be
321 * sent is greater than MAX_LEN
322 */
323
stm32_i2c_handle_reload(struct stm32_i2c_priv * i2c_priv,struct i2c_msg * msg,bool stop)324 static void stm32_i2c_handle_reload(struct stm32_i2c_priv *i2c_priv,
325 struct i2c_msg *msg, bool stop)
326 {
327 struct stm32_i2c_regs *regs = i2c_priv->regs;
328 u32 cr2 = readl(®s->cr2);
329
330 cr2 &= ~STM32_I2C_CR2_NBYTES_MASK;
331
332 if (msg->len > STM32_I2C_MAX_LEN) {
333 cr2 |= STM32_I2C_CR2_NBYTES(STM32_I2C_MAX_LEN);
334 } else {
335 cr2 &= ~STM32_I2C_CR2_RELOAD;
336 cr2 |= STM32_I2C_CR2_NBYTES(msg->len);
337 }
338
339 writel(cr2, ®s->cr2);
340 }
341
stm32_i2c_wait_flags(struct stm32_i2c_priv * i2c_priv,u32 flags,u32 * status)342 static int stm32_i2c_wait_flags(struct stm32_i2c_priv *i2c_priv,
343 u32 flags, u32 *status)
344 {
345 struct stm32_i2c_regs *regs = i2c_priv->regs;
346 u32 time_start = get_timer(0);
347
348 *status = readl(®s->isr);
349 while (!(*status & flags)) {
350 if (get_timer(time_start) > CONFIG_SYS_HZ) {
351 log_debug("i2c timeout\n");
352 return -ETIMEDOUT;
353 }
354
355 *status = readl(®s->isr);
356 }
357
358 return 0;
359 }
360
stm32_i2c_check_end_of_message(struct stm32_i2c_priv * i2c_priv)361 static int stm32_i2c_check_end_of_message(struct stm32_i2c_priv *i2c_priv)
362 {
363 struct stm32_i2c_regs *regs = i2c_priv->regs;
364 u32 mask = STM32_I2C_ISR_ERRORS | STM32_I2C_ISR_NACKF |
365 STM32_I2C_ISR_STOPF;
366 u32 status;
367 int ret;
368
369 ret = stm32_i2c_wait_flags(i2c_priv, mask, &status);
370 if (ret)
371 return ret;
372
373 if (status & STM32_I2C_ISR_BERR) {
374 log_debug("Bus error\n");
375
376 /* Clear BERR flag */
377 setbits_le32(®s->icr, STM32_I2C_ICR_BERRCF);
378
379 return -EIO;
380 }
381
382 if (status & STM32_I2C_ISR_ARLO) {
383 log_debug("Arbitration lost\n");
384
385 /* Clear ARLO flag */
386 setbits_le32(®s->icr, STM32_I2C_ICR_ARLOCF);
387
388 return -EAGAIN;
389 }
390
391 if (status & STM32_I2C_ISR_NACKF) {
392 log_debug("Receive NACK\n");
393
394 /* Clear NACK flag */
395 setbits_le32(®s->icr, STM32_I2C_ICR_NACKCF);
396
397 /* Wait until STOPF flag is set */
398 mask = STM32_I2C_ISR_STOPF;
399 ret = stm32_i2c_wait_flags(i2c_priv, mask, &status);
400 if (ret)
401 return ret;
402
403 ret = -EIO;
404 }
405
406 if (status & STM32_I2C_ISR_STOPF) {
407 /* Clear STOP flag */
408 setbits_le32(®s->icr, STM32_I2C_ICR_STOPCF);
409
410 /* Clear control register 2 */
411 setbits_le32(®s->cr2, STM32_I2C_CR2_RESET_MASK);
412 }
413
414 return ret;
415 }
416
stm32_i2c_message_xfer(struct stm32_i2c_priv * i2c_priv,struct i2c_msg * msg,bool stop)417 static int stm32_i2c_message_xfer(struct stm32_i2c_priv *i2c_priv,
418 struct i2c_msg *msg, bool stop)
419 {
420 struct stm32_i2c_regs *regs = i2c_priv->regs;
421 u32 status;
422 u32 mask = msg->flags & I2C_M_RD ? STM32_I2C_ISR_RXNE :
423 STM32_I2C_ISR_TXIS | STM32_I2C_ISR_NACKF;
424 int bytes_to_rw = msg->len > STM32_I2C_MAX_LEN ?
425 STM32_I2C_MAX_LEN : msg->len;
426 int ret = 0;
427
428 /* Add errors */
429 mask |= STM32_I2C_ISR_ERRORS;
430
431 stm32_i2c_message_start(i2c_priv, msg, stop);
432
433 while (msg->len) {
434 /*
435 * Wait until TXIS/NACKF/BERR/ARLO flags or
436 * RXNE/BERR/ARLO flags are set
437 */
438 ret = stm32_i2c_wait_flags(i2c_priv, mask, &status);
439 if (ret)
440 break;
441
442 if (status & (STM32_I2C_ISR_NACKF | STM32_I2C_ISR_ERRORS))
443 break;
444
445 if (status & STM32_I2C_ISR_RXNE) {
446 *msg->buf++ = readb(®s->rxdr);
447 msg->len--;
448 bytes_to_rw--;
449 }
450
451 if (status & STM32_I2C_ISR_TXIS) {
452 writeb(*msg->buf++, ®s->txdr);
453 msg->len--;
454 bytes_to_rw--;
455 }
456
457 if (!bytes_to_rw && msg->len) {
458 /* Wait until TCR flag is set */
459 mask = STM32_I2C_ISR_TCR;
460 ret = stm32_i2c_wait_flags(i2c_priv, mask, &status);
461 if (ret)
462 break;
463
464 bytes_to_rw = msg->len > STM32_I2C_MAX_LEN ?
465 STM32_I2C_MAX_LEN : msg->len;
466 mask = msg->flags & I2C_M_RD ? STM32_I2C_ISR_RXNE :
467 STM32_I2C_ISR_TXIS | STM32_I2C_ISR_NACKF;
468
469 stm32_i2c_handle_reload(i2c_priv, msg, stop);
470 } else if (!bytes_to_rw) {
471 /* Wait until TC flag is set */
472 mask = STM32_I2C_ISR_TC;
473 ret = stm32_i2c_wait_flags(i2c_priv, mask, &status);
474 if (ret)
475 break;
476
477 if (!stop)
478 /* Message sent, new message has to be sent */
479 return 0;
480 }
481 }
482
483 /* End of transfer, send stop condition */
484 mask = STM32_I2C_CR2_STOP;
485 setbits_le32(®s->cr2, mask);
486
487 return stm32_i2c_check_end_of_message(i2c_priv);
488 }
489
stm32_i2c_xfer(struct udevice * bus,struct i2c_msg * msg,int nmsgs)490 static int stm32_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
491 int nmsgs)
492 {
493 struct stm32_i2c_priv *i2c_priv = dev_get_priv(bus);
494 int ret;
495
496 ret = stm32_i2c_check_device_busy(i2c_priv);
497 if (ret)
498 return ret;
499
500 for (; nmsgs > 0; nmsgs--, msg++) {
501 ret = stm32_i2c_message_xfer(i2c_priv, msg, nmsgs == 1);
502 if (ret)
503 return ret;
504 }
505
506 return 0;
507 }
508
stm32_i2c_compute_solutions(struct stm32_i2c_setup * setup,const struct stm32_i2c_spec * specs,struct list_head * solutions)509 static int stm32_i2c_compute_solutions(struct stm32_i2c_setup *setup,
510 const struct stm32_i2c_spec *specs,
511 struct list_head *solutions)
512 {
513 struct stm32_i2c_timings *v;
514 u32 p_prev = STM32_PRESC_MAX;
515 u32 i2cclk = DIV_ROUND_CLOSEST(STM32_NSEC_PER_SEC,
516 setup->clock_src);
517 u32 af_delay_min, af_delay_max;
518 u16 p, l, a;
519 int sdadel_min, sdadel_max, scldel_min;
520 int ret = 0;
521
522 af_delay_min = setup->analog_filter ?
523 STM32_I2C_ANALOG_FILTER_DELAY_MIN : 0;
524 af_delay_max = setup->analog_filter ?
525 STM32_I2C_ANALOG_FILTER_DELAY_MAX : 0;
526
527 sdadel_min = specs->hddat_min + setup->fall_time -
528 af_delay_min - (setup->dnf + 3) * i2cclk;
529
530 sdadel_max = specs->vddat_max - setup->rise_time -
531 af_delay_max - (setup->dnf + 4) * i2cclk;
532
533 scldel_min = setup->rise_time + specs->sudat_min;
534
535 if (sdadel_min < 0)
536 sdadel_min = 0;
537 if (sdadel_max < 0)
538 sdadel_max = 0;
539
540 log_debug("SDADEL(min/max): %i/%i, SCLDEL(Min): %i\n",
541 sdadel_min, sdadel_max, scldel_min);
542
543 /* Compute possible values for PRESC, SCLDEL and SDADEL */
544 for (p = 0; p < STM32_PRESC_MAX; p++) {
545 for (l = 0; l < STM32_SCLDEL_MAX; l++) {
546 int scldel = (l + 1) * (p + 1) * i2cclk;
547
548 if (scldel < scldel_min)
549 continue;
550
551 for (a = 0; a < STM32_SDADEL_MAX; a++) {
552 int sdadel = (a * (p + 1) + 1) * i2cclk;
553
554 if (((sdadel >= sdadel_min) &&
555 (sdadel <= sdadel_max)) &&
556 (p != p_prev)) {
557 v = calloc(1, sizeof(*v));
558 if (!v)
559 return -ENOMEM;
560
561 v->presc = p;
562 v->scldel = l;
563 v->sdadel = a;
564 p_prev = p;
565
566 list_add_tail(&v->node, solutions);
567 break;
568 }
569 }
570
571 if (p_prev == p)
572 break;
573 }
574 }
575
576 if (list_empty(solutions)) {
577 log_err("no Prescaler solution\n");
578 ret = -EPERM;
579 }
580
581 return ret;
582 }
583
stm32_i2c_choose_solution(struct stm32_i2c_setup * setup,const struct stm32_i2c_spec * specs,struct list_head * solutions,struct stm32_i2c_timings * s)584 static int stm32_i2c_choose_solution(struct stm32_i2c_setup *setup,
585 const struct stm32_i2c_spec *specs,
586 struct list_head *solutions,
587 struct stm32_i2c_timings *s)
588 {
589 struct stm32_i2c_timings *v;
590 u32 i2cbus = DIV_ROUND_CLOSEST(STM32_NSEC_PER_SEC,
591 setup->speed_freq);
592 u32 clk_error_prev = i2cbus;
593 u32 i2cclk = DIV_ROUND_CLOSEST(STM32_NSEC_PER_SEC,
594 setup->clock_src);
595 u32 clk_min, clk_max;
596 u32 af_delay_min;
597 u32 dnf_delay;
598 u32 tsync;
599 u16 l, h;
600 bool sol_found = false;
601 int ret = 0;
602
603 af_delay_min = setup->analog_filter ?
604 STM32_I2C_ANALOG_FILTER_DELAY_MIN : 0;
605 dnf_delay = setup->dnf * i2cclk;
606
607 tsync = af_delay_min + dnf_delay + (2 * i2cclk);
608 clk_max = STM32_NSEC_PER_SEC / specs->rate_min;
609 clk_min = STM32_NSEC_PER_SEC / specs->rate_max;
610
611 /*
612 * Among Prescaler possibilities discovered above figures out SCL Low
613 * and High Period. Provided:
614 * - SCL Low Period has to be higher than Low Period of the SCL Clock
615 * defined by I2C Specification. I2C Clock has to be lower than
616 * (SCL Low Period - Analog/Digital filters) / 4.
617 * - SCL High Period has to be lower than High Period of the SCL Clock
618 * defined by I2C Specification
619 * - I2C Clock has to be lower than SCL High Period
620 */
621 list_for_each_entry(v, solutions, node) {
622 u32 prescaler = (v->presc + 1) * i2cclk;
623
624 for (l = 0; l < STM32_SCLL_MAX; l++) {
625 u32 tscl_l = (l + 1) * prescaler + tsync;
626
627 if (tscl_l < specs->l_min ||
628 (i2cclk >=
629 ((tscl_l - af_delay_min - dnf_delay) / 4))) {
630 continue;
631 }
632
633 for (h = 0; h < STM32_SCLH_MAX; h++) {
634 u32 tscl_h = (h + 1) * prescaler + tsync;
635 u32 tscl = tscl_l + tscl_h +
636 setup->rise_time + setup->fall_time;
637
638 if ((tscl >= clk_min) && (tscl <= clk_max) &&
639 (tscl_h >= specs->h_min) &&
640 (i2cclk < tscl_h)) {
641 u32 clk_error;
642
643 if (tscl > i2cbus)
644 clk_error = tscl - i2cbus;
645 else
646 clk_error = i2cbus - tscl;
647
648 if (clk_error < clk_error_prev) {
649 clk_error_prev = clk_error;
650 v->scll = l;
651 v->sclh = h;
652 sol_found = true;
653 memcpy(s, v, sizeof(*s));
654 }
655 }
656 }
657 }
658 }
659
660 if (!sol_found) {
661 log_err("no solution at all\n");
662 ret = -EPERM;
663 }
664
665 return ret;
666 }
667
get_specs(u32 rate)668 static const struct stm32_i2c_spec *get_specs(u32 rate)
669 {
670 unsigned int i;
671
672 for (i = 0; i < ARRAY_SIZE(i2c_specs); i++)
673 if (rate <= i2c_specs[i].rate)
674 return &i2c_specs[i];
675
676 /* NOT REACHED */
677 return ERR_PTR(-EINVAL);
678 }
679
stm32_i2c_compute_timing(struct stm32_i2c_priv * i2c_priv,struct stm32_i2c_setup * setup,struct stm32_i2c_timings * output)680 static int stm32_i2c_compute_timing(struct stm32_i2c_priv *i2c_priv,
681 struct stm32_i2c_setup *setup,
682 struct stm32_i2c_timings *output)
683 {
684 const struct stm32_i2c_spec *specs;
685 struct stm32_i2c_timings *v, *_v;
686 struct list_head solutions;
687 int ret;
688
689 specs = get_specs(setup->speed_freq);
690 if (specs == ERR_PTR(-EINVAL)) {
691 log_err("speed out of bound {%d}\n",
692 setup->speed_freq);
693 return -EINVAL;
694 }
695
696 if (setup->rise_time > specs->rise_max ||
697 setup->fall_time > specs->fall_max) {
698 log_err("timings out of bound Rise{%d>%d}/Fall{%d>%d}\n",
699 setup->rise_time, specs->rise_max,
700 setup->fall_time, specs->fall_max);
701 return -EINVAL;
702 }
703
704 if (setup->dnf > STM32_I2C_DNF_MAX) {
705 log_err("DNF out of bound %d/%d\n",
706 setup->dnf, STM32_I2C_DNF_MAX);
707 return -EINVAL;
708 }
709
710 INIT_LIST_HEAD(&solutions);
711 ret = stm32_i2c_compute_solutions(setup, specs, &solutions);
712 if (ret)
713 goto exit;
714
715 ret = stm32_i2c_choose_solution(setup, specs, &solutions, output);
716 if (ret)
717 goto exit;
718
719 log_debug("Presc: %i, scldel: %i, sdadel: %i, scll: %i, sclh: %i\n",
720 output->presc,
721 output->scldel, output->sdadel,
722 output->scll, output->sclh);
723
724 exit:
725 /* Release list and memory */
726 list_for_each_entry_safe(v, _v, &solutions, node) {
727 list_del(&v->node);
728 free(v);
729 }
730
731 return ret;
732 }
733
get_lower_rate(u32 rate)734 static u32 get_lower_rate(u32 rate)
735 {
736 int i;
737
738 for (i = ARRAY_SIZE(i2c_specs) - 1; i >= 0; i--)
739 if (rate > i2c_specs[i].rate)
740 return i2c_specs[i].rate;
741
742 return i2c_specs[0].rate;
743 }
744
stm32_i2c_setup_timing(struct stm32_i2c_priv * i2c_priv,struct stm32_i2c_timings * timing)745 static int stm32_i2c_setup_timing(struct stm32_i2c_priv *i2c_priv,
746 struct stm32_i2c_timings *timing)
747 {
748 struct stm32_i2c_setup *setup = i2c_priv->setup;
749 int ret = 0;
750
751 setup->speed_freq = i2c_priv->speed;
752 setup->clock_src = clk_get_rate(&i2c_priv->clk);
753
754 if (!setup->clock_src) {
755 log_err("clock rate is 0\n");
756 return -EINVAL;
757 }
758
759 do {
760 ret = stm32_i2c_compute_timing(i2c_priv, setup, timing);
761 if (ret) {
762 log_debug("failed to compute I2C timings.\n");
763 if (setup->speed_freq > I2C_SPEED_STANDARD_RATE) {
764 setup->speed_freq =
765 get_lower_rate(setup->speed_freq);
766 log_debug("downgrade I2C Speed Freq to (%i)\n",
767 setup->speed_freq);
768 } else {
769 break;
770 }
771 }
772 } while (ret);
773
774 if (ret) {
775 log_err("impossible to compute I2C timings.\n");
776 return ret;
777 }
778
779 log_debug("I2C Freq(%i), Clk Source(%i)\n",
780 setup->speed_freq, setup->clock_src);
781 log_debug("I2C Rise(%i) and Fall(%i) Time\n",
782 setup->rise_time, setup->fall_time);
783 log_debug("I2C Analog Filter(%s), DNF(%i)\n",
784 setup->analog_filter ? "On" : "Off", setup->dnf);
785
786 i2c_priv->speed = setup->speed_freq;
787
788 return 0;
789 }
790
stm32_i2c_write_fm_plus_bits(struct stm32_i2c_priv * i2c_priv)791 static int stm32_i2c_write_fm_plus_bits(struct stm32_i2c_priv *i2c_priv)
792 {
793 int ret;
794 bool enable = i2c_priv->speed > I2C_SPEED_FAST_RATE;
795
796 /* Optional */
797 if (IS_ERR_OR_NULL(i2c_priv->regmap))
798 return 0;
799
800 if (i2c_priv->regmap_sreg == i2c_priv->regmap_creg)
801 ret = regmap_update_bits(i2c_priv->regmap,
802 i2c_priv->regmap_sreg,
803 i2c_priv->regmap_mask,
804 enable ? i2c_priv->regmap_mask : 0);
805 else
806 ret = regmap_write(i2c_priv->regmap,
807 enable ? i2c_priv->regmap_sreg :
808 i2c_priv->regmap_creg,
809 i2c_priv->regmap_mask);
810
811 return ret;
812 }
813
stm32_i2c_hw_config(struct stm32_i2c_priv * i2c_priv)814 static int stm32_i2c_hw_config(struct stm32_i2c_priv *i2c_priv)
815 {
816 struct stm32_i2c_regs *regs = i2c_priv->regs;
817 struct stm32_i2c_timings t;
818 int ret;
819 u32 timing = 0;
820
821 ret = stm32_i2c_setup_timing(i2c_priv, &t);
822 if (ret)
823 return ret;
824
825 /* Disable I2C */
826 clrbits_le32(®s->cr1, STM32_I2C_CR1_PE);
827
828 /* Setup Fast mode plus if necessary */
829 ret = stm32_i2c_write_fm_plus_bits(i2c_priv);
830 if (ret)
831 return ret;
832
833 /* Timing settings */
834 timing |= STM32_I2C_TIMINGR_PRESC(t.presc);
835 timing |= STM32_I2C_TIMINGR_SCLDEL(t.scldel);
836 timing |= STM32_I2C_TIMINGR_SDADEL(t.sdadel);
837 timing |= STM32_I2C_TIMINGR_SCLH(t.sclh);
838 timing |= STM32_I2C_TIMINGR_SCLL(t.scll);
839 writel(timing, ®s->timingr);
840
841 /* Enable I2C */
842 if (i2c_priv->setup->analog_filter)
843 clrbits_le32(®s->cr1, STM32_I2C_CR1_ANFOFF);
844 else
845 setbits_le32(®s->cr1, STM32_I2C_CR1_ANFOFF);
846 setbits_le32(®s->cr1, STM32_I2C_CR1_PE);
847
848 return 0;
849 }
850
stm32_i2c_set_bus_speed(struct udevice * dev,unsigned int speed)851 static int stm32_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
852 {
853 struct stm32_i2c_priv *i2c_priv = dev_get_priv(dev);
854
855 if (speed > I2C_SPEED_FAST_PLUS_RATE) {
856 dev_dbg(dev, "Speed %d not supported\n", speed);
857 return -EINVAL;
858 }
859
860 i2c_priv->speed = speed;
861
862 return stm32_i2c_hw_config(i2c_priv);
863 }
864
stm32_i2c_probe(struct udevice * dev)865 static int stm32_i2c_probe(struct udevice *dev)
866 {
867 struct stm32_i2c_priv *i2c_priv = dev_get_priv(dev);
868 struct reset_ctl reset_ctl;
869 fdt_addr_t addr;
870 int ret;
871
872 addr = dev_read_addr(dev);
873 if (addr == FDT_ADDR_T_NONE)
874 return -EINVAL;
875
876 i2c_priv->regs = (struct stm32_i2c_regs *)addr;
877
878 ret = clk_get_by_index(dev, 0, &i2c_priv->clk);
879 if (ret)
880 return ret;
881
882 ret = clk_enable(&i2c_priv->clk);
883 if (ret)
884 goto clk_free;
885
886 ret = reset_get_by_index(dev, 0, &reset_ctl);
887 if (ret)
888 goto clk_disable;
889
890 reset_assert(&reset_ctl);
891 udelay(2);
892 reset_deassert(&reset_ctl);
893
894 return 0;
895
896 clk_disable:
897 clk_disable(&i2c_priv->clk);
898 clk_free:
899 clk_free(&i2c_priv->clk);
900
901 return ret;
902 }
903
stm32_of_to_plat(struct udevice * dev)904 static int stm32_of_to_plat(struct udevice *dev)
905 {
906 struct stm32_i2c_priv *i2c_priv = dev_get_priv(dev);
907 u32 rise_time, fall_time;
908 int ret;
909
910 i2c_priv->setup = (struct stm32_i2c_setup *)dev_get_driver_data(dev);
911 if (!i2c_priv->setup)
912 return -EINVAL;
913
914 rise_time = dev_read_u32_default(dev, "i2c-scl-rising-time-ns", 0);
915 if (rise_time)
916 i2c_priv->setup->rise_time = rise_time;
917
918 fall_time = dev_read_u32_default(dev, "i2c-scl-falling-time-ns", 0);
919 if (fall_time)
920 i2c_priv->setup->fall_time = fall_time;
921
922 /* Optional */
923 i2c_priv->regmap = syscon_regmap_lookup_by_phandle(dev,
924 "st,syscfg-fmp");
925 if (!IS_ERR(i2c_priv->regmap)) {
926 u32 fmp[3];
927
928 ret = dev_read_u32_array(dev, "st,syscfg-fmp", fmp, 3);
929 if (ret)
930 return ret;
931
932 i2c_priv->regmap_sreg = fmp[1];
933 i2c_priv->regmap_creg = fmp[1] +
934 i2c_priv->setup->fmp_clr_offset;
935 i2c_priv->regmap_mask = fmp[2];
936 }
937
938 return 0;
939 }
940
941 static const struct dm_i2c_ops stm32_i2c_ops = {
942 .xfer = stm32_i2c_xfer,
943 .set_bus_speed = stm32_i2c_set_bus_speed,
944 };
945
946 static const struct udevice_id stm32_i2c_of_match[] = {
947 { .compatible = "st,stm32f7-i2c", .data = (ulong)&stm32f7_setup },
948 { .compatible = "st,stm32mp15-i2c", .data = (ulong)&stm32mp15_setup },
949 {}
950 };
951
952 U_BOOT_DRIVER(stm32f7_i2c) = {
953 .name = "stm32f7-i2c",
954 .id = UCLASS_I2C,
955 .of_match = stm32_i2c_of_match,
956 .of_to_plat = stm32_of_to_plat,
957 .probe = stm32_i2c_probe,
958 .priv_auto = sizeof(struct stm32_i2c_priv),
959 .ops = &stm32_i2c_ops,
960 };
961