1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * LPC32xx Ethernet MAC interface driver
4 *
5 * (C) Copyright 2014 DENX Software Engineering GmbH
6 * Written-by: Albert ARIBAUD - 3ADEV <albert.aribaud@3adev.fr>
7 */
8
9 #include <common.h>
10 #include <log.h>
11 #include <net.h>
12 #include <malloc.h>
13 #include <miiphy.h>
14 #include <asm/io.h>
15 #include <linux/delay.h>
16 #include <linux/errno.h>
17 #include <asm/types.h>
18 #include <asm/system.h>
19 #include <asm/byteorder.h>
20 #include <asm/arch/cpu.h>
21 #include <asm/arch/config.h>
22
23 /*
24 * Notes:
25 *
26 * 1. Unless specified otherwise, all references to tables or paragraphs
27 * are to UM10326, "LPC32x0 and LPC32x0/01 User manual".
28 *
29 * 2. Only bitfield masks/values which are actually used by the driver
30 * are defined.
31 */
32
33 /* a single RX descriptor. The controller has an array of these */
34 struct lpc32xx_eth_rxdesc {
35 u32 packet; /* Receive packet pointer */
36 u32 control; /* Descriptor command status */
37 };
38
39 #define LPC32XX_ETH_RX_DESC_SIZE (sizeof(struct lpc32xx_eth_rxdesc))
40
41 /* RX control bitfields/masks (see Table 330) */
42 #define LPC32XX_ETH_RX_CTRL_SIZE_MASK 0x000007FF
43 #define LPC32XX_ETH_RX_CTRL_UNUSED 0x7FFFF800
44 #define LPC32XX_ETH_RX_CTRL_INTERRUPT 0x80000000
45
46 /* a single RX status. The controller has an array of these */
47 struct lpc32xx_eth_rxstat {
48 u32 statusinfo; /* Transmit Descriptor status */
49 u32 statushashcrc; /* Transmit Descriptor CRCs */
50 };
51
52 #define LPC32XX_ETH_RX_STAT_SIZE (sizeof(struct lpc32xx_eth_rxstat))
53
54 /* RX statusinfo bitfields/masks (see Table 333) */
55 #define RX_STAT_RXSIZE 0x000007FF
56 /* Helper: OR of all errors except RANGE */
57 #define RX_STAT_ERRORS 0x1B800000
58
59 /* a single TX descriptor. The controller has an array of these */
60 struct lpc32xx_eth_txdesc {
61 u32 packet; /* Transmit packet pointer */
62 u32 control; /* Descriptor control */
63 };
64
65 #define LPC32XX_ETH_TX_DESC_SIZE (sizeof(struct lpc32xx_eth_txdesc))
66
67 /* TX control bitfields/masks (see Table 335) */
68 #define TX_CTRL_TXSIZE 0x000007FF
69 #define TX_CTRL_LAST 0x40000000
70
71 /* a single TX status. The controller has an array of these */
72 struct lpc32xx_eth_txstat {
73 u32 statusinfo; /* Transmit Descriptor status */
74 };
75
76 #define LPC32XX_ETH_TX_STAT_SIZE (sizeof(struct lpc32xx_eth_txstat))
77
78 /* Ethernet MAC interface registers (see Table 283) */
79 struct lpc32xx_eth_registers {
80 /* MAC registers - 0x3106_0000 to 0x3106_01FC */
81 u32 mac1; /* MAC configuration register 1 */
82 u32 mac2; /* MAC configuration register 2 */
83 u32 ipgt; /* Back-to-back Inter-Packet Gap reg. */
84 u32 ipgr; /* Non-back-to-back IPG register */
85 u32 clrt; /* Collision Window / Retry register */
86 u32 maxf; /* Maximum Frame register */
87 u32 supp; /* Phy Support register */
88 u32 test;
89 u32 mcfg; /* MII management configuration reg. */
90 u32 mcmd; /* MII management command register */
91 u32 madr; /* MII management address register */
92 u32 mwtd; /* MII management wite data register */
93 u32 mrdd; /* MII management read data register */
94 u32 mind; /* MII management indicators register */
95 u32 reserved1[2];
96 u32 sa0; /* Station address register 0 */
97 u32 sa1; /* Station address register 1 */
98 u32 sa2; /* Station address register 2 */
99 u32 reserved2[45];
100 /* Control registers */
101 u32 command;
102 u32 status;
103 u32 rxdescriptor;
104 u32 rxstatus;
105 u32 rxdescriptornumber; /* actually, number MINUS ONE */
106 u32 rxproduceindex; /* head of rx desc fifo */
107 u32 rxconsumeindex; /* tail of rx desc fifo */
108 u32 txdescriptor;
109 u32 txstatus;
110 u32 txdescriptornumber; /* actually, number MINUS ONE */
111 u32 txproduceindex; /* head of rx desc fifo */
112 u32 txconsumeindex; /* tail of rx desc fifo */
113 u32 reserved3[10];
114 u32 tsv0; /* Transmit status vector register 0 */
115 u32 tsv1; /* Transmit status vector register 1 */
116 u32 rsv; /* Receive status vector register */
117 u32 reserved4[3];
118 u32 flowcontrolcounter;
119 u32 flowcontrolstatus;
120 u32 reserved5[34];
121 /* RX filter registers - 0x3106_0200 to 0x3106_0FDC */
122 u32 rxfilterctrl;
123 u32 rxfilterwolstatus;
124 u32 rxfilterwolclear;
125 u32 reserved6;
126 u32 hashfilterl;
127 u32 hashfilterh;
128 u32 reserved7[882];
129 /* Module control registers - 0x3106_0FE0 to 0x3106_0FF8 */
130 u32 intstatus; /* Interrupt status register */
131 u32 intenable;
132 u32 intclear;
133 u32 intset;
134 u32 reserved8;
135 u32 powerdown;
136 u32 reserved9;
137 };
138
139 /* MAC1 register bitfields/masks and offsets (see Table 283) */
140 #define MAC1_RECV_ENABLE 0x00000001
141 #define MAC1_PASS_ALL_RX_FRAMES 0x00000002
142 #define MAC1_SOFT_RESET 0x00008000
143 /* Helper: general reset */
144 #define MAC1_RESETS 0x0000CF00
145
146 /* MAC2 register bitfields/masks and offsets (see Table 284) */
147 #define MAC2_FULL_DUPLEX 0x00000001
148 #define MAC2_CRC_ENABLE 0x00000010
149 #define MAC2_PAD_CRC_ENABLE 0x00000020
150
151 /* SUPP register bitfields/masks and offsets (see Table 290) */
152 #define SUPP_SPEED 0x00000100
153
154 /* MCFG register bitfields/masks and offsets (see Table 292) */
155 #define MCFG_RESET_MII_MGMT 0x00008000
156 /* divide clock by 28 (see Table 293) */
157 #define MCFG_CLOCK_SELECT_DIV28 0x0000001C
158
159 /* MADR register bitfields/masks and offsets (see Table 295) */
160 #define MADR_REG_MASK 0x0000001F
161 #define MADR_PHY_MASK 0x00001F00
162 #define MADR_REG_OFFSET 0
163 #define MADR_PHY_OFFSET 8
164
165 /* MIND register bitfields/masks (see Table 298) */
166 #define MIND_BUSY 0x00000001
167
168 /* COMMAND register bitfields/masks and offsets (see Table 283) */
169 #define COMMAND_RXENABLE 0x00000001
170 #define COMMAND_TXENABLE 0x00000002
171 #define COMMAND_PASSRUNTFRAME 0x00000040
172 #define COMMAND_RMII 0x00000200
173 #define COMMAND_FULL_DUPLEX 0x00000400
174 /* Helper: general reset */
175 #define COMMAND_RESETS 0x00000038
176
177 /* STATUS register bitfields/masks and offsets (see Table 283) */
178 #define STATUS_RXSTATUS 0x00000001
179 #define STATUS_TXSTATUS 0x00000002
180
181 /* RXFILTERCTRL register bitfields/masks (see Table 319) */
182 #define RXFILTERCTRL_ACCEPTBROADCAST 0x00000002
183 #define RXFILTERCTRL_ACCEPTPERFECT 0x00000020
184
185 /* Buffers and descriptors */
186
187 #define ATTRS(n) __aligned(n)
188
189 #define TX_BUF_COUNT 4
190 #define RX_BUF_COUNT 4
191
192 struct lpc32xx_eth_buffers {
193 ATTRS(4) struct lpc32xx_eth_txdesc tx_desc[TX_BUF_COUNT];
194 ATTRS(4) struct lpc32xx_eth_txstat tx_stat[TX_BUF_COUNT];
195 ATTRS(PKTALIGN) u8 tx_buf[TX_BUF_COUNT*PKTSIZE_ALIGN];
196 ATTRS(4) struct lpc32xx_eth_rxdesc rx_desc[RX_BUF_COUNT];
197 ATTRS(8) struct lpc32xx_eth_rxstat rx_stat[RX_BUF_COUNT];
198 ATTRS(PKTALIGN) u8 rx_buf[RX_BUF_COUNT*PKTSIZE_ALIGN];
199 };
200
201 /* port device data struct */
202 struct lpc32xx_eth_device {
203 struct eth_device dev;
204 struct lpc32xx_eth_registers *regs;
205 struct lpc32xx_eth_buffers *bufs;
206 bool phy_rmii;
207 };
208
209 #define LPC32XX_ETH_DEVICE_SIZE (sizeof(struct lpc32xx_eth_device))
210
211 /* generic macros */
212 #define to_lpc32xx_eth(_d) container_of(_d, struct lpc32xx_eth_device, dev)
213
214 /* timeout for MII polling */
215 #define MII_TIMEOUT 10000000
216
217 /* limits for PHY and register addresses */
218 #define MII_MAX_REG (MADR_REG_MASK >> MADR_REG_OFFSET)
219
220 #define MII_MAX_PHY (MADR_PHY_MASK >> MADR_PHY_OFFSET)
221
222 #if defined(CONFIG_PHYLIB) || defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
223 /*
224 * mii_reg_read - miiphy_read callback function.
225 *
226 * Returns 16bit phy register value, or 0xffff on error
227 */
mii_reg_read(struct mii_dev * bus,int phy_adr,int devad,int reg_ofs)228 static int mii_reg_read(struct mii_dev *bus, int phy_adr, int devad,
229 int reg_ofs)
230 {
231 u16 data = 0;
232 struct eth_device *dev = eth_get_dev_by_name(bus->name);
233 struct lpc32xx_eth_device *dlpc32xx_eth = to_lpc32xx_eth(dev);
234 struct lpc32xx_eth_registers *regs = dlpc32xx_eth->regs;
235 u32 mind_reg;
236 u32 timeout;
237
238 /* check parameters */
239 if (phy_adr > MII_MAX_PHY) {
240 printf("%s:%u: Invalid PHY address %d\n",
241 __func__, __LINE__, phy_adr);
242 return -EFAULT;
243 }
244 if (reg_ofs > MII_MAX_REG) {
245 printf("%s:%u: Invalid register offset %d\n",
246 __func__, __LINE__, reg_ofs);
247 return -EFAULT;
248 }
249
250 /* write the phy and reg addressse into the MII address reg */
251 writel((phy_adr << MADR_PHY_OFFSET) | (reg_ofs << MADR_REG_OFFSET),
252 ®s->madr);
253
254 /* write 1 to the MII command register to cause a read */
255 writel(1, ®s->mcmd);
256
257 /* wait till the MII is not busy */
258 timeout = MII_TIMEOUT;
259 do {
260 /* read MII indicators register */
261 mind_reg = readl(®s->mind);
262 if (--timeout == 0)
263 break;
264 } while (mind_reg & MIND_BUSY);
265
266 /* write 0 to the MII command register to finish the read */
267 writel(0, ®s->mcmd);
268
269 if (timeout == 0) {
270 printf("%s:%u: MII busy timeout\n", __func__, __LINE__);
271 return -EFAULT;
272 }
273
274 data = (u16) readl(®s->mrdd);
275
276 debug("%s:(adr %d, off %d) => %04x\n", __func__, phy_adr,
277 reg_ofs, data);
278
279 return data;
280 }
281
282 /*
283 * mii_reg_write - imiiphy_write callback function.
284 *
285 * Returns 0 if write succeed, -EINVAL on bad parameters
286 * -ETIME on timeout
287 */
mii_reg_write(struct mii_dev * bus,int phy_adr,int devad,int reg_ofs,u16 data)288 static int mii_reg_write(struct mii_dev *bus, int phy_adr, int devad,
289 int reg_ofs, u16 data)
290 {
291 struct eth_device *dev = eth_get_dev_by_name(bus->name);
292 struct lpc32xx_eth_device *dlpc32xx_eth = to_lpc32xx_eth(dev);
293 struct lpc32xx_eth_registers *regs = dlpc32xx_eth->regs;
294 u32 mind_reg;
295 u32 timeout;
296
297 /* check parameters */
298 if (phy_adr > MII_MAX_PHY) {
299 printf("%s:%u: Invalid PHY address %d\n",
300 __func__, __LINE__, phy_adr);
301 return -EFAULT;
302 }
303 if (reg_ofs > MII_MAX_REG) {
304 printf("%s:%u: Invalid register offset %d\n",
305 __func__, __LINE__, reg_ofs);
306 return -EFAULT;
307 }
308
309 /* write the phy and reg addressse into the MII address reg */
310 writel((phy_adr << MADR_PHY_OFFSET) | (reg_ofs << MADR_REG_OFFSET),
311 ®s->madr);
312
313 /* write data to the MII write register */
314 writel(data, ®s->mwtd);
315
316 /* wait till the MII is not busy */
317 timeout = MII_TIMEOUT;
318 do {
319 /* read MII indicators register */
320 mind_reg = readl(®s->mind);
321 if (--timeout == 0)
322 break;
323 } while (mind_reg & MIND_BUSY);
324
325 if (timeout == 0) {
326 printf("%s:%u: MII busy timeout\n", __func__,
327 __LINE__);
328 return -EFAULT;
329 }
330
331 /*debug("%s:(adr %d, off %d) <= %04x\n", __func__, phy_adr,
332 reg_ofs, data);*/
333
334 return 0;
335 }
336 #endif
337
338 /*
339 * Provide default Ethernet buffers base address if target did not.
340 * Locate buffers in SRAM at 0x00001000 to avoid cache issues and
341 * maximize throughput.
342 */
343 #if !defined(CONFIG_LPC32XX_ETH_BUFS_BASE)
344 #define CONFIG_LPC32XX_ETH_BUFS_BASE 0x00001000
345 #endif
346
347 static struct lpc32xx_eth_device lpc32xx_eth = {
348 .regs = (struct lpc32xx_eth_registers *)LPC32XX_ETH_BASE,
349 .bufs = (struct lpc32xx_eth_buffers *)CONFIG_LPC32XX_ETH_BUFS_BASE,
350 #if defined(CONFIG_RMII)
351 .phy_rmii = true,
352 #endif
353 };
354
355 #define TX_TIMEOUT 10000
356
lpc32xx_eth_send(struct eth_device * dev,void * dataptr,int datasize)357 static int lpc32xx_eth_send(struct eth_device *dev, void *dataptr, int datasize)
358 {
359 struct lpc32xx_eth_device *lpc32xx_eth_device =
360 container_of(dev, struct lpc32xx_eth_device, dev);
361 struct lpc32xx_eth_registers *regs = lpc32xx_eth_device->regs;
362 struct lpc32xx_eth_buffers *bufs = lpc32xx_eth_device->bufs;
363 int timeout, tx_index;
364
365 /* time out if transmit descriptor array remains full too long */
366 timeout = TX_TIMEOUT;
367 while ((readl(®s->status) & STATUS_TXSTATUS) &&
368 (readl(®s->txconsumeindex)
369 == readl(®s->txproduceindex))) {
370 if (timeout-- == 0)
371 return -1;
372 }
373
374 /* determine next transmit packet index to use */
375 tx_index = readl(®s->txproduceindex);
376
377 /* set up transmit packet */
378 memcpy((void *)&bufs->tx_buf[tx_index * PKTSIZE_ALIGN],
379 (void *)dataptr, datasize);
380 writel(TX_CTRL_LAST | ((datasize - 1) & TX_CTRL_TXSIZE),
381 &bufs->tx_desc[tx_index].control);
382 writel(0, &bufs->tx_stat[tx_index].statusinfo);
383
384 /* pass transmit packet to DMA engine */
385 tx_index = (tx_index + 1) % TX_BUF_COUNT;
386 writel(tx_index, ®s->txproduceindex);
387
388 /* transmission succeeded */
389 return 0;
390 }
391
392 #define RX_TIMEOUT 1000000
393
lpc32xx_eth_recv(struct eth_device * dev)394 static int lpc32xx_eth_recv(struct eth_device *dev)
395 {
396 struct lpc32xx_eth_device *lpc32xx_eth_device =
397 container_of(dev, struct lpc32xx_eth_device, dev);
398 struct lpc32xx_eth_registers *regs = lpc32xx_eth_device->regs;
399 struct lpc32xx_eth_buffers *bufs = lpc32xx_eth_device->bufs;
400 int timeout, rx_index;
401
402 /* time out if receive descriptor array remains empty too long */
403 timeout = RX_TIMEOUT;
404 while (readl(®s->rxproduceindex) == readl(®s->rxconsumeindex)) {
405 if (timeout-- == 0)
406 return -1;
407 }
408
409 /* determine next receive packet index to use */
410 rx_index = readl(®s->rxconsumeindex);
411
412 /* if data was valid, pass it on */
413 if (!(bufs->rx_stat[rx_index].statusinfo & RX_STAT_ERRORS)) {
414 net_process_received_packet(
415 &(bufs->rx_buf[rx_index * PKTSIZE_ALIGN]),
416 (bufs->rx_stat[rx_index].statusinfo
417 & RX_STAT_RXSIZE) + 1);
418 }
419
420 /* pass receive slot back to DMA engine */
421 rx_index = (rx_index + 1) % RX_BUF_COUNT;
422 writel(rx_index, ®s->rxconsumeindex);
423
424 /* reception successful */
425 return 0;
426 }
427
lpc32xx_eth_write_hwaddr(struct eth_device * dev)428 static int lpc32xx_eth_write_hwaddr(struct eth_device *dev)
429 {
430 struct lpc32xx_eth_device *lpc32xx_eth_device =
431 container_of(dev, struct lpc32xx_eth_device, dev);
432 struct lpc32xx_eth_registers *regs = lpc32xx_eth_device->regs;
433
434 /* Save station address */
435 writel((unsigned long) (dev->enetaddr[0] |
436 (dev->enetaddr[1] << 8)), ®s->sa2);
437 writel((unsigned long) (dev->enetaddr[2] |
438 (dev->enetaddr[3] << 8)), ®s->sa1);
439 writel((unsigned long) (dev->enetaddr[4] |
440 (dev->enetaddr[5] << 8)), ®s->sa0);
441
442 return 0;
443 }
444
lpc32xx_eth_init(struct eth_device * dev)445 static int lpc32xx_eth_init(struct eth_device *dev)
446 {
447 struct lpc32xx_eth_device *lpc32xx_eth_device =
448 container_of(dev, struct lpc32xx_eth_device, dev);
449 struct lpc32xx_eth_registers *regs = lpc32xx_eth_device->regs;
450 struct lpc32xx_eth_buffers *bufs = lpc32xx_eth_device->bufs;
451 int index;
452
453 /* Initial MAC initialization */
454 writel(MAC1_PASS_ALL_RX_FRAMES, ®s->mac1);
455 writel(MAC2_PAD_CRC_ENABLE | MAC2_CRC_ENABLE, ®s->mac2);
456 writel(PKTSIZE_ALIGN, ®s->maxf);
457
458 /* Retries: 15 (0xF). Collision window: 57 (0x37). */
459 writel(0x370F, ®s->clrt);
460
461 /* Set IP gap pt 2 to default 0x12 but pt 1 to non-default 0 */
462 writel(0x0012, ®s->ipgr);
463
464 /* pass runt (smaller than 64 bytes) frames */
465 if (lpc32xx_eth_device->phy_rmii)
466 writel(COMMAND_PASSRUNTFRAME | COMMAND_RMII, ®s->command);
467 else
468 writel(COMMAND_PASSRUNTFRAME, ®s->command);
469
470 /* Configure Full/Half Duplex mode */
471 if (miiphy_duplex(dev->name, CONFIG_PHY_ADDR) == FULL) {
472 setbits_le32(®s->mac2, MAC2_FULL_DUPLEX);
473 setbits_le32(®s->command, COMMAND_FULL_DUPLEX);
474 writel(0x15, ®s->ipgt);
475 } else {
476 writel(0x12, ®s->ipgt);
477 }
478
479 /* Configure 100MBit/10MBit mode */
480 if (miiphy_speed(dev->name, CONFIG_PHY_ADDR) == _100BASET)
481 writel(SUPP_SPEED, ®s->supp);
482 else
483 writel(0, ®s->supp);
484
485 /* Save station address */
486 writel((unsigned long) (dev->enetaddr[0] |
487 (dev->enetaddr[1] << 8)), ®s->sa2);
488 writel((unsigned long) (dev->enetaddr[2] |
489 (dev->enetaddr[3] << 8)), ®s->sa1);
490 writel((unsigned long) (dev->enetaddr[4] |
491 (dev->enetaddr[5] << 8)), ®s->sa0);
492
493 /* set up transmit buffers */
494 for (index = 0; index < TX_BUF_COUNT; index++) {
495 bufs->tx_desc[index].control = 0;
496 bufs->tx_stat[index].statusinfo = 0;
497 }
498 writel((u32)(&bufs->tx_desc), (u32 *)®s->txdescriptor);
499 writel((u32)(&bufs->tx_stat), ®s->txstatus);
500 writel(TX_BUF_COUNT-1, ®s->txdescriptornumber);
501
502 /* set up receive buffers */
503 for (index = 0; index < RX_BUF_COUNT; index++) {
504 bufs->rx_desc[index].packet =
505 (u32) (bufs->rx_buf+index*PKTSIZE_ALIGN);
506 bufs->rx_desc[index].control = PKTSIZE_ALIGN - 1;
507 bufs->rx_stat[index].statusinfo = 0;
508 bufs->rx_stat[index].statushashcrc = 0;
509 }
510 writel((u32)(&bufs->rx_desc), ®s->rxdescriptor);
511 writel((u32)(&bufs->rx_stat), ®s->rxstatus);
512 writel(RX_BUF_COUNT-1, ®s->rxdescriptornumber);
513
514 /* set up transmit buffers */
515 for (index = 0; index < TX_BUF_COUNT; index++)
516 bufs->tx_desc[index].packet =
517 (u32)(bufs->tx_buf + index * PKTSIZE_ALIGN);
518
519 /* Enable broadcast and matching address packets */
520 writel(RXFILTERCTRL_ACCEPTBROADCAST |
521 RXFILTERCTRL_ACCEPTPERFECT, ®s->rxfilterctrl);
522
523 /* Clear and disable interrupts */
524 writel(0xFFFF, ®s->intclear);
525 writel(0, ®s->intenable);
526
527 /* Enable receive and transmit mode of MAC ethernet core */
528 setbits_le32(®s->command, COMMAND_RXENABLE | COMMAND_TXENABLE);
529 setbits_le32(®s->mac1, MAC1_RECV_ENABLE);
530
531 /*
532 * Perform a 'dummy' first send to work around Ethernet.1
533 * erratum (see ES_LPC3250 rev. 9 dated 1 June 2011).
534 * Use zeroed "index" variable as the dummy.
535 */
536
537 index = 0;
538 lpc32xx_eth_send(dev, &index, 4);
539
540 return 0;
541 }
542
lpc32xx_eth_halt(struct eth_device * dev)543 static int lpc32xx_eth_halt(struct eth_device *dev)
544 {
545 struct lpc32xx_eth_device *lpc32xx_eth_device =
546 container_of(dev, struct lpc32xx_eth_device, dev);
547 struct lpc32xx_eth_registers *regs = lpc32xx_eth_device->regs;
548
549 /* Reset all MAC logic */
550 writel(MAC1_RESETS, ®s->mac1);
551 writel(COMMAND_RESETS, ®s->command);
552 /* Let reset condition settle */
553 udelay(2000);
554
555 return 0;
556 }
557
558 #if defined(CONFIG_PHYLIB)
lpc32xx_eth_phylib_init(struct eth_device * dev,int phyid)559 int lpc32xx_eth_phylib_init(struct eth_device *dev, int phyid)
560 {
561 struct lpc32xx_eth_device *lpc32xx_eth_device =
562 container_of(dev, struct lpc32xx_eth_device, dev);
563 struct mii_dev *bus;
564 struct phy_device *phydev;
565 int ret;
566
567 bus = mdio_alloc();
568 if (!bus) {
569 printf("mdio_alloc failed\n");
570 return -ENOMEM;
571 }
572 bus->read = mii_reg_read;
573 bus->write = mii_reg_write;
574 strcpy(bus->name, dev->name);
575
576 ret = mdio_register(bus);
577 if (ret) {
578 printf("mdio_register failed\n");
579 free(bus);
580 return -ENOMEM;
581 }
582
583 if (lpc32xx_eth_device->phy_rmii)
584 phydev = phy_connect(bus, phyid, dev, PHY_INTERFACE_MODE_RMII);
585 else
586 phydev = phy_connect(bus, phyid, dev, PHY_INTERFACE_MODE_MII);
587
588 if (!phydev) {
589 printf("phy_connect failed\n");
590 return -ENODEV;
591 }
592
593 phy_config(phydev);
594 phy_startup(phydev);
595
596 return 0;
597 }
598 #endif
599
lpc32xx_eth_initialize(struct bd_info * bis)600 int lpc32xx_eth_initialize(struct bd_info *bis)
601 {
602 struct eth_device *dev = &lpc32xx_eth.dev;
603 struct lpc32xx_eth_registers *regs = lpc32xx_eth.regs;
604
605 /*
606 * Set RMII management clock rate. With HCLK at 104 MHz and
607 * a divider of 28, this will be 3.72 MHz.
608 */
609 writel(MCFG_RESET_MII_MGMT, ®s->mcfg);
610 writel(MCFG_CLOCK_SELECT_DIV28, ®s->mcfg);
611
612 /* Reset all MAC logic */
613 writel(MAC1_RESETS, ®s->mac1);
614 writel(COMMAND_RESETS, ®s->command);
615
616 /* wait 10 ms for the whole I/F to reset */
617 udelay(10000);
618
619 /* must be less than sizeof(dev->name) */
620 strcpy(dev->name, "eth0");
621
622 dev->init = (void *)lpc32xx_eth_init;
623 dev->halt = (void *)lpc32xx_eth_halt;
624 dev->send = (void *)lpc32xx_eth_send;
625 dev->recv = (void *)lpc32xx_eth_recv;
626 dev->write_hwaddr = (void *)lpc32xx_eth_write_hwaddr;
627
628 /* Release SOFT reset to let MII talk to PHY */
629 clrbits_le32(®s->mac1, MAC1_SOFT_RESET);
630
631 /* register driver before talking to phy */
632 eth_register(dev);
633
634 #if defined(CONFIG_PHYLIB)
635 lpc32xx_eth_phylib_init(dev, CONFIG_PHY_ADDR);
636 #elif defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
637 int retval;
638 struct mii_dev *mdiodev = mdio_alloc();
639 if (!mdiodev)
640 return -ENOMEM;
641 strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
642 mdiodev->read = mii_reg_read;
643 mdiodev->write = mii_reg_write;
644
645 retval = mdio_register(mdiodev);
646 if (retval < 0)
647 return retval;
648 #endif
649
650 return 0;
651 }
652