1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Rockchip DesignWare based PCIe host controller driver
4 *
5 * Copyright (c) 2021 Rockchip, Inc.
6 */
7
8 #include <common.h>
9 #include <clk.h>
10 #include <dm.h>
11 #include <generic-phy.h>
12 #include <pci.h>
13 #include <power-domain.h>
14 #include <reset.h>
15 #include <syscon.h>
16 #include <asm/arch-rockchip/clock.h>
17 #include <asm/global_data.h>
18 #include <asm/io.h>
19 #include <asm-generic/gpio.h>
20 #include <dm/device_compat.h>
21 #include <linux/iopoll.h>
22 #include <linux/delay.h>
23 #include <power/regulator.h>
24
25 #include "pcie_dw_common.h"
26
27 DECLARE_GLOBAL_DATA_PTR;
28
29 /**
30 * struct rk_pcie - RK DW PCIe controller state
31 *
32 * @vpcie3v3: The 3.3v power supply for slot
33 * @apb_base: The base address of vendor regs
34 * @rst_gpio: The #PERST signal for slot
35 */
36 struct rk_pcie {
37 /* Must be first member of the struct */
38 struct pcie_dw dw;
39 struct udevice *vpcie3v3;
40 void *apb_base;
41 struct phy phy;
42 struct clk_bulk clks;
43 struct reset_ctl_bulk rsts;
44 struct gpio_desc rst_gpio;
45 };
46
47 /* Parameters for the waiting for iATU enabled routine */
48 #define PCIE_CLIENT_GENERAL_DEBUG 0x104
49 #define PCIE_CLIENT_HOT_RESET_CTRL 0x180
50 #define PCIE_LTSSM_ENABLE_ENHANCE BIT(4)
51 #define PCIE_CLIENT_LTSSM_STATUS 0x300
52 #define SMLH_LINKUP BIT(16)
53 #define RDLH_LINKUP BIT(17)
54 #define PCIE_CLIENT_DBG_FIFO_MODE_CON 0x310
55 #define PCIE_CLIENT_DBG_FIFO_PTN_HIT_D0 0x320
56 #define PCIE_CLIENT_DBG_FIFO_PTN_HIT_D1 0x324
57 #define PCIE_CLIENT_DBG_FIFO_TRN_HIT_D0 0x328
58 #define PCIE_CLIENT_DBG_FIFO_TRN_HIT_D1 0x32c
59 #define PCIE_CLIENT_DBG_FIFO_STATUS 0x350
60 #define PCIE_CLIENT_DBG_TRANSITION_DATA 0xffff0000
61 #define PCIE_CLIENT_DBF_EN 0xffff0003
62
63 /* Parameters for the waiting for #perst signal */
64 #define PERST_WAIT_MS 1000
65
rk_pcie_read(void __iomem * addr,int size,u32 * val)66 static int rk_pcie_read(void __iomem *addr, int size, u32 *val)
67 {
68 if ((uintptr_t)addr & (size - 1)) {
69 *val = 0;
70 return PCIBIOS_UNSUPPORTED;
71 }
72
73 if (size == 4) {
74 *val = readl(addr);
75 } else if (size == 2) {
76 *val = readw(addr);
77 } else if (size == 1) {
78 *val = readb(addr);
79 } else {
80 *val = 0;
81 return -ENODEV;
82 }
83
84 return 0;
85 }
86
rk_pcie_write(void __iomem * addr,int size,u32 val)87 static int rk_pcie_write(void __iomem *addr, int size, u32 val)
88 {
89 if ((uintptr_t)addr & (size - 1))
90 return PCIBIOS_UNSUPPORTED;
91
92 if (size == 4)
93 writel(val, addr);
94 else if (size == 2)
95 writew(val, addr);
96 else if (size == 1)
97 writeb(val, addr);
98 else
99 return -ENODEV;
100
101 return 0;
102 }
103
__rk_pcie_read_apb(struct rk_pcie * rk_pcie,void __iomem * base,u32 reg,size_t size)104 static u32 __rk_pcie_read_apb(struct rk_pcie *rk_pcie, void __iomem *base,
105 u32 reg, size_t size)
106 {
107 int ret;
108 u32 val;
109
110 ret = rk_pcie_read(base + reg, size, &val);
111 if (ret)
112 dev_err(rk_pcie->dw.dev, "Read APB address failed\n");
113
114 return val;
115 }
116
__rk_pcie_write_apb(struct rk_pcie * rk_pcie,void __iomem * base,u32 reg,size_t size,u32 val)117 static void __rk_pcie_write_apb(struct rk_pcie *rk_pcie, void __iomem *base,
118 u32 reg, size_t size, u32 val)
119 {
120 int ret;
121
122 ret = rk_pcie_write(base + reg, size, val);
123 if (ret)
124 dev_err(rk_pcie->dw.dev, "Write APB address failed\n");
125 }
126
127 /**
128 * rk_pcie_readl_apb() - Read vendor regs
129 *
130 * @rk_pcie: Pointer to the PCI controller state
131 * @reg: Offset of regs
132 */
rk_pcie_readl_apb(struct rk_pcie * rk_pcie,u32 reg)133 static inline u32 rk_pcie_readl_apb(struct rk_pcie *rk_pcie, u32 reg)
134 {
135 return __rk_pcie_read_apb(rk_pcie, rk_pcie->apb_base, reg, 0x4);
136 }
137
138 /**
139 * rk_pcie_writel_apb() - Write vendor regs
140 *
141 * @rk_pcie: Pointer to the PCI controller state
142 * @reg: Offset of regs
143 * @val: Value to be writen
144 */
rk_pcie_writel_apb(struct rk_pcie * rk_pcie,u32 reg,u32 val)145 static inline void rk_pcie_writel_apb(struct rk_pcie *rk_pcie, u32 reg,
146 u32 val)
147 {
148 __rk_pcie_write_apb(rk_pcie, rk_pcie->apb_base, reg, 0x4, val);
149 }
150
151 /**
152 * rk_pcie_configure() - Configure link capabilities and speed
153 *
154 * @rk_pcie: Pointer to the PCI controller state
155 * @cap_speed: The capabilities and speed to configure
156 *
157 * Configure the link capabilities and speed in the PCIe root complex.
158 */
rk_pcie_configure(struct rk_pcie * pci,u32 cap_speed)159 static void rk_pcie_configure(struct rk_pcie *pci, u32 cap_speed)
160 {
161 u32 val;
162
163 dw_pcie_dbi_write_enable(&pci->dw, true);
164
165 clrsetbits_le32(pci->dw.dbi_base + PCIE_LINK_CAPABILITY,
166 TARGET_LINK_SPEED_MASK, cap_speed);
167
168 clrsetbits_le32(pci->dw.dbi_base + PCIE_LINK_CTL_2,
169 TARGET_LINK_SPEED_MASK, cap_speed);
170
171 dw_pcie_dbi_write_enable(&pci->dw, false);
172 }
173
rk_pcie_enable_debug(struct rk_pcie * rk_pcie)174 static void rk_pcie_enable_debug(struct rk_pcie *rk_pcie)
175 {
176 rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_PTN_HIT_D0,
177 PCIE_CLIENT_DBG_TRANSITION_DATA);
178 rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_PTN_HIT_D1,
179 PCIE_CLIENT_DBG_TRANSITION_DATA);
180 rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_TRN_HIT_D0,
181 PCIE_CLIENT_DBG_TRANSITION_DATA);
182 rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_TRN_HIT_D1,
183 PCIE_CLIENT_DBG_TRANSITION_DATA);
184 rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_MODE_CON,
185 PCIE_CLIENT_DBF_EN);
186 }
187
rk_pcie_debug_dump(struct rk_pcie * rk_pcie)188 static void rk_pcie_debug_dump(struct rk_pcie *rk_pcie)
189 {
190 u32 loop;
191
192 debug("ltssm = 0x%x\n",
193 rk_pcie_readl_apb(rk_pcie, PCIE_CLIENT_LTSSM_STATUS));
194 for (loop = 0; loop < 64; loop++)
195 debug("fifo_status = 0x%x\n",
196 rk_pcie_readl_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_STATUS));
197 }
198
rk_pcie_link_status_clear(struct rk_pcie * rk_pcie)199 static inline void rk_pcie_link_status_clear(struct rk_pcie *rk_pcie)
200 {
201 rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_GENERAL_DEBUG, 0x0);
202 }
203
rk_pcie_disable_ltssm(struct rk_pcie * rk_pcie)204 static inline void rk_pcie_disable_ltssm(struct rk_pcie *rk_pcie)
205 {
206 rk_pcie_writel_apb(rk_pcie, 0x0, 0xc0008);
207 }
208
rk_pcie_enable_ltssm(struct rk_pcie * rk_pcie)209 static inline void rk_pcie_enable_ltssm(struct rk_pcie *rk_pcie)
210 {
211 rk_pcie_writel_apb(rk_pcie, 0x0, 0xc000c);
212 }
213
is_link_up(struct rk_pcie * priv)214 static int is_link_up(struct rk_pcie *priv)
215 {
216 u32 val;
217
218 val = rk_pcie_readl_apb(priv, PCIE_CLIENT_LTSSM_STATUS);
219 if ((val & (RDLH_LINKUP | SMLH_LINKUP)) == 0x30000 &&
220 (val & GENMASK(5, 0)) == 0x11)
221 return 1;
222
223 return 0;
224 }
225
226 /**
227 * rk_pcie_link_up() - Wait for the link to come up
228 *
229 * @rk_pcie: Pointer to the PCI controller state
230 * @cap_speed: Desired link speed
231 *
232 * Return: 1 (true) for active line and negetive (false) for no link (timeout)
233 */
rk_pcie_link_up(struct rk_pcie * priv,u32 cap_speed)234 static int rk_pcie_link_up(struct rk_pcie *priv, u32 cap_speed)
235 {
236 int retries;
237
238 if (is_link_up(priv)) {
239 printf("PCI Link already up before configuration!\n");
240 return 1;
241 }
242
243 /* DW pre link configurations */
244 rk_pcie_configure(priv, cap_speed);
245
246 /* Rest the device */
247 if (dm_gpio_is_valid(&priv->rst_gpio)) {
248 dm_gpio_set_value(&priv->rst_gpio, 0);
249 /*
250 * Minimal is 100ms from spec but we see
251 * some wired devices need much more, such as 600ms.
252 * Add a enough delay to cover all cases.
253 */
254 msleep(PERST_WAIT_MS);
255 dm_gpio_set_value(&priv->rst_gpio, 1);
256 }
257
258 rk_pcie_disable_ltssm(priv);
259 rk_pcie_link_status_clear(priv);
260 rk_pcie_enable_debug(priv);
261
262 /* Enable LTSSM */
263 rk_pcie_enable_ltssm(priv);
264
265 for (retries = 0; retries < 5; retries++) {
266 if (is_link_up(priv)) {
267 dev_info(priv->dw.dev, "PCIe Link up, LTSSM is 0x%x\n",
268 rk_pcie_readl_apb(priv, PCIE_CLIENT_LTSSM_STATUS));
269 rk_pcie_debug_dump(priv);
270 return 0;
271 }
272
273 dev_info(priv->dw.dev, "PCIe Linking... LTSSM is 0x%x\n",
274 rk_pcie_readl_apb(priv, PCIE_CLIENT_LTSSM_STATUS));
275 rk_pcie_debug_dump(priv);
276 msleep(1000);
277 }
278
279 dev_err(priv->dw.dev, "PCIe-%d Link Fail\n", dev_seq(priv->dw.dev));
280 /* Link maybe in Gen switch recovery but we need to wait more 1s */
281 msleep(1000);
282 return -EIO;
283 }
284
rockchip_pcie_init_port(struct udevice * dev)285 static int rockchip_pcie_init_port(struct udevice *dev)
286 {
287 int ret;
288 u32 val;
289 struct rk_pcie *priv = dev_get_priv(dev);
290
291 /* Set power and maybe external ref clk input */
292 if (priv->vpcie3v3) {
293 ret = regulator_set_value(priv->vpcie3v3, 3300000);
294 if (ret) {
295 dev_err(priv->dw.dev, "failed to enable vpcie3v3 (ret=%d)\n",
296 ret);
297 return ret;
298 }
299 }
300
301 msleep(1000);
302
303 ret = generic_phy_init(&priv->phy);
304 if (ret) {
305 dev_err(dev, "failed to init phy (ret=%d)\n", ret);
306 return ret;
307 }
308
309 ret = generic_phy_power_on(&priv->phy);
310 if (ret) {
311 dev_err(dev, "failed to power on phy (ret=%d)\n", ret);
312 goto err_exit_phy;
313 }
314
315 ret = reset_deassert_bulk(&priv->rsts);
316 if (ret) {
317 dev_err(dev, "failed to deassert resets (ret=%d)\n", ret);
318 goto err_power_off_phy;
319 }
320
321 ret = clk_enable_bulk(&priv->clks);
322 if (ret) {
323 dev_err(dev, "failed to enable clks (ret=%d)\n", ret);
324 goto err_deassert_bulk;
325 }
326
327 /* LTSSM EN ctrl mode */
328 val = rk_pcie_readl_apb(priv, PCIE_CLIENT_HOT_RESET_CTRL);
329 val |= PCIE_LTSSM_ENABLE_ENHANCE | (PCIE_LTSSM_ENABLE_ENHANCE << 16);
330 rk_pcie_writel_apb(priv, PCIE_CLIENT_HOT_RESET_CTRL, val);
331
332 /* Set RC mode */
333 rk_pcie_writel_apb(priv, 0x0, 0xf00040);
334 pcie_dw_setup_host(&priv->dw);
335
336 ret = rk_pcie_link_up(priv, LINK_SPEED_GEN_3);
337 if (ret < 0)
338 goto err_link_up;
339
340 return 0;
341 err_link_up:
342 clk_disable_bulk(&priv->clks);
343 err_deassert_bulk:
344 reset_assert_bulk(&priv->rsts);
345 err_power_off_phy:
346 generic_phy_power_off(&priv->phy);
347 err_exit_phy:
348 generic_phy_exit(&priv->phy);
349
350 return ret;
351 }
352
rockchip_pcie_parse_dt(struct udevice * dev)353 static int rockchip_pcie_parse_dt(struct udevice *dev)
354 {
355 struct rk_pcie *priv = dev_get_priv(dev);
356 int ret;
357
358 priv->dw.dbi_base = (void *)dev_read_addr_index(dev, 0);
359 if (!priv->dw.dbi_base)
360 return -ENODEV;
361
362 dev_dbg(dev, "DBI address is 0x%p\n", priv->dw.dbi_base);
363
364 priv->apb_base = (void *)dev_read_addr_index(dev, 1);
365 if (!priv->apb_base)
366 return -ENODEV;
367
368 dev_dbg(dev, "APB address is 0x%p\n", priv->apb_base);
369
370 ret = gpio_request_by_name(dev, "reset-gpios", 0,
371 &priv->rst_gpio, GPIOD_IS_OUT);
372 if (ret) {
373 dev_err(dev, "failed to find reset-gpios property\n");
374 return ret;
375 }
376
377 ret = reset_get_bulk(dev, &priv->rsts);
378 if (ret) {
379 dev_err(dev, "Can't get reset: %d\n", ret);
380 return ret;
381 }
382
383 ret = clk_get_bulk(dev, &priv->clks);
384 if (ret) {
385 dev_err(dev, "Can't get clock: %d\n", ret);
386 return ret;
387 }
388
389 ret = device_get_supply_regulator(dev, "vpcie3v3-supply",
390 &priv->vpcie3v3);
391 if (ret && ret != -ENOENT) {
392 dev_err(dev, "failed to get vpcie3v3 supply (ret=%d)\n", ret);
393 return ret;
394 }
395
396 ret = generic_phy_get_by_index(dev, 0, &priv->phy);
397 if (ret) {
398 dev_err(dev, "failed to get pcie phy (ret=%d)\n", ret);
399 return ret;
400 }
401
402 return 0;
403 }
404
405 /**
406 * rockchip_pcie_probe() - Probe the PCIe bus for active link
407 *
408 * @dev: A pointer to the device being operated on
409 *
410 * Probe for an active link on the PCIe bus and configure the controller
411 * to enable this port.
412 *
413 * Return: 0 on success, else -ENODEV
414 */
rockchip_pcie_probe(struct udevice * dev)415 static int rockchip_pcie_probe(struct udevice *dev)
416 {
417 struct rk_pcie *priv = dev_get_priv(dev);
418 struct udevice *ctlr = pci_get_controller(dev);
419 struct pci_controller *hose = dev_get_uclass_priv(ctlr);
420 int ret = 0;
421
422 priv->dw.first_busno = dev_seq(dev);
423 priv->dw.dev = dev;
424
425 ret = rockchip_pcie_parse_dt(dev);
426 if (ret)
427 return ret;
428
429 ret = rockchip_pcie_init_port(dev);
430 if (ret)
431 return ret;
432
433 dev_info(dev, "PCIE-%d: Link up (Gen%d-x%d, Bus%d)\n",
434 dev_seq(dev), pcie_dw_get_link_speed(&priv->dw),
435 pcie_dw_get_link_width(&priv->dw),
436 hose->first_busno);
437
438
439 return pcie_dw_prog_outbound_atu_unroll(&priv->dw,
440 PCIE_ATU_REGION_INDEX0,
441 PCIE_ATU_TYPE_MEM,
442 priv->dw.mem.phys_start,
443 priv->dw.mem.bus_start,
444 priv->dw.mem.size);
445 }
446
447 static const struct dm_pci_ops rockchip_pcie_ops = {
448 .read_config = pcie_dw_read_config,
449 .write_config = pcie_dw_write_config,
450 };
451
452 static const struct udevice_id rockchip_pcie_ids[] = {
453 { .compatible = "rockchip,rk3568-pcie" },
454 { }
455 };
456
457 U_BOOT_DRIVER(rockchip_dw_pcie) = {
458 .name = "pcie_dw_rockchip",
459 .id = UCLASS_PCI,
460 .of_match = rockchip_pcie_ids,
461 .ops = &rockchip_pcie_ops,
462 .probe = rockchip_pcie_probe,
463 .priv_auto = sizeof(struct rk_pcie),
464 };
465