1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2016, Fuzhou Rockchip Electronics Co., Ltd
4 * Copyright (C) 2019, STMicroelectronics - All Rights Reserved
5 * Author(s): Philippe Cornu <philippe.cornu@st.com> for STMicroelectronics.
6 * Yannick Fertre <yannick.fertre@st.com> for STMicroelectronics.
7 *
8 * This generic Synopsys DesignWare MIPI DSI host driver is inspired from
9 * the Linux Kernel driver drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c.
10 */
11
12 #include <common.h>
13 #include <clk.h>
14 #include <dsi_host.h>
15 #include <dm.h>
16 #include <errno.h>
17 #include <panel.h>
18 #include <video.h>
19 #include <asm/io.h>
20 #include <asm/arch/gpio.h>
21 #include <dm/device-internal.h>
22 #include <dm/device_compat.h>
23 #include <linux/bitops.h>
24 #include <linux/delay.h>
25 #include <linux/iopoll.h>
26 #include <video_bridge.h>
27
28 #define HWVER_131 0x31333100 /* IP version 1.31 */
29
30 #define DSI_VERSION 0x00
31 #define VERSION GENMASK(31, 8)
32
33 #define DSI_PWR_UP 0x04
34 #define RESET 0
35 #define POWERUP BIT(0)
36
37 #define DSI_CLKMGR_CFG 0x08
38 #define TO_CLK_DIVISION(div) (((div) & 0xff) << 8)
39 #define TX_ESC_CLK_DIVISION(div) ((div) & 0xff)
40
41 #define DSI_DPI_VCID 0x0c
42 #define DPI_VCID(vcid) ((vcid) & 0x3)
43
44 #define DSI_DPI_COLOR_CODING 0x10
45 #define LOOSELY18_EN BIT(8)
46 #define DPI_COLOR_CODING_16BIT_1 0x0
47 #define DPI_COLOR_CODING_16BIT_2 0x1
48 #define DPI_COLOR_CODING_16BIT_3 0x2
49 #define DPI_COLOR_CODING_18BIT_1 0x3
50 #define DPI_COLOR_CODING_18BIT_2 0x4
51 #define DPI_COLOR_CODING_24BIT 0x5
52
53 #define DSI_DPI_CFG_POL 0x14
54 #define COLORM_ACTIVE_LOW BIT(4)
55 #define SHUTD_ACTIVE_LOW BIT(3)
56 #define HSYNC_ACTIVE_LOW BIT(2)
57 #define VSYNC_ACTIVE_LOW BIT(1)
58 #define DATAEN_ACTIVE_LOW BIT(0)
59
60 #define DSI_DPI_LP_CMD_TIM 0x18
61 #define OUTVACT_LPCMD_TIME(p) (((p) & 0xff) << 16)
62 #define INVACT_LPCMD_TIME(p) ((p) & 0xff)
63
64 #define DSI_DBI_VCID 0x1c
65 #define DSI_DBI_CFG 0x20
66 #define DSI_DBI_PARTITIONING_EN 0x24
67 #define DSI_DBI_CMDSIZE 0x28
68
69 #define DSI_PCKHDL_CFG 0x2c
70 #define CRC_RX_EN BIT(4)
71 #define ECC_RX_EN BIT(3)
72 #define BTA_EN BIT(2)
73 #define EOTP_RX_EN BIT(1)
74 #define EOTP_TX_EN BIT(0)
75
76 #define DSI_GEN_VCID 0x30
77
78 #define DSI_MODE_CFG 0x34
79 #define ENABLE_VIDEO_MODE 0
80 #define ENABLE_CMD_MODE BIT(0)
81
82 #define DSI_VID_MODE_CFG 0x38
83 #define ENABLE_LOW_POWER (0x3f << 8)
84 #define ENABLE_LOW_POWER_MASK (0x3f << 8)
85 #define VID_MODE_TYPE_NON_BURST_SYNC_PULSES 0x0
86 #define VID_MODE_TYPE_NON_BURST_SYNC_EVENTS 0x1
87 #define VID_MODE_TYPE_BURST 0x2
88 #define VID_MODE_TYPE_MASK 0x3
89
90 #define DSI_VID_PKT_SIZE 0x3c
91 #define VID_PKT_SIZE(p) ((p) & 0x3fff)
92
93 #define DSI_VID_NUM_CHUNKS 0x40
94 #define VID_NUM_CHUNKS(c) ((c) & 0x1fff)
95
96 #define DSI_VID_NULL_SIZE 0x44
97 #define VID_NULL_SIZE(b) ((b) & 0x1fff)
98
99 #define DSI_VID_HSA_TIME 0x48
100 #define DSI_VID_HBP_TIME 0x4c
101 #define DSI_VID_HLINE_TIME 0x50
102 #define DSI_VID_VSA_LINES 0x54
103 #define DSI_VID_VBP_LINES 0x58
104 #define DSI_VID_VFP_LINES 0x5c
105 #define DSI_VID_VACTIVE_LINES 0x60
106 #define DSI_EDPI_CMD_SIZE 0x64
107
108 #define DSI_CMD_MODE_CFG 0x68
109 #define MAX_RD_PKT_SIZE_LP BIT(24)
110 #define DCS_LW_TX_LP BIT(19)
111 #define DCS_SR_0P_TX_LP BIT(18)
112 #define DCS_SW_1P_TX_LP BIT(17)
113 #define DCS_SW_0P_TX_LP BIT(16)
114 #define GEN_LW_TX_LP BIT(14)
115 #define GEN_SR_2P_TX_LP BIT(13)
116 #define GEN_SR_1P_TX_LP BIT(12)
117 #define GEN_SR_0P_TX_LP BIT(11)
118 #define GEN_SW_2P_TX_LP BIT(10)
119 #define GEN_SW_1P_TX_LP BIT(9)
120 #define GEN_SW_0P_TX_LP BIT(8)
121 #define ACK_RQST_EN BIT(1)
122 #define TEAR_FX_EN BIT(0)
123
124 #define CMD_MODE_ALL_LP (MAX_RD_PKT_SIZE_LP | \
125 DCS_LW_TX_LP | \
126 DCS_SR_0P_TX_LP | \
127 DCS_SW_1P_TX_LP | \
128 DCS_SW_0P_TX_LP | \
129 GEN_LW_TX_LP | \
130 GEN_SR_2P_TX_LP | \
131 GEN_SR_1P_TX_LP | \
132 GEN_SR_0P_TX_LP | \
133 GEN_SW_2P_TX_LP | \
134 GEN_SW_1P_TX_LP | \
135 GEN_SW_0P_TX_LP)
136
137 #define DSI_GEN_HDR 0x6c
138 #define DSI_GEN_PLD_DATA 0x70
139
140 #define DSI_CMD_PKT_STATUS 0x74
141 #define GEN_RD_CMD_BUSY BIT(6)
142 #define GEN_PLD_R_FULL BIT(5)
143 #define GEN_PLD_R_EMPTY BIT(4)
144 #define GEN_PLD_W_FULL BIT(3)
145 #define GEN_PLD_W_EMPTY BIT(2)
146 #define GEN_CMD_FULL BIT(1)
147 #define GEN_CMD_EMPTY BIT(0)
148
149 #define DSI_TO_CNT_CFG 0x78
150 #define HSTX_TO_CNT(p) (((p) & 0xffff) << 16)
151 #define LPRX_TO_CNT(p) ((p) & 0xffff)
152
153 #define DSI_HS_RD_TO_CNT 0x7c
154 #define DSI_LP_RD_TO_CNT 0x80
155 #define DSI_HS_WR_TO_CNT 0x84
156 #define DSI_LP_WR_TO_CNT 0x88
157 #define DSI_BTA_TO_CNT 0x8c
158
159 #define DSI_LPCLK_CTRL 0x94
160 #define AUTO_CLKLANE_CTRL BIT(1)
161 #define PHY_TXREQUESTCLKHS BIT(0)
162
163 #define DSI_PHY_TMR_LPCLK_CFG 0x98
164 #define PHY_CLKHS2LP_TIME(lbcc) (((lbcc) & 0x3ff) << 16)
165 #define PHY_CLKLP2HS_TIME(lbcc) ((lbcc) & 0x3ff)
166
167 #define DSI_PHY_TMR_CFG 0x9c
168 #define PHY_HS2LP_TIME(lbcc) (((lbcc) & 0xff) << 24)
169 #define PHY_LP2HS_TIME(lbcc) (((lbcc) & 0xff) << 16)
170 #define MAX_RD_TIME(lbcc) ((lbcc) & 0x7fff)
171 #define PHY_HS2LP_TIME_V131(lbcc) (((lbcc) & 0x3ff) << 16)
172 #define PHY_LP2HS_TIME_V131(lbcc) ((lbcc) & 0x3ff)
173
174 #define DSI_PHY_RSTZ 0xa0
175 #define PHY_DISFORCEPLL 0
176 #define PHY_ENFORCEPLL BIT(3)
177 #define PHY_DISABLECLK 0
178 #define PHY_ENABLECLK BIT(2)
179 #define PHY_RSTZ 0
180 #define PHY_UNRSTZ BIT(1)
181 #define PHY_SHUTDOWNZ 0
182 #define PHY_UNSHUTDOWNZ BIT(0)
183
184 #define DSI_PHY_IF_CFG 0xa4
185 #define PHY_STOP_WAIT_TIME(cycle) (((cycle) & 0xff) << 8)
186 #define N_LANES(n) (((n) - 1) & 0x3)
187
188 #define DSI_PHY_ULPS_CTRL 0xa8
189 #define DSI_PHY_TX_TRIGGERS 0xac
190
191 #define DSI_PHY_STATUS 0xb0
192 #define PHY_STOP_STATE_CLK_LANE BIT(2)
193 #define PHY_LOCK BIT(0)
194
195 #define DSI_PHY_TST_CTRL0 0xb4
196 #define PHY_TESTCLK BIT(1)
197 #define PHY_UNTESTCLK 0
198 #define PHY_TESTCLR BIT(0)
199 #define PHY_UNTESTCLR 0
200
201 #define DSI_PHY_TST_CTRL1 0xb8
202 #define PHY_TESTEN BIT(16)
203 #define PHY_UNTESTEN 0
204 #define PHY_TESTDOUT(n) (((n) & 0xff) << 8)
205 #define PHY_TESTDIN(n) ((n) & 0xff)
206
207 #define DSI_INT_ST0 0xbc
208 #define DSI_INT_ST1 0xc0
209 #define DSI_INT_MSK0 0xc4
210 #define DSI_INT_MSK1 0xc8
211
212 #define DSI_PHY_TMR_RD_CFG 0xf4
213 #define MAX_RD_TIME_V131(lbcc) ((lbcc) & 0x7fff)
214
215 #define PHY_STATUS_TIMEOUT_US 10000
216 #define CMD_PKT_STATUS_TIMEOUT_US 20000
217
218 #define MSEC_PER_SEC 1000
219
220 struct dw_mipi_dsi {
221 struct mipi_dsi_host dsi_host;
222 struct mipi_dsi_device *device;
223 void __iomem *base;
224 unsigned int lane_mbps; /* per lane */
225 u32 channel;
226 unsigned int max_data_lanes;
227 const struct mipi_dsi_phy_ops *phy_ops;
228 };
229
dsi_mode_vrefresh(struct display_timing * timings)230 static int dsi_mode_vrefresh(struct display_timing *timings)
231 {
232 int refresh = 0;
233 unsigned int calc_val;
234 u32 htotal = timings->hactive.typ + timings->hfront_porch.typ +
235 timings->hback_porch.typ + timings->hsync_len.typ;
236 u32 vtotal = timings->vactive.typ + timings->vfront_porch.typ +
237 timings->vback_porch.typ + timings->vsync_len.typ;
238
239 if (htotal > 0 && vtotal > 0) {
240 calc_val = timings->pixelclock.typ;
241 calc_val /= htotal;
242 refresh = (calc_val + vtotal / 2) / vtotal;
243 }
244
245 return refresh;
246 }
247
248 /*
249 * The controller should generate 2 frames before
250 * preparing the peripheral.
251 */
dw_mipi_dsi_wait_for_two_frames(struct display_timing * timings)252 static void dw_mipi_dsi_wait_for_two_frames(struct display_timing *timings)
253 {
254 int refresh, two_frames;
255
256 refresh = dsi_mode_vrefresh(timings);
257 two_frames = DIV_ROUND_UP(MSEC_PER_SEC, refresh) * 2;
258 mdelay(two_frames);
259 }
260
host_to_dsi(struct mipi_dsi_host * host)261 static inline struct dw_mipi_dsi *host_to_dsi(struct mipi_dsi_host *host)
262 {
263 return container_of(host, struct dw_mipi_dsi, dsi_host);
264 }
265
dsi_write(struct dw_mipi_dsi * dsi,u32 reg,u32 val)266 static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val)
267 {
268 writel(val, dsi->base + reg);
269 }
270
dsi_read(struct dw_mipi_dsi * dsi,u32 reg)271 static inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg)
272 {
273 return readl(dsi->base + reg);
274 }
275
dw_mipi_dsi_host_attach(struct mipi_dsi_host * host,struct mipi_dsi_device * device)276 static int dw_mipi_dsi_host_attach(struct mipi_dsi_host *host,
277 struct mipi_dsi_device *device)
278 {
279 struct dw_mipi_dsi *dsi = host_to_dsi(host);
280
281 if (device->lanes > dsi->max_data_lanes) {
282 dev_err(device->dev,
283 "the number of data lanes(%u) is too many\n",
284 device->lanes);
285 return -EINVAL;
286 }
287
288 dsi->channel = device->channel;
289
290 return 0;
291 }
292
dw_mipi_message_config(struct dw_mipi_dsi * dsi,const struct mipi_dsi_msg * msg)293 static void dw_mipi_message_config(struct dw_mipi_dsi *dsi,
294 const struct mipi_dsi_msg *msg)
295 {
296 bool lpm = msg->flags & MIPI_DSI_MSG_USE_LPM;
297 u32 val = 0;
298
299 if (msg->flags & MIPI_DSI_MSG_REQ_ACK)
300 val |= ACK_RQST_EN;
301 if (lpm)
302 val |= CMD_MODE_ALL_LP;
303
304 dsi_write(dsi, DSI_LPCLK_CTRL, lpm ? 0 : PHY_TXREQUESTCLKHS);
305 dsi_write(dsi, DSI_CMD_MODE_CFG, val);
306 }
307
dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi * dsi,u32 hdr_val)308 static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 hdr_val)
309 {
310 int ret;
311 u32 val, mask;
312
313 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
314 val, !(val & GEN_CMD_FULL),
315 CMD_PKT_STATUS_TIMEOUT_US);
316 if (ret) {
317 dev_err(dsi->dsi_host.dev,
318 "failed to get available command FIFO\n");
319 return ret;
320 }
321
322 dsi_write(dsi, DSI_GEN_HDR, hdr_val);
323
324 mask = GEN_CMD_EMPTY | GEN_PLD_W_EMPTY;
325 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
326 val, (val & mask) == mask,
327 CMD_PKT_STATUS_TIMEOUT_US);
328 if (ret) {
329 dev_err(dsi->dsi_host.dev, "failed to write command FIFO\n");
330 return ret;
331 }
332
333 return 0;
334 }
335
dw_mipi_dsi_write(struct dw_mipi_dsi * dsi,const struct mipi_dsi_packet * packet)336 static int dw_mipi_dsi_write(struct dw_mipi_dsi *dsi,
337 const struct mipi_dsi_packet *packet)
338 {
339 const u8 *tx_buf = packet->payload;
340 int len = packet->payload_length, pld_data_bytes = sizeof(u32), ret;
341 __le32 word;
342 u32 val;
343
344 while (len) {
345 if (len < pld_data_bytes) {
346 word = 0;
347 memcpy(&word, tx_buf, len);
348 dsi_write(dsi, DSI_GEN_PLD_DATA, le32_to_cpu(word));
349 len = 0;
350 } else {
351 memcpy(&word, tx_buf, pld_data_bytes);
352 dsi_write(dsi, DSI_GEN_PLD_DATA, le32_to_cpu(word));
353 tx_buf += pld_data_bytes;
354 len -= pld_data_bytes;
355 }
356
357 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
358 val, !(val & GEN_PLD_W_FULL),
359 CMD_PKT_STATUS_TIMEOUT_US);
360 if (ret) {
361 dev_err(dsi->dsi_host.dev,
362 "failed to get available write payload FIFO\n");
363 return ret;
364 }
365 }
366
367 word = 0;
368 memcpy(&word, packet->header, sizeof(packet->header));
369 return dw_mipi_dsi_gen_pkt_hdr_write(dsi, le32_to_cpu(word));
370 }
371
dw_mipi_dsi_read(struct dw_mipi_dsi * dsi,const struct mipi_dsi_msg * msg)372 static int dw_mipi_dsi_read(struct dw_mipi_dsi *dsi,
373 const struct mipi_dsi_msg *msg)
374 {
375 int i, j, ret, len = msg->rx_len;
376 u8 *buf = msg->rx_buf;
377 u32 val;
378
379 /* Wait end of the read operation */
380 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
381 val, !(val & GEN_RD_CMD_BUSY),
382 CMD_PKT_STATUS_TIMEOUT_US);
383 if (ret) {
384 dev_err(dsi->dsi_host.dev, "Timeout during read operation\n");
385 return ret;
386 }
387
388 for (i = 0; i < len; i += 4) {
389 /* Read fifo must not be empty before all bytes are read */
390 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
391 val, !(val & GEN_PLD_R_EMPTY),
392 CMD_PKT_STATUS_TIMEOUT_US);
393 if (ret) {
394 dev_err(dsi->dsi_host.dev,
395 "Read payload FIFO is empty\n");
396 return ret;
397 }
398
399 val = dsi_read(dsi, DSI_GEN_PLD_DATA);
400 for (j = 0; j < 4 && j + i < len; j++)
401 buf[i + j] = val >> (8 * j);
402 }
403
404 return ret;
405 }
406
dw_mipi_dsi_host_transfer(struct mipi_dsi_host * host,const struct mipi_dsi_msg * msg)407 static ssize_t dw_mipi_dsi_host_transfer(struct mipi_dsi_host *host,
408 const struct mipi_dsi_msg *msg)
409 {
410 struct dw_mipi_dsi *dsi = host_to_dsi(host);
411 struct mipi_dsi_packet packet;
412 int ret, nb_bytes;
413
414 ret = mipi_dsi_create_packet(&packet, msg);
415 if (ret) {
416 dev_err(host->dev, "failed to create packet: %d\n", ret);
417 return ret;
418 }
419
420 dw_mipi_message_config(dsi, msg);
421
422 ret = dw_mipi_dsi_write(dsi, &packet);
423 if (ret)
424 return ret;
425
426 if (msg->rx_buf && msg->rx_len) {
427 ret = dw_mipi_dsi_read(dsi, msg);
428 if (ret)
429 return ret;
430 nb_bytes = msg->rx_len;
431 } else {
432 nb_bytes = packet.size;
433 }
434
435 return nb_bytes;
436 }
437
438 static const struct mipi_dsi_host_ops dw_mipi_dsi_host_ops = {
439 .attach = dw_mipi_dsi_host_attach,
440 .transfer = dw_mipi_dsi_host_transfer,
441 };
442
dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi * dsi)443 static void dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi *dsi)
444 {
445 struct mipi_dsi_device *device = dsi->device;
446 u32 val;
447
448 /*
449 * TODO dw drv improvements
450 * enabling low power is panel-dependent, we should use the
451 * panel configuration here...
452 */
453 val = ENABLE_LOW_POWER;
454
455 if (device->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
456 val |= VID_MODE_TYPE_BURST;
457 else if (device->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
458 val |= VID_MODE_TYPE_NON_BURST_SYNC_PULSES;
459 else
460 val |= VID_MODE_TYPE_NON_BURST_SYNC_EVENTS;
461
462 dsi_write(dsi, DSI_VID_MODE_CFG, val);
463 }
464
dw_mipi_dsi_set_mode(struct dw_mipi_dsi * dsi,unsigned long mode_flags)465 static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi,
466 unsigned long mode_flags)
467 {
468 const struct mipi_dsi_phy_ops *phy_ops = dsi->phy_ops;
469
470 dsi_write(dsi, DSI_PWR_UP, RESET);
471
472 if (mode_flags & MIPI_DSI_MODE_VIDEO) {
473 dsi_write(dsi, DSI_MODE_CFG, ENABLE_VIDEO_MODE);
474 dw_mipi_dsi_video_mode_config(dsi);
475 dsi_write(dsi, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS);
476 } else {
477 dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
478 }
479
480 if (phy_ops->post_set_mode)
481 phy_ops->post_set_mode(dsi->device, mode_flags);
482
483 dsi_write(dsi, DSI_PWR_UP, POWERUP);
484 }
485
dw_mipi_dsi_init_pll(struct dw_mipi_dsi * dsi)486 static void dw_mipi_dsi_init_pll(struct dw_mipi_dsi *dsi)
487 {
488 const struct mipi_dsi_phy_ops *phy_ops = dsi->phy_ops;
489 unsigned int esc_rate;
490 u32 esc_clk_division;
491
492 /*
493 * The maximum permitted escape clock is 20MHz and it is derived from
494 * lanebyteclk, which is running at "lane_mbps / 8".
495 */
496 if (phy_ops->get_esc_clk_rate)
497 phy_ops->get_esc_clk_rate(dsi->device, &esc_rate);
498 else
499 esc_rate = 20; /* Default to 20MHz */
500
501 /*
502 * We want:
503 *
504 * (lane_mbps >> 3) / esc_clk_division < X
505 * which is:
506 * (lane_mbps >> 3) / X > esc_clk_division
507 */
508 esc_clk_division = (dsi->lane_mbps >> 3) / esc_rate + 1;
509
510 dsi_write(dsi, DSI_PWR_UP, RESET);
511
512 /*
513 * TODO dw drv improvements
514 * timeout clock division should be computed with the
515 * high speed transmission counter timeout and byte lane...
516 */
517 dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVISION(10) |
518 TX_ESC_CLK_DIVISION(esc_clk_division));
519 }
520
dw_mipi_dsi_dpi_config(struct dw_mipi_dsi * dsi,struct display_timing * timings)521 static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi,
522 struct display_timing *timings)
523 {
524 struct mipi_dsi_device *device = dsi->device;
525 u32 val = 0, color = 0;
526
527 switch (device->format) {
528 case MIPI_DSI_FMT_RGB888:
529 color = DPI_COLOR_CODING_24BIT;
530 break;
531 case MIPI_DSI_FMT_RGB666:
532 color = DPI_COLOR_CODING_18BIT_2 | LOOSELY18_EN;
533 break;
534 case MIPI_DSI_FMT_RGB666_PACKED:
535 color = DPI_COLOR_CODING_18BIT_1;
536 break;
537 case MIPI_DSI_FMT_RGB565:
538 color = DPI_COLOR_CODING_16BIT_1;
539 break;
540 }
541
542 if (device->mode_flags & DISPLAY_FLAGS_VSYNC_HIGH)
543 val |= VSYNC_ACTIVE_LOW;
544 if (device->mode_flags & DISPLAY_FLAGS_HSYNC_HIGH)
545 val |= HSYNC_ACTIVE_LOW;
546
547 dsi_write(dsi, DSI_DPI_VCID, DPI_VCID(dsi->channel));
548 dsi_write(dsi, DSI_DPI_COLOR_CODING, color);
549 dsi_write(dsi, DSI_DPI_CFG_POL, val);
550 /*
551 * TODO dw drv improvements
552 * largest packet sizes during hfp or during vsa/vpb/vfp
553 * should be computed according to byte lane, lane number and only
554 * if sending lp cmds in high speed is enable (PHY_TXREQUESTCLKHS)
555 */
556 dsi_write(dsi, DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(4)
557 | INVACT_LPCMD_TIME(4));
558 }
559
dw_mipi_dsi_packet_handler_config(struct dw_mipi_dsi * dsi)560 static void dw_mipi_dsi_packet_handler_config(struct dw_mipi_dsi *dsi)
561 {
562 dsi_write(dsi, DSI_PCKHDL_CFG, CRC_RX_EN | ECC_RX_EN | BTA_EN);
563 }
564
dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi * dsi,struct display_timing * timings)565 static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi,
566 struct display_timing *timings)
567 {
568 /*
569 * TODO dw drv improvements
570 * only burst mode is supported here. For non-burst video modes,
571 * we should compute DSI_VID_PKT_SIZE, DSI_VCCR.NUMC &
572 * DSI_VNPCR.NPSIZE... especially because this driver supports
573 * non-burst video modes, see dw_mipi_dsi_video_mode_config()...
574 */
575 dsi_write(dsi, DSI_VID_PKT_SIZE, VID_PKT_SIZE(timings->hactive.typ));
576 }
577
dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi * dsi)578 static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi)
579 {
580 const struct mipi_dsi_phy_ops *phy_ops = dsi->phy_ops;
581
582 /*
583 * TODO dw drv improvements
584 * compute high speed transmission counter timeout according
585 * to the timeout clock division (TO_CLK_DIVISION) and byte lane...
586 */
587 dsi_write(dsi, DSI_TO_CNT_CFG, HSTX_TO_CNT(1000) | LPRX_TO_CNT(1000));
588 /*
589 * TODO dw drv improvements
590 * the Bus-Turn-Around Timeout Counter should be computed
591 * according to byte lane...
592 */
593 dsi_write(dsi, DSI_BTA_TO_CNT, 0xd00);
594 dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
595
596 if (phy_ops->post_set_mode)
597 phy_ops->post_set_mode(dsi->device, 0);
598 }
599
600 /* Get lane byte clock cycles. */
dw_mipi_dsi_get_hcomponent_lbcc(struct dw_mipi_dsi * dsi,struct display_timing * timings,u32 hcomponent)601 static u32 dw_mipi_dsi_get_hcomponent_lbcc(struct dw_mipi_dsi *dsi,
602 struct display_timing *timings,
603 u32 hcomponent)
604 {
605 u32 frac, lbcc;
606
607 lbcc = hcomponent * dsi->lane_mbps * MSEC_PER_SEC / 8;
608
609 frac = lbcc % (timings->pixelclock.typ / 1000);
610 lbcc = lbcc / (timings->pixelclock.typ / 1000);
611 if (frac)
612 lbcc++;
613
614 return lbcc;
615 }
616
dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi * dsi,struct display_timing * timings)617 static void dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi *dsi,
618 struct display_timing *timings)
619 {
620 u32 htotal, hsa, hbp, lbcc;
621
622 htotal = timings->hactive.typ + timings->hfront_porch.typ +
623 timings->hback_porch.typ + timings->hsync_len.typ;
624
625 hsa = timings->hback_porch.typ;
626 hbp = timings->hsync_len.typ;
627
628 /*
629 * TODO dw drv improvements
630 * computations below may be improved...
631 */
632 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, timings, htotal);
633 dsi_write(dsi, DSI_VID_HLINE_TIME, lbcc);
634
635 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, timings, hsa);
636 dsi_write(dsi, DSI_VID_HSA_TIME, lbcc);
637
638 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, timings, hbp);
639 dsi_write(dsi, DSI_VID_HBP_TIME, lbcc);
640 }
641
dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi * dsi,struct display_timing * timings)642 static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi,
643 struct display_timing *timings)
644 {
645 u32 vactive, vsa, vfp, vbp;
646
647 vactive = timings->vactive.typ;
648 vsa = timings->vback_porch.typ;
649 vfp = timings->vfront_porch.typ;
650 vbp = timings->vsync_len.typ;
651
652 dsi_write(dsi, DSI_VID_VACTIVE_LINES, vactive);
653 dsi_write(dsi, DSI_VID_VSA_LINES, vsa);
654 dsi_write(dsi, DSI_VID_VFP_LINES, vfp);
655 dsi_write(dsi, DSI_VID_VBP_LINES, vbp);
656 }
657
dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi * dsi)658 static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi)
659 {
660 const struct mipi_dsi_phy_ops *phy_ops = dsi->phy_ops;
661 struct mipi_dsi_phy_timing timing = {0x40, 0x40, 0x40, 0x40};
662 u32 hw_version;
663
664 if (phy_ops->get_timing)
665 phy_ops->get_timing(dsi->device, dsi->lane_mbps, &timing);
666
667 /*
668 * TODO dw drv improvements
669 * data & clock lane timers should be computed according to panel
670 * blankings and to the automatic clock lane control mode...
671 * note: DSI_PHY_TMR_CFG.MAX_RD_TIME should be in line with
672 * DSI_CMD_MODE_CFG.MAX_RD_PKT_SIZE_LP (see CMD_MODE_ALL_LP)
673 */
674
675 hw_version = dsi_read(dsi, DSI_VERSION) & VERSION;
676
677 if (hw_version >= HWVER_131) {
678 dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME_V131(timing.data_hs2lp) |
679 PHY_LP2HS_TIME_V131(timing.data_lp2hs));
680 dsi_write(dsi, DSI_PHY_TMR_RD_CFG, MAX_RD_TIME_V131(10000));
681 } else {
682 dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME(timing.data_hs2lp) |
683 PHY_LP2HS_TIME(timing.data_lp2hs) | MAX_RD_TIME(10000));
684 }
685
686 dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG, PHY_CLKHS2LP_TIME(timing.clk_hs2lp)
687 | PHY_CLKLP2HS_TIME(timing.clk_lp2hs));
688 }
689
dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi * dsi)690 static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi)
691 {
692 struct mipi_dsi_device *device = dsi->device;
693
694 /*
695 * TODO dw drv improvements
696 * stop wait time should be the maximum between host dsi
697 * and panel stop wait times
698 */
699 dsi_write(dsi, DSI_PHY_IF_CFG, PHY_STOP_WAIT_TIME(0x20) |
700 N_LANES(device->lanes));
701 }
702
dw_mipi_dsi_dphy_init(struct dw_mipi_dsi * dsi)703 static void dw_mipi_dsi_dphy_init(struct dw_mipi_dsi *dsi)
704 {
705 /* Clear PHY state */
706 dsi_write(dsi, DSI_PHY_RSTZ, PHY_DISFORCEPLL | PHY_DISABLECLK
707 | PHY_RSTZ | PHY_SHUTDOWNZ);
708 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
709 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLR);
710 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
711 }
712
dw_mipi_dsi_dphy_enable(struct dw_mipi_dsi * dsi)713 static void dw_mipi_dsi_dphy_enable(struct dw_mipi_dsi *dsi)
714 {
715 u32 val;
716 int ret;
717
718 dsi_write(dsi, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK |
719 PHY_UNRSTZ | PHY_UNSHUTDOWNZ);
720
721 ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS, val,
722 val & PHY_LOCK, PHY_STATUS_TIMEOUT_US);
723 if (ret)
724 dev_dbg(dsi->dsi_host.dev,
725 "failed to wait phy lock state\n");
726
727 ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS,
728 val, val & PHY_STOP_STATE_CLK_LANE,
729 PHY_STATUS_TIMEOUT_US);
730 if (ret)
731 dev_dbg(dsi->dsi_host.dev,
732 "failed to wait phy clk lane stop state\n");
733 }
734
dw_mipi_dsi_clear_err(struct dw_mipi_dsi * dsi)735 static void dw_mipi_dsi_clear_err(struct dw_mipi_dsi *dsi)
736 {
737 dsi_read(dsi, DSI_INT_ST0);
738 dsi_read(dsi, DSI_INT_ST1);
739 dsi_write(dsi, DSI_INT_MSK0, 0);
740 dsi_write(dsi, DSI_INT_MSK1, 0);
741 }
742
dw_mipi_dsi_bridge_set(struct dw_mipi_dsi * dsi,struct display_timing * timings)743 static void dw_mipi_dsi_bridge_set(struct dw_mipi_dsi *dsi,
744 struct display_timing *timings)
745 {
746 const struct mipi_dsi_phy_ops *phy_ops = dsi->phy_ops;
747 struct mipi_dsi_device *device = dsi->device;
748 int ret;
749
750 ret = phy_ops->get_lane_mbps(dsi->device, timings, device->lanes,
751 device->format, &dsi->lane_mbps);
752 if (ret)
753 dev_warn(dsi->dsi_host.dev, "Phy get_lane_mbps() failed\n");
754
755 dw_mipi_dsi_init_pll(dsi);
756 dw_mipi_dsi_dpi_config(dsi, timings);
757 dw_mipi_dsi_packet_handler_config(dsi);
758 dw_mipi_dsi_video_mode_config(dsi);
759 dw_mipi_dsi_video_packet_config(dsi, timings);
760 dw_mipi_dsi_command_mode_config(dsi);
761 dw_mipi_dsi_line_timer_config(dsi, timings);
762 dw_mipi_dsi_vertical_timing_config(dsi, timings);
763
764 dw_mipi_dsi_dphy_init(dsi);
765 dw_mipi_dsi_dphy_timing_config(dsi);
766 dw_mipi_dsi_dphy_interface_config(dsi);
767
768 dw_mipi_dsi_clear_err(dsi);
769
770 ret = phy_ops->init(dsi->device);
771 if (ret)
772 dev_warn(dsi->dsi_host.dev, "Phy init() failed\n");
773
774 dw_mipi_dsi_dphy_enable(dsi);
775
776 dw_mipi_dsi_wait_for_two_frames(timings);
777
778 /* Switch to cmd mode for panel-bridge pre_enable & panel prepare */
779 dw_mipi_dsi_set_mode(dsi, 0);
780 }
781
dw_mipi_dsi_init(struct udevice * dev,struct mipi_dsi_device * device,struct display_timing * timings,unsigned int max_data_lanes,const struct mipi_dsi_phy_ops * phy_ops)782 static int dw_mipi_dsi_init(struct udevice *dev,
783 struct mipi_dsi_device *device,
784 struct display_timing *timings,
785 unsigned int max_data_lanes,
786 const struct mipi_dsi_phy_ops *phy_ops)
787 {
788 struct dw_mipi_dsi *dsi = dev_get_priv(dev);
789 struct clk clk;
790 int ret;
791
792 if (!phy_ops->init || !phy_ops->get_lane_mbps) {
793 dev_err(device->dev, "Phy not properly configured\n");
794 return -ENODEV;
795 }
796
797 dsi->phy_ops = phy_ops;
798 dsi->max_data_lanes = max_data_lanes;
799 dsi->device = device;
800 dsi->dsi_host.dev = (struct device *)dev;
801 dsi->dsi_host.ops = &dw_mipi_dsi_host_ops;
802 device->host = &dsi->dsi_host;
803
804 dsi->base = (void *)dev_read_addr(device->dev);
805 if ((fdt_addr_t)dsi->base == FDT_ADDR_T_NONE) {
806 dev_err(device->dev, "dsi dt register address error\n");
807 return -EINVAL;
808 }
809
810 ret = clk_get_by_name(device->dev, "px_clk", &clk);
811 if (ret) {
812 dev_err(device->dev, "peripheral clock get error %d\n", ret);
813 return ret;
814 }
815
816 /* get the pixel clock set by the clock framework */
817 timings->pixelclock.typ = clk_get_rate(&clk);
818
819 dw_mipi_dsi_bridge_set(dsi, timings);
820
821 return 0;
822 }
823
dw_mipi_dsi_enable(struct udevice * dev)824 static int dw_mipi_dsi_enable(struct udevice *dev)
825 {
826 struct dw_mipi_dsi *dsi = dev_get_priv(dev);
827
828 /* Switch to video mode for panel-bridge enable & panel enable */
829 dw_mipi_dsi_set_mode(dsi, MIPI_DSI_MODE_VIDEO);
830
831 return 0;
832 }
833
834 struct dsi_host_ops dw_mipi_dsi_ops = {
835 .init = dw_mipi_dsi_init,
836 .enable = dw_mipi_dsi_enable,
837 };
838
dw_mipi_dsi_probe(struct udevice * dev)839 static int dw_mipi_dsi_probe(struct udevice *dev)
840 {
841 return 0;
842 }
843
844 U_BOOT_DRIVER(dw_mipi_dsi) = {
845 .name = "dw_mipi_dsi",
846 .id = UCLASS_DSI_HOST,
847 .probe = dw_mipi_dsi_probe,
848 .ops = &dw_mipi_dsi_ops,
849 .priv_auto = sizeof(struct dw_mipi_dsi),
850 };
851
852 MODULE_AUTHOR("Chris Zhong <zyw@rock-chips.com>");
853 MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>");
854 MODULE_AUTHOR("Yannick Fertré <yannick.fertre@st.com>");
855 MODULE_DESCRIPTION("DW MIPI DSI host controller driver");
856 MODULE_LICENSE("GPL");
857 MODULE_ALIAS("platform:dw-mipi-dsi");
858