1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright (C) 2016 Intel Corp.
4 * (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.)
5 */
6
7/*
8 * NOTE: The layout of the GNVS structure below must match the layout in
9 * soc/intel/apollolake/include/soc/nvs.h !!!
10 *
11 */
12
13External (NVSA)
14
15OperationRegion (GNVS, SystemMemory, NVSA, ACPI_GNVS_SIZE)
16Field (GNVS, ByteAcc, NoLock, Preserve)
17{
18	/* Miscellaneous */
19	Offset (0x00),
20	PCNT,	8,      // 0x00 - Processor Count
21	PPCM,	8,      // 0x01 - Max PPC State
22	LIDS,	8,      // 0x02 - LID State
23	PWRS,	8,      // 0x03 - AC Power State
24	DPTE,	8,      // 0x04 - Enable DPTF
25	CBMC,	32,     // 0x05 - 0x08 - coreboot Memory Console
26	PM1I,	64,     // 0x09 - 0x10 - System Wake Source - PM1 Index
27	GPEI,	64,     // 0x11 - 0x18 - GPE Wake Source
28	NHLA,	64,     // 0x19 - 0x20 - NHLT Address
29	NHLL,	32,     // 0x21 - 0x24 - NHLT Length
30	PRT0,	32,     // 0x25 - 0x28 - PERST_0 Address
31	SCDP,	8,      // 0x29 - SD_CD GPIO portid
32	SCDO,	8,      // 0x2A - GPIO pad offset relative to the community
33	UIOR,	8,      // 0x2B - UART debug controller init on S3 resume
34	EPCS,   8,      // 0x2C - SGX Enabled status
35	EMNA,   64,     // 0x2D - 0x34 EPC base address
36	ELNG,   64,     // 0x35 - 0x3C EPC Length
37
38	/* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */
39	Offset (0x100),
40	#include <asm/acpi/cros_gnvs.asl>
41}
42