1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
4 * Copyright 2019-2021 NXP
5 * Andy Fleming
6 *
7 * Based vaguely on the pxa mmc code:
8 * (C) Copyright 2003
9 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
10 */
11
12 #include <config.h>
13 #include <common.h>
14 #include <command.h>
15 #include <cpu_func.h>
16 #include <errno.h>
17 #include <hwconfig.h>
18 #include <mmc.h>
19 #include <part.h>
20 #include <malloc.h>
21 #include <fsl_esdhc.h>
22 #include <fdt_support.h>
23 #include <asm/cache.h>
24 #include <asm/global_data.h>
25 #include <asm/io.h>
26 #include <dm.h>
27 #include <dm/device_compat.h>
28 #include <linux/bitops.h>
29 #include <linux/delay.h>
30 #include <linux/dma-mapping.h>
31 #include <sdhci.h>
32
33 DECLARE_GLOBAL_DATA_PTR;
34
35 struct fsl_esdhc {
36 uint dsaddr; /* SDMA system address register */
37 uint blkattr; /* Block attributes register */
38 uint cmdarg; /* Command argument register */
39 uint xfertyp; /* Transfer type register */
40 uint cmdrsp0; /* Command response 0 register */
41 uint cmdrsp1; /* Command response 1 register */
42 uint cmdrsp2; /* Command response 2 register */
43 uint cmdrsp3; /* Command response 3 register */
44 uint datport; /* Buffer data port register */
45 uint prsstat; /* Present state register */
46 uint proctl; /* Protocol control register */
47 uint sysctl; /* System Control Register */
48 uint irqstat; /* Interrupt status register */
49 uint irqstaten; /* Interrupt status enable register */
50 uint irqsigen; /* Interrupt signal enable register */
51 uint autoc12err; /* Auto CMD error status register */
52 uint hostcapblt; /* Host controller capabilities register */
53 uint wml; /* Watermark level register */
54 char reserved1[8]; /* reserved */
55 uint fevt; /* Force event register */
56 uint admaes; /* ADMA error status register */
57 uint adsaddrl; /* ADMA system address low register */
58 uint adsaddrh; /* ADMA system address high register */
59 char reserved2[156];
60 uint hostver; /* Host controller version register */
61 char reserved3[4]; /* reserved */
62 uint dmaerraddr; /* DMA error address register */
63 char reserved4[4]; /* reserved */
64 uint dmaerrattr; /* DMA error attribute register */
65 char reserved5[4]; /* reserved */
66 uint hostcapblt2; /* Host controller capabilities register 2 */
67 char reserved6[8]; /* reserved */
68 uint tbctl; /* Tuning block control register */
69 char reserved7[32]; /* reserved */
70 uint sdclkctl; /* SD clock control register */
71 uint sdtimingctl; /* SD timing control register */
72 char reserved8[20]; /* reserved */
73 uint dllcfg0; /* DLL config 0 register */
74 uint dllcfg1; /* DLL config 1 register */
75 char reserved9[8]; /* reserved */
76 uint dllstat0; /* DLL status 0 register */
77 char reserved10[664];/* reserved */
78 uint esdhcctl; /* eSDHC control register */
79 };
80
81 struct fsl_esdhc_plat {
82 struct mmc_config cfg;
83 struct mmc mmc;
84 };
85
86 /**
87 * struct fsl_esdhc_priv
88 *
89 * @esdhc_regs: registers of the sdhc controller
90 * @sdhc_clk: Current clk of the sdhc controller
91 * @bus_width: bus width, 1bit, 4bit or 8bit
92 * @cfg: mmc config
93 * @mmc: mmc
94 * Following is used when Driver Model is enabled for MMC
95 * @dev: pointer for the device
96 * @cd_gpio: gpio for card detection
97 * @wp_gpio: gpio for write protection
98 */
99 struct fsl_esdhc_priv {
100 struct fsl_esdhc *esdhc_regs;
101 unsigned int sdhc_clk;
102 bool is_sdhc_per_clk;
103 unsigned int clock;
104 #if !CONFIG_IS_ENABLED(DM_MMC)
105 struct mmc *mmc;
106 #endif
107 struct udevice *dev;
108 struct sdhci_adma_desc *adma_desc_table;
109 dma_addr_t dma_addr;
110 };
111
112 /* Return the XFERTYP flags for a given command and data packet */
esdhc_xfertyp(struct mmc_cmd * cmd,struct mmc_data * data)113 static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
114 {
115 uint xfertyp = 0;
116
117 if (data) {
118 xfertyp |= XFERTYP_DPSEL;
119 if (!IS_ENABLED(CONFIG_SYS_FSL_ESDHC_USE_PIO) &&
120 cmd->cmdidx != MMC_CMD_SEND_TUNING_BLOCK &&
121 cmd->cmdidx != MMC_CMD_SEND_TUNING_BLOCK_HS200)
122 xfertyp |= XFERTYP_DMAEN;
123 if (data->blocks > 1) {
124 xfertyp |= XFERTYP_MSBSEL;
125 xfertyp |= XFERTYP_BCEN;
126 if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_ESDHC111))
127 xfertyp |= XFERTYP_AC12EN;
128 }
129
130 if (data->flags & MMC_DATA_READ)
131 xfertyp |= XFERTYP_DTDSEL;
132 }
133
134 if (cmd->resp_type & MMC_RSP_CRC)
135 xfertyp |= XFERTYP_CCCEN;
136 if (cmd->resp_type & MMC_RSP_OPCODE)
137 xfertyp |= XFERTYP_CICEN;
138 if (cmd->resp_type & MMC_RSP_136)
139 xfertyp |= XFERTYP_RSPTYP_136;
140 else if (cmd->resp_type & MMC_RSP_BUSY)
141 xfertyp |= XFERTYP_RSPTYP_48_BUSY;
142 else if (cmd->resp_type & MMC_RSP_PRESENT)
143 xfertyp |= XFERTYP_RSPTYP_48;
144
145 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
146 xfertyp |= XFERTYP_CMDTYP_ABORT;
147
148 return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
149 }
150
151 /*
152 * PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
153 */
esdhc_pio_read_write(struct fsl_esdhc_priv * priv,struct mmc_data * data)154 static void esdhc_pio_read_write(struct fsl_esdhc_priv *priv,
155 struct mmc_data *data)
156 {
157 struct fsl_esdhc *regs = priv->esdhc_regs;
158 uint blocks;
159 char *buffer;
160 uint databuf;
161 uint size;
162 uint irqstat;
163 ulong start;
164
165 if (data->flags & MMC_DATA_READ) {
166 blocks = data->blocks;
167 buffer = data->dest;
168 while (blocks) {
169 start = get_timer(0);
170 size = data->blocksize;
171 irqstat = esdhc_read32(®s->irqstat);
172 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BREN)) {
173 if (get_timer(start) > PIO_TIMEOUT) {
174 printf("\nData Read Failed in PIO Mode.");
175 return;
176 }
177 }
178 while (size && (!(irqstat & IRQSTAT_TC))) {
179 udelay(100); /* Wait before last byte transfer complete */
180 irqstat = esdhc_read32(®s->irqstat);
181 databuf = in_le32(®s->datport);
182 *((uint *)buffer) = databuf;
183 buffer += 4;
184 size -= 4;
185 }
186 blocks--;
187 }
188 } else {
189 blocks = data->blocks;
190 buffer = (char *)data->src;
191 while (blocks) {
192 start = get_timer(0);
193 size = data->blocksize;
194 irqstat = esdhc_read32(®s->irqstat);
195 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BWEN)) {
196 if (get_timer(start) > PIO_TIMEOUT) {
197 printf("\nData Write Failed in PIO Mode.");
198 return;
199 }
200 }
201 while (size && (!(irqstat & IRQSTAT_TC))) {
202 udelay(100); /* Wait before last byte transfer complete */
203 databuf = *((uint *)buffer);
204 buffer += 4;
205 size -= 4;
206 irqstat = esdhc_read32(®s->irqstat);
207 out_le32(®s->datport, databuf);
208 }
209 blocks--;
210 }
211 }
212 }
213
esdhc_setup_watermark_level(struct fsl_esdhc_priv * priv,struct mmc_data * data)214 static void esdhc_setup_watermark_level(struct fsl_esdhc_priv *priv,
215 struct mmc_data *data)
216 {
217 struct fsl_esdhc *regs = priv->esdhc_regs;
218 uint wml_value = data->blocksize / 4;
219
220 if (data->flags & MMC_DATA_READ) {
221 if (wml_value > WML_RD_WML_MAX)
222 wml_value = WML_RD_WML_MAX_VAL;
223
224 esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value);
225 } else {
226 if (wml_value > WML_WR_WML_MAX)
227 wml_value = WML_WR_WML_MAX_VAL;
228
229 esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK,
230 wml_value << 16);
231 }
232 }
233
esdhc_setup_dma(struct fsl_esdhc_priv * priv,struct mmc_data * data)234 static void esdhc_setup_dma(struct fsl_esdhc_priv *priv, struct mmc_data *data)
235 {
236 uint trans_bytes = data->blocksize * data->blocks;
237 struct fsl_esdhc *regs = priv->esdhc_regs;
238 phys_addr_t adma_addr;
239 void *buf;
240
241 if (data->flags & MMC_DATA_WRITE)
242 buf = (void *)data->src;
243 else
244 buf = data->dest;
245
246 priv->dma_addr = dma_map_single(buf, trans_bytes,
247 mmc_get_dma_dir(data));
248
249 if (IS_ENABLED(CONFIG_FSL_ESDHC_SUPPORT_ADMA2) &&
250 priv->adma_desc_table) {
251 debug("Using ADMA2\n");
252 /* prefer ADMA2 if it is available */
253 sdhci_prepare_adma_table(priv->adma_desc_table, data,
254 priv->dma_addr);
255
256 adma_addr = virt_to_phys(priv->adma_desc_table);
257 esdhc_write32(®s->adsaddrl, lower_32_bits(adma_addr));
258 if (IS_ENABLED(CONFIG_DMA_ADDR_T_64BIT))
259 esdhc_write32(®s->adsaddrh, upper_32_bits(adma_addr));
260 esdhc_clrsetbits32(®s->proctl, PROCTL_DMAS_MASK,
261 PROCTL_DMAS_ADMA2);
262 } else {
263 debug("Using SDMA\n");
264 if (upper_32_bits(priv->dma_addr))
265 printf("Cannot use 64 bit addresses with SDMA\n");
266 esdhc_write32(®s->dsaddr, lower_32_bits(priv->dma_addr));
267 esdhc_clrsetbits32(®s->proctl, PROCTL_DMAS_MASK,
268 PROCTL_DMAS_SDMA);
269 }
270
271 esdhc_write32(®s->blkattr, data->blocks << 16 | data->blocksize);
272 }
273
esdhc_setup_data(struct fsl_esdhc_priv * priv,struct mmc * mmc,struct mmc_data * data)274 static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,
275 struct mmc_data *data)
276 {
277 int timeout;
278 bool is_write = data->flags & MMC_DATA_WRITE;
279 struct fsl_esdhc *regs = priv->esdhc_regs;
280
281 if (is_write && !(esdhc_read32(®s->prsstat) & PRSSTAT_WPSPL)) {
282 printf("Can not write to locked SD card.\n");
283 return -EINVAL;
284 }
285
286 if (IS_ENABLED(CONFIG_SYS_FSL_ESDHC_USE_PIO))
287 esdhc_setup_watermark_level(priv, data);
288 else
289 esdhc_setup_dma(priv, data);
290
291 /* Calculate the timeout period for data transactions */
292 /*
293 * 1)Timeout period = (2^(timeout+13)) SD Clock cycles
294 * 2)Timeout period should be minimum 0.250sec as per SD Card spec
295 * So, Number of SD Clock cycles for 0.25sec should be minimum
296 * (SD Clock/sec * 0.25 sec) SD Clock cycles
297 * = (mmc->clock * 1/4) SD Clock cycles
298 * As 1) >= 2)
299 * => (2^(timeout+13)) >= mmc->clock * 1/4
300 * Taking log2 both the sides
301 * => timeout + 13 >= log2(mmc->clock/4)
302 * Rounding up to next power of 2
303 * => timeout + 13 = log2(mmc->clock/4) + 1
304 * => timeout + 13 = fls(mmc->clock/4)
305 *
306 * However, the MMC spec "It is strongly recommended for hosts to
307 * implement more than 500ms timeout value even if the card
308 * indicates the 250ms maximum busy length." Even the previous
309 * value of 300ms is known to be insufficient for some cards.
310 * So, we use
311 * => timeout + 13 = fls(mmc->clock/2)
312 */
313 timeout = fls(mmc->clock/2);
314 timeout -= 13;
315
316 if (timeout > 14)
317 timeout = 14;
318
319 if (timeout < 0)
320 timeout = 0;
321
322 if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_ESDHC_A001) &&
323 (timeout == 4 || timeout == 8 || timeout == 12))
324 timeout++;
325
326 if (IS_ENABLED(ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE))
327 timeout = 0xE;
328
329 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
330
331 return 0;
332 }
333
334 /*
335 * Sends a command out on the bus. Takes the mmc pointer,
336 * a command pointer, and an optional data pointer.
337 */
esdhc_send_cmd_common(struct fsl_esdhc_priv * priv,struct mmc * mmc,struct mmc_cmd * cmd,struct mmc_data * data)338 static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc,
339 struct mmc_cmd *cmd, struct mmc_data *data)
340 {
341 int err = 0;
342 uint xfertyp;
343 uint irqstat;
344 u32 flags = IRQSTAT_CC | IRQSTAT_CTOE;
345 struct fsl_esdhc *regs = priv->esdhc_regs;
346 unsigned long start;
347
348 if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_ESDHC111) &&
349 cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
350 return 0;
351
352 esdhc_write32(®s->irqstat, -1);
353
354 sync();
355
356 /* Wait for the bus to be idle */
357 while ((esdhc_read32(®s->prsstat) & PRSSTAT_CICHB) ||
358 (esdhc_read32(®s->prsstat) & PRSSTAT_CIDHB))
359 ;
360
361 while (esdhc_read32(®s->prsstat) & PRSSTAT_DLA)
362 ;
363
364 /* Wait at least 8 SD clock cycles before the next command */
365 /*
366 * Note: This is way more than 8 cycles, but 1ms seems to
367 * resolve timing issues with some cards
368 */
369 udelay(1000);
370
371 /* Set up for a data transfer if we have one */
372 if (data) {
373 err = esdhc_setup_data(priv, mmc, data);
374 if(err)
375 return err;
376 }
377
378 /* Figure out the transfer arguments */
379 xfertyp = esdhc_xfertyp(cmd, data);
380
381 /* Mask all irqs */
382 esdhc_write32(®s->irqsigen, 0);
383
384 /* Send the command */
385 esdhc_write32(®s->cmdarg, cmd->cmdarg);
386 esdhc_write32(®s->xfertyp, xfertyp);
387
388 if (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
389 cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)
390 flags = IRQSTAT_BRR;
391
392 /* Wait for the command to complete */
393 start = get_timer(0);
394 while (!(esdhc_read32(®s->irqstat) & flags)) {
395 if (get_timer(start) > 1000) {
396 err = -ETIMEDOUT;
397 goto out;
398 }
399 }
400
401 irqstat = esdhc_read32(®s->irqstat);
402
403 if (irqstat & CMD_ERR) {
404 err = -ECOMM;
405 goto out;
406 }
407
408 if (irqstat & IRQSTAT_CTOE) {
409 err = -ETIMEDOUT;
410 goto out;
411 }
412
413 /* Workaround for ESDHC errata ENGcm03648 */
414 if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
415 int timeout = 6000;
416
417 /* Poll on DATA0 line for cmd with busy signal for 600 ms */
418 while (timeout > 0 && !(esdhc_read32(®s->prsstat) &
419 PRSSTAT_DAT0)) {
420 udelay(100);
421 timeout--;
422 }
423
424 if (timeout <= 0) {
425 printf("Timeout waiting for DAT0 to go high!\n");
426 err = -ETIMEDOUT;
427 goto out;
428 }
429 }
430
431 /* Copy the response to the response buffer */
432 if (cmd->resp_type & MMC_RSP_136) {
433 u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
434
435 cmdrsp3 = esdhc_read32(®s->cmdrsp3);
436 cmdrsp2 = esdhc_read32(®s->cmdrsp2);
437 cmdrsp1 = esdhc_read32(®s->cmdrsp1);
438 cmdrsp0 = esdhc_read32(®s->cmdrsp0);
439 cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24);
440 cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24);
441 cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24);
442 cmd->response[3] = (cmdrsp0 << 8);
443 } else
444 cmd->response[0] = esdhc_read32(®s->cmdrsp0);
445
446 /* Wait until all of the blocks are transferred */
447 if (data) {
448 if (IS_ENABLED(CONFIG_SYS_FSL_ESDHC_USE_PIO)) {
449 esdhc_pio_read_write(priv, data);
450 } else {
451 flags = DATA_COMPLETE;
452 if (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
453 cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)
454 flags = IRQSTAT_BRR;
455
456 do {
457 irqstat = esdhc_read32(®s->irqstat);
458
459 if (irqstat & IRQSTAT_DTOE) {
460 err = -ETIMEDOUT;
461 goto out;
462 }
463
464 if (irqstat & DATA_ERR) {
465 err = -ECOMM;
466 goto out;
467 }
468 } while ((irqstat & flags) != flags);
469
470 /*
471 * Need invalidate the dcache here again to avoid any
472 * cache-fill during the DMA operations such as the
473 * speculative pre-fetching etc.
474 */
475 dma_unmap_single(priv->dma_addr,
476 data->blocks * data->blocksize,
477 mmc_get_dma_dir(data));
478 }
479 }
480
481 out:
482 /* Reset CMD and DATA portions on error */
483 if (err) {
484 esdhc_write32(®s->sysctl, esdhc_read32(®s->sysctl) |
485 SYSCTL_RSTC);
486 while (esdhc_read32(®s->sysctl) & SYSCTL_RSTC)
487 ;
488
489 if (data) {
490 esdhc_write32(®s->sysctl,
491 esdhc_read32(®s->sysctl) |
492 SYSCTL_RSTD);
493 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTD))
494 ;
495 }
496 }
497
498 esdhc_write32(®s->irqstat, -1);
499
500 return err;
501 }
502
set_sysctl(struct fsl_esdhc_priv * priv,struct mmc * mmc,uint clock)503 static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock)
504 {
505 struct fsl_esdhc *regs = priv->esdhc_regs;
506 int div = 1;
507 int pre_div = 2;
508 unsigned int sdhc_clk = priv->sdhc_clk;
509 u32 time_out;
510 u32 value;
511 uint clk;
512
513 if (clock < mmc->cfg->f_min)
514 clock = mmc->cfg->f_min;
515
516 while (sdhc_clk / (16 * pre_div) > clock && pre_div < 256)
517 pre_div *= 2;
518
519 while (sdhc_clk / (div * pre_div) > clock && div < 16)
520 div++;
521
522 if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_A011334) &&
523 clock == 200000000 && mmc->selected_mode == MMC_HS_400) {
524 u32 div_ratio = pre_div * div;
525
526 if (div_ratio <= 4) {
527 pre_div = 4;
528 div = 1;
529 } else if (div_ratio <= 8) {
530 pre_div = 4;
531 div = 2;
532 } else if (div_ratio <= 12) {
533 pre_div = 4;
534 div = 3;
535 } else {
536 printf("unsupported clock division.\n");
537 }
538 }
539
540 mmc->clock = sdhc_clk / pre_div / div;
541 priv->clock = mmc->clock;
542
543 pre_div >>= 1;
544 div -= 1;
545
546 clk = (pre_div << 8) | (div << 4);
547
548 esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN);
549
550 esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk);
551
552 time_out = 20;
553 value = PRSSTAT_SDSTB;
554 while (!(esdhc_read32(®s->prsstat) & value)) {
555 if (time_out == 0) {
556 printf("fsl_esdhc: Internal clock never stabilised.\n");
557 break;
558 }
559 time_out--;
560 mdelay(1);
561 }
562
563 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
564 }
565
esdhc_clock_control(struct fsl_esdhc_priv * priv,bool enable)566 static void esdhc_clock_control(struct fsl_esdhc_priv *priv, bool enable)
567 {
568 struct fsl_esdhc *regs = priv->esdhc_regs;
569 u32 value;
570 u32 time_out;
571
572 value = esdhc_read32(®s->sysctl);
573
574 if (enable)
575 value |= SYSCTL_CKEN;
576 else
577 value &= ~SYSCTL_CKEN;
578
579 esdhc_write32(®s->sysctl, value);
580
581 time_out = 20;
582 value = PRSSTAT_SDSTB;
583 while (!(esdhc_read32(®s->prsstat) & value)) {
584 if (time_out == 0) {
585 printf("fsl_esdhc: Internal clock never stabilised.\n");
586 break;
587 }
588 time_out--;
589 mdelay(1);
590 }
591 }
592
esdhc_flush_async_fifo(struct fsl_esdhc_priv * priv)593 static void esdhc_flush_async_fifo(struct fsl_esdhc_priv *priv)
594 {
595 struct fsl_esdhc *regs = priv->esdhc_regs;
596 u32 time_out;
597
598 esdhc_setbits32(®s->esdhcctl, ESDHCCTL_FAF);
599
600 time_out = 20;
601 while (esdhc_read32(®s->esdhcctl) & ESDHCCTL_FAF) {
602 if (time_out == 0) {
603 printf("fsl_esdhc: Flush asynchronous FIFO timeout.\n");
604 break;
605 }
606 time_out--;
607 mdelay(1);
608 }
609 }
610
esdhc_tuning_block_enable(struct fsl_esdhc_priv * priv,bool en)611 static void esdhc_tuning_block_enable(struct fsl_esdhc_priv *priv,
612 bool en)
613 {
614 struct fsl_esdhc *regs = priv->esdhc_regs;
615
616 esdhc_clock_control(priv, false);
617 esdhc_flush_async_fifo(priv);
618 if (en)
619 esdhc_setbits32(®s->tbctl, TBCTL_TB_EN);
620 else
621 esdhc_clrbits32(®s->tbctl, TBCTL_TB_EN);
622 esdhc_clock_control(priv, true);
623 }
624
esdhc_exit_hs400(struct fsl_esdhc_priv * priv)625 static void esdhc_exit_hs400(struct fsl_esdhc_priv *priv)
626 {
627 struct fsl_esdhc *regs = priv->esdhc_regs;
628
629 esdhc_clrbits32(®s->sdtimingctl, FLW_CTL_BG);
630 esdhc_clrbits32(®s->sdclkctl, CMD_CLK_CTL);
631
632 esdhc_clock_control(priv, false);
633 esdhc_clrbits32(®s->tbctl, HS400_MODE);
634 esdhc_clock_control(priv, true);
635
636 esdhc_clrbits32(®s->dllcfg0, DLL_FREQ_SEL | DLL_ENABLE);
637 esdhc_clrbits32(®s->tbctl, HS400_WNDW_ADJUST);
638
639 esdhc_tuning_block_enable(priv, false);
640 }
641
esdhc_set_timing(struct fsl_esdhc_priv * priv,enum bus_mode mode)642 static int esdhc_set_timing(struct fsl_esdhc_priv *priv, enum bus_mode mode)
643 {
644 struct fsl_esdhc *regs = priv->esdhc_regs;
645 ulong start;
646 u32 val;
647
648 /* Exit HS400 mode before setting any other mode */
649 if (esdhc_read32(®s->tbctl) & HS400_MODE &&
650 mode != MMC_HS_400)
651 esdhc_exit_hs400(priv);
652
653 esdhc_clock_control(priv, false);
654
655 if (mode == MMC_HS_200)
656 esdhc_clrsetbits32(®s->autoc12err, UHSM_MASK,
657 UHSM_SDR104_HS200);
658 if (mode == MMC_HS_400) {
659 esdhc_setbits32(®s->tbctl, HS400_MODE);
660 esdhc_setbits32(®s->sdclkctl, CMD_CLK_CTL);
661 esdhc_clock_control(priv, true);
662
663 if (priv->clock == 200000000)
664 esdhc_setbits32(®s->dllcfg0, DLL_FREQ_SEL);
665
666 esdhc_setbits32(®s->dllcfg0, DLL_ENABLE);
667
668 esdhc_setbits32(®s->dllcfg0, DLL_RESET);
669 udelay(1);
670 esdhc_clrbits32(®s->dllcfg0, DLL_RESET);
671
672 start = get_timer(0);
673 val = DLL_STS_SLV_LOCK;
674 while (!(esdhc_read32(®s->dllstat0) & val)) {
675 if (get_timer(start) > 1000) {
676 printf("fsl_esdhc: delay chain lock timeout\n");
677 return -ETIMEDOUT;
678 }
679 }
680
681 esdhc_setbits32(®s->tbctl, HS400_WNDW_ADJUST);
682
683 esdhc_clock_control(priv, false);
684 esdhc_flush_async_fifo(priv);
685 }
686 esdhc_clock_control(priv, true);
687 return 0;
688 }
689
esdhc_set_ios_common(struct fsl_esdhc_priv * priv,struct mmc * mmc)690 static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
691 {
692 struct fsl_esdhc *regs = priv->esdhc_regs;
693 int ret;
694
695 if (priv->is_sdhc_per_clk) {
696 /* Select to use peripheral clock */
697 esdhc_clock_control(priv, false);
698 esdhc_setbits32(®s->esdhcctl, ESDHCCTL_PCS);
699 esdhc_clock_control(priv, true);
700 }
701
702 if (mmc->selected_mode == MMC_HS_400)
703 esdhc_tuning_block_enable(priv, true);
704
705 /* Set the clock speed */
706 if (priv->clock != mmc->clock)
707 set_sysctl(priv, mmc, mmc->clock);
708
709 /* Set timing */
710 ret = esdhc_set_timing(priv, mmc->selected_mode);
711 if (ret)
712 return ret;
713
714 /* Set the bus width */
715 esdhc_clrbits32(®s->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);
716
717 if (mmc->bus_width == 4)
718 esdhc_setbits32(®s->proctl, PROCTL_DTW_4);
719 else if (mmc->bus_width == 8)
720 esdhc_setbits32(®s->proctl, PROCTL_DTW_8);
721
722 return 0;
723 }
724
esdhc_enable_cache_snooping(struct fsl_esdhc * regs)725 static void esdhc_enable_cache_snooping(struct fsl_esdhc *regs)
726 {
727 #ifdef CONFIG_ARCH_MPC830X
728 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
729 sysconf83xx_t *sysconf = &immr->sysconf;
730
731 setbits_be32(&sysconf->sdhccr, 0x02000000);
732 #else
733 esdhc_write32(®s->esdhcctl, 0x00000040);
734 #endif
735 }
736
esdhc_init_common(struct fsl_esdhc_priv * priv,struct mmc * mmc)737 static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
738 {
739 struct fsl_esdhc *regs = priv->esdhc_regs;
740 ulong start;
741
742 /* Reset the entire host controller */
743 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA);
744
745 /* Wait until the controller is available */
746 start = get_timer(0);
747 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA)) {
748 if (get_timer(start) > 1000)
749 return -ETIMEDOUT;
750 }
751
752 /* Clean TBCTL[TB_EN] which is not able to be reset by reset all */
753 esdhc_clrbits32(®s->tbctl, TBCTL_TB_EN);
754
755 esdhc_enable_cache_snooping(regs);
756
757 esdhc_setbits32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
758
759 /* Set the initial clock speed */
760 set_sysctl(priv, mmc, 400000);
761
762 /* Disable the BRR and BWR bits in IRQSTAT */
763 esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
764
765 /* Put the PROCTL reg back to the default */
766 esdhc_write32(®s->proctl, PROCTL_INIT);
767
768 /* Set timout to the maximum value */
769 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
770
771 if (IS_ENABLED(CONFIG_SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND))
772 esdhc_clrbits32(®s->dllcfg1, DLL_PD_PULSE_STRETCH_SEL);
773
774 return 0;
775 }
776
esdhc_getcd_common(struct fsl_esdhc_priv * priv)777 static int esdhc_getcd_common(struct fsl_esdhc_priv *priv)
778 {
779 struct fsl_esdhc *regs = priv->esdhc_regs;
780
781 #ifdef CONFIG_ESDHC_DETECT_QUIRK
782 if (CONFIG_ESDHC_DETECT_QUIRK)
783 return 1;
784 #endif
785 if (esdhc_read32(®s->prsstat) & PRSSTAT_CINS)
786 return 1;
787
788 return 0;
789 }
790
fsl_esdhc_get_cfg_common(struct fsl_esdhc_priv * priv,struct mmc_config * cfg)791 static void fsl_esdhc_get_cfg_common(struct fsl_esdhc_priv *priv,
792 struct mmc_config *cfg)
793 {
794 struct fsl_esdhc *regs = priv->esdhc_regs;
795 u32 caps;
796
797 caps = esdhc_read32(®s->hostcapblt);
798
799 /*
800 * For eSDHC, power supply is through peripheral circuit. Some eSDHC
801 * versions have value 0 of the bit but that does not reflect the
802 * truth. 3.3V is common for SD/MMC, and is supported for all boards
803 * with eSDHC in current u-boot. So, make 3.3V is supported in
804 * default in code. CONFIG_FSL_ESDHC_VS33_NOT_SUPPORT can be enabled
805 * if future board does not support 3.3V.
806 */
807 caps |= HOSTCAPBLT_VS33;
808 if (IS_ENABLED(CONFIG_FSL_ESDHC_VS33_NOT_SUPPORT))
809 caps &= ~HOSTCAPBLT_VS33;
810
811 if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_ESDHC135))
812 caps &= ~(HOSTCAPBLT_SRS | HOSTCAPBLT_VS18 | HOSTCAPBLT_VS30);
813 if (caps & HOSTCAPBLT_VS18)
814 cfg->voltages |= MMC_VDD_165_195;
815 if (caps & HOSTCAPBLT_VS30)
816 cfg->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
817 if (caps & HOSTCAPBLT_VS33)
818 cfg->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;
819
820 cfg->name = "FSL_SDHC";
821
822 if (caps & HOSTCAPBLT_HSS)
823 cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
824
825 cfg->f_min = 400000;
826 cfg->f_max = min(priv->sdhc_clk, (u32)200000000);
827 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
828 }
829
830 #ifdef CONFIG_OF_LIBFDT
esdhc_status_fixup(void * blob,const char * compat)831 __weak int esdhc_status_fixup(void *blob, const char *compat)
832 {
833 if (IS_ENABLED(CONFIG_FSL_ESDHC_PIN_MUX) && !hwconfig("esdhc")) {
834 do_fixup_by_compat(blob, compat, "status", "disabled",
835 sizeof("disabled"), 1);
836 return 1;
837 }
838
839 return 0;
840 }
841
842
843 #if CONFIG_IS_ENABLED(DM_MMC)
844 static int fsl_esdhc_get_cd(struct udevice *dev);
esdhc_disable_for_no_card(void * blob)845 static void esdhc_disable_for_no_card(void *blob)
846 {
847 struct udevice *dev;
848
849 for (uclass_first_device(UCLASS_MMC, &dev);
850 dev;
851 uclass_next_device(&dev)) {
852 char esdhc_path[50];
853
854 if (fsl_esdhc_get_cd(dev))
855 continue;
856
857 snprintf(esdhc_path, sizeof(esdhc_path), "/soc/esdhc@%lx",
858 (unsigned long)dev_read_addr(dev));
859 do_fixup_by_path(blob, esdhc_path, "status", "disabled",
860 sizeof("disabled"), 1);
861 }
862 }
863 #else
esdhc_disable_for_no_card(void * blob)864 static void esdhc_disable_for_no_card(void *blob)
865 {
866 }
867 #endif
868
fdt_fixup_esdhc(void * blob,struct bd_info * bd)869 void fdt_fixup_esdhc(void *blob, struct bd_info *bd)
870 {
871 const char *compat = "fsl,esdhc";
872
873 if (esdhc_status_fixup(blob, compat))
874 return;
875
876 if (IS_ENABLED(CONFIG_FSL_ESDHC_33V_IO_RELIABILITY_WORKAROUND))
877 esdhc_disable_for_no_card(blob);
878
879 do_fixup_by_compat_u32(blob, compat, "clock-frequency",
880 gd->arch.sdhc_clk, 1);
881 }
882 #endif
883
884 #if !CONFIG_IS_ENABLED(DM_MMC)
esdhc_getcd(struct mmc * mmc)885 static int esdhc_getcd(struct mmc *mmc)
886 {
887 struct fsl_esdhc_priv *priv = mmc->priv;
888
889 return esdhc_getcd_common(priv);
890 }
891
esdhc_init(struct mmc * mmc)892 static int esdhc_init(struct mmc *mmc)
893 {
894 struct fsl_esdhc_priv *priv = mmc->priv;
895
896 return esdhc_init_common(priv, mmc);
897 }
898
esdhc_send_cmd(struct mmc * mmc,struct mmc_cmd * cmd,struct mmc_data * data)899 static int esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
900 struct mmc_data *data)
901 {
902 struct fsl_esdhc_priv *priv = mmc->priv;
903
904 return esdhc_send_cmd_common(priv, mmc, cmd, data);
905 }
906
esdhc_set_ios(struct mmc * mmc)907 static int esdhc_set_ios(struct mmc *mmc)
908 {
909 struct fsl_esdhc_priv *priv = mmc->priv;
910
911 return esdhc_set_ios_common(priv, mmc);
912 }
913
914 static const struct mmc_ops esdhc_ops = {
915 .getcd = esdhc_getcd,
916 .init = esdhc_init,
917 .send_cmd = esdhc_send_cmd,
918 .set_ios = esdhc_set_ios,
919 };
920
fsl_esdhc_initialize(struct bd_info * bis,struct fsl_esdhc_cfg * cfg)921 int fsl_esdhc_initialize(struct bd_info *bis, struct fsl_esdhc_cfg *cfg)
922 {
923 struct fsl_esdhc_plat *plat;
924 struct fsl_esdhc_priv *priv;
925 struct mmc_config *mmc_cfg;
926 struct mmc *mmc;
927
928 if (!cfg)
929 return -EINVAL;
930
931 priv = calloc(sizeof(struct fsl_esdhc_priv), 1);
932 if (!priv)
933 return -ENOMEM;
934 plat = calloc(sizeof(struct fsl_esdhc_plat), 1);
935 if (!plat) {
936 free(priv);
937 return -ENOMEM;
938 }
939
940 priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base);
941 priv->sdhc_clk = cfg->sdhc_clk;
942 if (gd->arch.sdhc_per_clk)
943 priv->is_sdhc_per_clk = true;
944
945 mmc_cfg = &plat->cfg;
946
947 if (cfg->max_bus_width == 8) {
948 mmc_cfg->host_caps |= MMC_MODE_1BIT | MMC_MODE_4BIT |
949 MMC_MODE_8BIT;
950 } else if (cfg->max_bus_width == 4) {
951 mmc_cfg->host_caps |= MMC_MODE_1BIT | MMC_MODE_4BIT;
952 } else if (cfg->max_bus_width == 1) {
953 mmc_cfg->host_caps |= MMC_MODE_1BIT;
954 } else {
955 mmc_cfg->host_caps |= MMC_MODE_1BIT | MMC_MODE_4BIT |
956 MMC_MODE_8BIT;
957 printf("No max bus width provided. Assume 8-bit supported.\n");
958 }
959
960 if (IS_ENABLED(CONFIG_ESDHC_DETECT_8_BIT_QUIRK))
961 mmc_cfg->host_caps &= ~MMC_MODE_8BIT;
962
963 mmc_cfg->ops = &esdhc_ops;
964
965 fsl_esdhc_get_cfg_common(priv, mmc_cfg);
966
967 mmc = mmc_create(mmc_cfg, priv);
968 if (!mmc)
969 return -EIO;
970
971 priv->mmc = mmc;
972 return 0;
973 }
974
fsl_esdhc_mmc_init(struct bd_info * bis)975 int fsl_esdhc_mmc_init(struct bd_info *bis)
976 {
977 struct fsl_esdhc_cfg *cfg;
978
979 cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1);
980 cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
981 /* Prefer peripheral clock which provides higher frequency. */
982 if (gd->arch.sdhc_per_clk)
983 cfg->sdhc_clk = gd->arch.sdhc_per_clk;
984 else
985 cfg->sdhc_clk = gd->arch.sdhc_clk;
986 return fsl_esdhc_initialize(bis, cfg);
987 }
988 #else /* DM_MMC */
fsl_esdhc_probe(struct udevice * dev)989 static int fsl_esdhc_probe(struct udevice *dev)
990 {
991 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
992 struct fsl_esdhc_plat *plat = dev_get_plat(dev);
993 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
994 u32 caps, hostver;
995 fdt_addr_t addr;
996 struct mmc *mmc;
997 int ret;
998
999 addr = dev_read_addr(dev);
1000 if (addr == FDT_ADDR_T_NONE)
1001 return -EINVAL;
1002 #ifdef CONFIG_PPC
1003 priv->esdhc_regs = (struct fsl_esdhc *)lower_32_bits(addr);
1004 #else
1005 priv->esdhc_regs = (struct fsl_esdhc *)addr;
1006 #endif
1007 priv->dev = dev;
1008
1009 if (IS_ENABLED(CONFIG_FSL_ESDHC_SUPPORT_ADMA2)) {
1010 /*
1011 * Only newer eSDHC controllers can do ADMA2 if the ADMA flag
1012 * is set in the host capabilities register.
1013 */
1014 caps = esdhc_read32(&priv->esdhc_regs->hostcapblt);
1015 hostver = esdhc_read32(&priv->esdhc_regs->hostver);
1016 if (caps & HOSTCAPBLT_DMAS &&
1017 HOSTVER_VENDOR(hostver) > VENDOR_V_22) {
1018 priv->adma_desc_table = sdhci_adma_init();
1019 if (!priv->adma_desc_table)
1020 debug("Could not allocate ADMA tables, falling back to SDMA\n");
1021 }
1022 }
1023
1024 if (gd->arch.sdhc_per_clk) {
1025 priv->sdhc_clk = gd->arch.sdhc_per_clk;
1026 priv->is_sdhc_per_clk = true;
1027 } else {
1028 priv->sdhc_clk = gd->arch.sdhc_clk;
1029 }
1030
1031 if (priv->sdhc_clk <= 0) {
1032 dev_err(dev, "Unable to get clk for %s\n", dev->name);
1033 return -EINVAL;
1034 }
1035
1036 fsl_esdhc_get_cfg_common(priv, &plat->cfg);
1037
1038 mmc_of_parse(dev, &plat->cfg);
1039
1040 mmc = &plat->mmc;
1041 mmc->cfg = &plat->cfg;
1042 mmc->dev = dev;
1043
1044 upriv->mmc = mmc;
1045
1046 ret = esdhc_init_common(priv, mmc);
1047 if (ret)
1048 return ret;
1049
1050 if (IS_ENABLED(CONFIG_FSL_ESDHC_33V_IO_RELIABILITY_WORKAROUND) &&
1051 !fsl_esdhc_get_cd(dev))
1052 esdhc_setbits32(&priv->esdhc_regs->proctl, PROCTL_VOLT_SEL);
1053
1054 return 0;
1055 }
1056
fsl_esdhc_get_cd(struct udevice * dev)1057 static int fsl_esdhc_get_cd(struct udevice *dev)
1058 {
1059 struct fsl_esdhc_plat *plat = dev_get_plat(dev);
1060 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1061
1062 if (plat->cfg.host_caps & MMC_CAP_NONREMOVABLE)
1063 return 1;
1064
1065 return esdhc_getcd_common(priv);
1066 }
1067
fsl_esdhc_send_cmd(struct udevice * dev,struct mmc_cmd * cmd,struct mmc_data * data)1068 static int fsl_esdhc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
1069 struct mmc_data *data)
1070 {
1071 struct fsl_esdhc_plat *plat = dev_get_plat(dev);
1072 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1073
1074 return esdhc_send_cmd_common(priv, &plat->mmc, cmd, data);
1075 }
1076
fsl_esdhc_set_ios(struct udevice * dev)1077 static int fsl_esdhc_set_ios(struct udevice *dev)
1078 {
1079 struct fsl_esdhc_plat *plat = dev_get_plat(dev);
1080 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1081
1082 return esdhc_set_ios_common(priv, &plat->mmc);
1083 }
1084
fsl_esdhc_reinit(struct udevice * dev)1085 static int fsl_esdhc_reinit(struct udevice *dev)
1086 {
1087 struct fsl_esdhc_plat *plat = dev_get_plat(dev);
1088 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1089
1090 return esdhc_init_common(priv, &plat->mmc);
1091 }
1092
1093 #ifdef MMC_SUPPORTS_TUNING
fsl_esdhc_execute_tuning(struct udevice * dev,uint32_t opcode)1094 static int fsl_esdhc_execute_tuning(struct udevice *dev, uint32_t opcode)
1095 {
1096 struct fsl_esdhc_plat *plat = dev_get_plat(dev);
1097 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1098 struct fsl_esdhc *regs = priv->esdhc_regs;
1099 struct mmc *mmc = &plat->mmc;
1100 u32 val, irqstaten;
1101 int i;
1102
1103 if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_A011334) &&
1104 plat->mmc.hs400_tuning)
1105 set_sysctl(priv, mmc, mmc->clock);
1106
1107 esdhc_tuning_block_enable(priv, true);
1108 esdhc_setbits32(®s->autoc12err, EXECUTE_TUNING);
1109
1110 irqstaten = esdhc_read32(®s->irqstaten);
1111 esdhc_write32(®s->irqstaten, IRQSTATEN_BRR);
1112
1113 for (i = 0; i < MAX_TUNING_LOOP; i++) {
1114 mmc_send_tuning(mmc, opcode, NULL);
1115 mdelay(1);
1116
1117 val = esdhc_read32(®s->autoc12err);
1118 if (!(val & EXECUTE_TUNING)) {
1119 if (val & SMPCLKSEL)
1120 break;
1121 }
1122 }
1123
1124 esdhc_write32(®s->irqstaten, irqstaten);
1125
1126 if (i != MAX_TUNING_LOOP) {
1127 if (plat->mmc.hs400_tuning)
1128 esdhc_setbits32(®s->sdtimingctl, FLW_CTL_BG);
1129 return 0;
1130 }
1131
1132 printf("fsl_esdhc: tuning failed!\n");
1133 esdhc_clrbits32(®s->autoc12err, SMPCLKSEL);
1134 esdhc_clrbits32(®s->autoc12err, EXECUTE_TUNING);
1135 esdhc_tuning_block_enable(priv, false);
1136 return -ETIMEDOUT;
1137 }
1138 #endif
1139
fsl_esdhc_hs400_prepare_ddr(struct udevice * dev)1140 int fsl_esdhc_hs400_prepare_ddr(struct udevice *dev)
1141 {
1142 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1143
1144 esdhc_tuning_block_enable(priv, false);
1145 return 0;
1146 }
1147
1148 static const struct dm_mmc_ops fsl_esdhc_ops = {
1149 .get_cd = fsl_esdhc_get_cd,
1150 .send_cmd = fsl_esdhc_send_cmd,
1151 .set_ios = fsl_esdhc_set_ios,
1152 #ifdef MMC_SUPPORTS_TUNING
1153 .execute_tuning = fsl_esdhc_execute_tuning,
1154 #endif
1155 .reinit = fsl_esdhc_reinit,
1156 .hs400_prepare_ddr = fsl_esdhc_hs400_prepare_ddr,
1157 };
1158
1159 static const struct udevice_id fsl_esdhc_ids[] = {
1160 { .compatible = "fsl,esdhc", },
1161 { /* sentinel */ }
1162 };
1163
fsl_esdhc_bind(struct udevice * dev)1164 static int fsl_esdhc_bind(struct udevice *dev)
1165 {
1166 struct fsl_esdhc_plat *plat = dev_get_plat(dev);
1167
1168 return mmc_bind(dev, &plat->mmc, &plat->cfg);
1169 }
1170
1171 U_BOOT_DRIVER(fsl_esdhc) = {
1172 .name = "fsl-esdhc-mmc",
1173 .id = UCLASS_MMC,
1174 .of_match = fsl_esdhc_ids,
1175 .ops = &fsl_esdhc_ops,
1176 .bind = fsl_esdhc_bind,
1177 .probe = fsl_esdhc_probe,
1178 .plat_auto = sizeof(struct fsl_esdhc_plat),
1179 .priv_auto = sizeof(struct fsl_esdhc_priv),
1180 };
1181 #endif
1182