1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
4 */
5
6 #include <common.h>
7 #include <clk.h>
8 #include <dm.h>
9 #include <hang.h>
10 #include <log.h>
11 #include <dt-bindings/memory/rk3368-dmc.h>
12 #include <dt-structs.h>
13 #include <ram.h>
14 #include <regmap.h>
15 #include <syscon.h>
16 #include <asm/io.h>
17 #include <asm/arch-rockchip/clock.h>
18 #include <asm/arch-rockchip/cru_rk3368.h>
19 #include <asm/arch-rockchip/grf_rk3368.h>
20 #include <asm/arch-rockchip/ddr_rk3368.h>
21 #include <asm/arch-rockchip/sdram.h>
22 #include <asm/arch-rockchip/sdram_rk3288.h>
23 #include <linux/bitops.h>
24 #include <linux/delay.h>
25 #include <linux/err.h>
26
27 struct dram_info {
28 struct ram_info info;
29 struct clk ddr_clk;
30 struct rk3368_cru *cru;
31 struct rk3368_grf *grf;
32 struct rk3368_ddr_pctl *pctl;
33 struct rk3368_ddrphy *phy;
34 struct rk3368_pmu_grf *pmugrf;
35 struct rk3368_msch *msch;
36 };
37
38 struct rk3368_sdram_params {
39 #if CONFIG_IS_ENABLED(OF_PLATDATA)
40 struct dtd_rockchip_rk3368_dmc of_plat;
41 #endif
42 struct rk3288_sdram_pctl_timing pctl_timing;
43 u32 trefi_mem_ddr3;
44 struct rk3288_sdram_channel chan;
45 struct regmap *map;
46 u32 ddr_freq;
47 u32 memory_schedule;
48 u32 ddr_speed_bin;
49 u32 tfaw_mult;
50 };
51
52 /* PTCL bits */
53 enum {
54 /* PCTL_DFISTCFG0 */
55 DFI_INIT_START = BIT(0),
56 DFI_DATA_BYTE_DISABLE_EN = BIT(2),
57
58 /* PCTL_DFISTCFG1 */
59 DFI_DRAM_CLK_SR_EN = BIT(0),
60 DFI_DRAM_CLK_DPD_EN = BIT(1),
61 ODT_LEN_BL8_W_SHIFT = 16,
62
63 /* PCTL_DFISTCFG2 */
64 DFI_PARITY_INTR_EN = BIT(0),
65 DFI_PARITY_EN = BIT(1),
66
67 /* PCTL_DFILPCFG0 */
68 TLP_RESP_TIME_SHIFT = 16,
69 LP_SR_EN = BIT(8),
70 LP_PD_EN = BIT(0),
71
72 /* PCTL_DFIODTCFG */
73 RANK0_ODT_WRITE_SEL = BIT(3),
74 RANK1_ODT_WRITE_SEL = BIT(11),
75
76 /* PCTL_SCFG */
77 HW_LOW_POWER_EN = BIT(0),
78
79 /* PCTL_MCMD */
80 START_CMD = BIT(31),
81 MCMD_RANK0 = BIT(20),
82 MCMD_RANK1 = BIT(21),
83 DESELECT_CMD = 0,
84 PREA_CMD,
85 REF_CMD,
86 MRS_CMD,
87 ZQCS_CMD,
88 ZQCL_CMD,
89 RSTL_CMD,
90 MRR_CMD = 8,
91 DPDE_CMD,
92
93 /* PCTL_POWCTL */
94 POWER_UP_START = BIT(0),
95
96 /* PCTL_POWSTAT */
97 POWER_UP_DONE = BIT(0),
98
99 /* PCTL_SCTL */
100 INIT_STATE = 0,
101 CFG_STATE,
102 GO_STATE,
103 SLEEP_STATE,
104 WAKEUP_STATE,
105
106 /* PCTL_STAT */
107 LP_TRIG_SHIFT = 4,
108 LP_TRIG_MASK = 7,
109 PCTL_STAT_MSK = 7,
110 INIT_MEM = 0,
111 CONFIG,
112 CONFIG_REQ,
113 ACCESS,
114 ACCESS_REQ,
115 LOW_POWER,
116 LOW_POWER_ENTRY_REQ,
117 LOW_POWER_EXIT_REQ,
118
119 /* PCTL_MCFG */
120 DDR2_DDR3_BL_8 = BIT(0),
121 DDR3_EN = BIT(5),
122 TFAW_TRRD_MULT4 = (0 << 18),
123 TFAW_TRRD_MULT5 = (1 << 18),
124 TFAW_TRRD_MULT6 = (2 << 18),
125 };
126
127 #define DDR3_MR0_WR(n) \
128 ((n <= 8) ? ((n - 4) << 9) : (((n >> 1) & 0x7) << 9))
129 #define DDR3_MR0_CL(n) \
130 ((((n - 4) & 0x7) << 4) | (((n - 4) & 0x8) >> 2))
131 #define DDR3_MR0_BL8 \
132 (0 << 0)
133 #define DDR3_MR0_DLL_RESET \
134 (1 << 8)
135 #define DDR3_MR1_RTT120OHM \
136 ((0 << 9) | (1 << 6) | (0 << 2))
137 #define DDR3_MR2_TWL(n) \
138 (((n - 5) & 0x7) << 3)
139
140
141 #ifdef CONFIG_TPL_BUILD
142
ddr_set_noc_spr_err_stall(struct rk3368_grf * grf,bool enable)143 static void ddr_set_noc_spr_err_stall(struct rk3368_grf *grf, bool enable)
144 {
145 if (enable)
146 rk_setreg(&grf->ddrc0_con0, NOC_RSP_ERR_STALL);
147 else
148 rk_clrreg(&grf->ddrc0_con0, NOC_RSP_ERR_STALL);
149 }
150
ddr_set_ddr3_mode(struct rk3368_grf * grf,bool ddr3_mode)151 static void ddr_set_ddr3_mode(struct rk3368_grf *grf, bool ddr3_mode)
152 {
153 if (ddr3_mode)
154 rk_setreg(&grf->ddrc0_con0, MSCH0_MAINDDR3_DDR3);
155 else
156 rk_clrreg(&grf->ddrc0_con0, MSCH0_MAINDDR3_DDR3);
157 }
158
ddrphy_config(struct rk3368_ddrphy * phy,u32 tcl,u32 tal,u32 tcwl)159 static void ddrphy_config(struct rk3368_ddrphy *phy,
160 u32 tcl, u32 tal, u32 tcwl)
161 {
162 int i;
163
164 /* Set to DDR3 mode */
165 clrsetbits_le32(&phy->reg[1], 0x3, 0x0);
166
167 /* DDRPHY_REGB: CL, AL */
168 clrsetbits_le32(&phy->reg[0xb], 0xff, tcl << 4 | tal);
169 /* DDRPHY_REGC: CWL */
170 clrsetbits_le32(&phy->reg[0xc], 0x0f, tcwl);
171
172 /* Update drive-strength */
173 writel(0xcc, &phy->reg[0x11]);
174 writel(0xaa, &phy->reg[0x16]);
175 /*
176 * Update NRCOMP/PRCOMP for all 4 channels (for details of all
177 * affected registers refer to the documentation of DDRPHY_REG20
178 * and DDRPHY_REG21 in the RK3368 TRM.
179 */
180 for (i = 0; i < 4; ++i) {
181 writel(0xcc, &phy->reg[0x20 + i * 0x10]);
182 writel(0x44, &phy->reg[0x21 + i * 0x10]);
183 }
184
185 /* Enable write-leveling calibration bypass */
186 setbits_le32(&phy->reg[2], BIT(3));
187 }
188
copy_to_reg(u32 * dest,const u32 * src,u32 n)189 static void copy_to_reg(u32 *dest, const u32 *src, u32 n)
190 {
191 int i;
192
193 for (i = 0; i < n / sizeof(u32); i++)
194 writel(*src++, dest++);
195 }
196
send_command(struct rk3368_ddr_pctl * pctl,u32 rank,u32 cmd)197 static void send_command(struct rk3368_ddr_pctl *pctl, u32 rank, u32 cmd)
198 {
199 u32 mcmd = START_CMD | cmd | rank;
200
201 debug("%s: writing %x to MCMD\n", __func__, mcmd);
202 writel(mcmd, &pctl->mcmd);
203 while (readl(&pctl->mcmd) & START_CMD)
204 /* spin */;
205 }
206
send_mrs(struct rk3368_ddr_pctl * pctl,u32 rank,u32 mr_num,u32 mr_data)207 static void send_mrs(struct rk3368_ddr_pctl *pctl,
208 u32 rank, u32 mr_num, u32 mr_data)
209 {
210 u32 mcmd = START_CMD | MRS_CMD | rank | (mr_num << 17) | (mr_data << 4);
211
212 debug("%s: writing %x to MCMD\n", __func__, mcmd);
213 writel(mcmd, &pctl->mcmd);
214 while (readl(&pctl->mcmd) & START_CMD)
215 /* spin */;
216 }
217
memory_init(struct rk3368_ddr_pctl * pctl,struct rk3368_sdram_params * params)218 static int memory_init(struct rk3368_ddr_pctl *pctl,
219 struct rk3368_sdram_params *params)
220 {
221 u32 mr[4];
222 const ulong timeout_ms = 500;
223 ulong tmp;
224
225 /*
226 * Power up DRAM by DDR_PCTL_POWCTL[0] register of PCTL and
227 * wait power up DRAM finish with DDR_PCTL_POWSTAT[0] register
228 * of PCTL.
229 */
230 writel(POWER_UP_START, &pctl->powctl);
231
232 tmp = get_timer(0);
233 do {
234 if (get_timer(tmp) > timeout_ms) {
235 pr_err("%s: POWER_UP_START did not complete in %ld ms\n",
236 __func__, timeout_ms);
237 return -ETIME;
238 }
239 } while (!(readl(&pctl->powstat) & POWER_UP_DONE));
240
241 /* Configure MR0 through MR3 */
242 mr[0] = DDR3_MR0_WR(params->pctl_timing.twr) |
243 DDR3_MR0_CL(params->pctl_timing.tcl) |
244 DDR3_MR0_DLL_RESET;
245 mr[1] = DDR3_MR1_RTT120OHM;
246 mr[2] = DDR3_MR2_TWL(params->pctl_timing.tcwl);
247 mr[3] = 0;
248
249 /*
250 * Also see RK3368 Technical Reference Manual:
251 * "16.6.2 Initialization (DDR3 Initialization Sequence)"
252 */
253 send_command(pctl, MCMD_RANK0 | MCMD_RANK1, DESELECT_CMD);
254 udelay(1);
255 send_command(pctl, MCMD_RANK0 | MCMD_RANK1, PREA_CMD);
256 send_mrs(pctl, MCMD_RANK0 | MCMD_RANK1, 2, mr[2]);
257 send_mrs(pctl, MCMD_RANK0 | MCMD_RANK1, 3, mr[3]);
258 send_mrs(pctl, MCMD_RANK0 | MCMD_RANK1, 1, mr[1]);
259 send_mrs(pctl, MCMD_RANK0 | MCMD_RANK1, 0, mr[0]);
260 send_command(pctl, MCMD_RANK0 | MCMD_RANK1, ZQCL_CMD);
261
262 return 0;
263 }
264
move_to_config_state(struct rk3368_ddr_pctl * pctl)265 static void move_to_config_state(struct rk3368_ddr_pctl *pctl)
266 {
267 /*
268 * Also see RK3368 Technical Reference Manual:
269 * "16.6.1 State transition of PCTL (Moving to Config State)"
270 */
271 u32 state = readl(&pctl->stat) & PCTL_STAT_MSK;
272
273 switch (state) {
274 case LOW_POWER:
275 writel(WAKEUP_STATE, &pctl->sctl);
276 while ((readl(&pctl->stat) & PCTL_STAT_MSK) != ACCESS)
277 /* spin */;
278
279 /* fall-through */
280 case ACCESS:
281 case INIT_MEM:
282 writel(CFG_STATE, &pctl->sctl);
283 while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG)
284 /* spin */;
285 break;
286
287 case CONFIG:
288 return;
289
290 default:
291 break;
292 }
293 }
294
move_to_access_state(struct rk3368_ddr_pctl * pctl)295 static void move_to_access_state(struct rk3368_ddr_pctl *pctl)
296 {
297 /*
298 * Also see RK3368 Technical Reference Manual:
299 * "16.6.1 State transition of PCTL (Moving to Access State)"
300 */
301 u32 state = readl(&pctl->stat) & PCTL_STAT_MSK;
302
303 switch (state) {
304 case LOW_POWER:
305 if (((readl(&pctl->stat) >> LP_TRIG_SHIFT) &
306 LP_TRIG_MASK) == 1)
307 return;
308
309 writel(WAKEUP_STATE, &pctl->sctl);
310 while ((readl(&pctl->stat) & PCTL_STAT_MSK) != ACCESS)
311 /* spin */;
312
313 /* fall-through */
314 case INIT_MEM:
315 writel(CFG_STATE, &pctl->sctl);
316 while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG)
317 /* spin */;
318
319 /* fall-through */
320 case CONFIG:
321 writel(GO_STATE, &pctl->sctl);
322 while ((readl(&pctl->stat) & PCTL_STAT_MSK) == CONFIG)
323 /* spin */;
324 break;
325
326 case ACCESS:
327 return;
328
329 default:
330 break;
331 }
332 }
333
ddrctl_reset(struct rk3368_cru * cru)334 static void ddrctl_reset(struct rk3368_cru *cru)
335 {
336 const u32 ctl_reset = BIT(3) | BIT(2);
337 const u32 phy_reset = BIT(1) | BIT(0);
338
339 /*
340 * The PHY reset should be released before the PCTL reset.
341 *
342 * Note that the following sequence (including the number of
343 * us to delay between releasing the PHY and PCTL reset) has
344 * been adapted per feedback received from Rockchips, so do
345 * not try to optimise.
346 */
347 rk_setreg(&cru->softrst_con[10], ctl_reset | phy_reset);
348 udelay(1);
349 rk_clrreg(&cru->softrst_con[10], phy_reset);
350 udelay(5);
351 rk_clrreg(&cru->softrst_con[10], ctl_reset);
352 }
353
ddrphy_reset(struct rk3368_ddrphy * ddrphy)354 static void ddrphy_reset(struct rk3368_ddrphy *ddrphy)
355 {
356 /*
357 * The analog part of the PHY should be release at least 1000
358 * DRAM cycles before the digital part of the PHY (waiting for
359 * 5us will ensure this for a DRAM clock as low as 200MHz).
360 */
361 clrbits_le32(&ddrphy->reg[0], BIT(3) | BIT(2));
362 udelay(1);
363 setbits_le32(&ddrphy->reg[0], BIT(2));
364 udelay(5);
365 setbits_le32(&ddrphy->reg[0], BIT(3));
366 }
367
ddrphy_config_delays(struct rk3368_ddrphy * ddrphy,u32 freq)368 static void ddrphy_config_delays(struct rk3368_ddrphy *ddrphy, u32 freq)
369 {
370 u32 dqs_dll_delay;
371
372 setbits_le32(&ddrphy->reg[0x13], BIT(4));
373 clrbits_le32(&ddrphy->reg[0x14], BIT(3));
374
375 setbits_le32(&ddrphy->reg[0x26], BIT(4));
376 clrbits_le32(&ddrphy->reg[0x27], BIT(3));
377
378 setbits_le32(&ddrphy->reg[0x36], BIT(4));
379 clrbits_le32(&ddrphy->reg[0x37], BIT(3));
380
381 setbits_le32(&ddrphy->reg[0x46], BIT(4));
382 clrbits_le32(&ddrphy->reg[0x47], BIT(3));
383
384 setbits_le32(&ddrphy->reg[0x56], BIT(4));
385 clrbits_le32(&ddrphy->reg[0x57], BIT(3));
386
387 if (freq <= 400000000)
388 setbits_le32(&ddrphy->reg[0xa4], 0x1f);
389 else
390 clrbits_le32(&ddrphy->reg[0xa4], 0x1f);
391
392 if (freq < 681000000)
393 dqs_dll_delay = 3; /* 67.5 degree delay */
394 else
395 dqs_dll_delay = 2; /* 45 degree delay */
396
397 writel(dqs_dll_delay, &ddrphy->reg[0x28]);
398 writel(dqs_dll_delay, &ddrphy->reg[0x38]);
399 writel(dqs_dll_delay, &ddrphy->reg[0x48]);
400 writel(dqs_dll_delay, &ddrphy->reg[0x58]);
401 }
402
dfi_cfg(struct rk3368_ddr_pctl * pctl)403 static int dfi_cfg(struct rk3368_ddr_pctl *pctl)
404 {
405 const ulong timeout_ms = 200;
406 ulong tmp;
407
408 writel(DFI_DATA_BYTE_DISABLE_EN, &pctl->dfistcfg0);
409
410 writel(DFI_DRAM_CLK_SR_EN | DFI_DRAM_CLK_DPD_EN,
411 &pctl->dfistcfg1);
412 writel(DFI_PARITY_INTR_EN | DFI_PARITY_EN, &pctl->dfistcfg2);
413 writel(7 << TLP_RESP_TIME_SHIFT | LP_SR_EN | LP_PD_EN,
414 &pctl->dfilpcfg0);
415
416 writel(1, &pctl->dfitphyupdtype0);
417
418 writel(0x1f, &pctl->dfitphyrdlat);
419 writel(0, &pctl->dfitphywrdata);
420 writel(0, &pctl->dfiupdcfg); /* phyupd and ctrlupd disabled */
421
422 setbits_le32(&pctl->dfistcfg0, DFI_INIT_START);
423
424 tmp = get_timer(0);
425 do {
426 if (get_timer(tmp) > timeout_ms) {
427 pr_err("%s: DFI init did not complete within %ld ms\n",
428 __func__, timeout_ms);
429 return -ETIME;
430 }
431 } while ((readl(&pctl->dfiststat0) & 1) == 0);
432
433 return 0;
434 }
435
ps_to_tCK(const u32 ps,const ulong freq)436 static inline u32 ps_to_tCK(const u32 ps, const ulong freq)
437 {
438 const ulong MHz = 1000000;
439 return DIV_ROUND_UP(ps * freq, 1000000 * MHz);
440 }
441
ns_to_tCK(const u32 ns,const ulong freq)442 static inline u32 ns_to_tCK(const u32 ns, const ulong freq)
443 {
444 return ps_to_tCK(ns * 1000, freq);
445 }
446
tCK_to_ps(const ulong tCK,const ulong freq)447 static inline u32 tCK_to_ps(const ulong tCK, const ulong freq)
448 {
449 const ulong MHz = 1000000;
450 return DIV_ROUND_UP(tCK * 1000000 * MHz, freq);
451 }
452
pctl_calc_timings(struct rk3368_sdram_params * params,ulong freq)453 static int pctl_calc_timings(struct rk3368_sdram_params *params,
454 ulong freq)
455 {
456 struct rk3288_sdram_pctl_timing *pctl_timing = ¶ms->pctl_timing;
457 const ulong MHz = 1000000;
458 u32 tccd;
459 u32 tfaw_as_ps;
460
461 if (params->ddr_speed_bin != DDR3_1600K) {
462 pr_err("%s: unimplemented DDR3 speed bin %d\n",
463 __func__, params->ddr_speed_bin);
464 return -1;
465 }
466
467 /* PCTL is clocked at 1/2 the DRAM clock; err on the side of caution */
468 pctl_timing->togcnt1u = DIV_ROUND_UP(freq, 2 * MHz);
469 pctl_timing->togcnt100n = DIV_ROUND_UP(freq / 10, 2 * MHz);
470
471 pctl_timing->tinit = 200; /* 200 usec */
472 pctl_timing->trsth = 500; /* 500 usec */
473 pctl_timing->trefi = 78; /* 7.8usec = 78 * 100ns */
474 params->trefi_mem_ddr3 = ns_to_tCK(pctl_timing->trefi * 100, freq);
475
476 if (freq <= (400 * MHz)) {
477 pctl_timing->tcl = 6;
478 pctl_timing->tcwl = 10;
479 } else if (freq <= (533 * MHz)) {
480 pctl_timing->tcl = 8;
481 pctl_timing->tcwl = 6;
482 } else if (freq <= (666 * MHz)) {
483 pctl_timing->tcl = 10;
484 pctl_timing->tcwl = 7;
485 } else {
486 pctl_timing->tcl = 11;
487 pctl_timing->tcwl = 8;
488 }
489
490 pctl_timing->tmrd = 4; /* 4 tCK (all speed bins) */
491 pctl_timing->trfc = ns_to_tCK(350, freq); /* tRFC: 350 (max) @ 8GBit */
492 pctl_timing->trp = max(4u, ps_to_tCK(13750, freq));
493 /*
494 * JESD-79:
495 * READ to WRITE Command Delay = RL + tCCD / 2 + 2tCK - WL
496 */
497 tccd = 4;
498 pctl_timing->trtw = pctl_timing->tcl + tccd/2 + 2 - pctl_timing->tcwl;
499 pctl_timing->tal = 0;
500 pctl_timing->tras = ps_to_tCK(35000, freq);
501 pctl_timing->trc = ps_to_tCK(48750, freq);
502 pctl_timing->trcd = ps_to_tCK(13750, freq);
503 pctl_timing->trrd = max(4u, ps_to_tCK(7500, freq));
504 pctl_timing->trtp = max(4u, ps_to_tCK(7500, freq));
505 pctl_timing->twr = ps_to_tCK(15000, freq);
506 /* The DDR3 mode-register does only support even values for tWR > 8. */
507 if (pctl_timing->twr > 8)
508 pctl_timing->twr = (pctl_timing->twr + 1) & ~1;
509 pctl_timing->twtr = max(4u, ps_to_tCK(7500, freq));
510 pctl_timing->texsr = 512; /* tEXSR(max) is tDLLLK */
511 pctl_timing->txp = max(3u, ps_to_tCK(6000, freq));
512 pctl_timing->txpdll = max(10u, ps_to_tCK(24000, freq));
513 pctl_timing->tzqcs = max(64u, ps_to_tCK(80000, freq));
514 pctl_timing->tzqcsi = 10000; /* as used by Rockchip */
515 pctl_timing->tdqs = 1; /* fixed for DDR3 */
516 pctl_timing->tcksre = max(5u, ps_to_tCK(10000, freq));
517 pctl_timing->tcksrx = max(5u, ps_to_tCK(10000, freq));
518 pctl_timing->tcke = max(3u, ps_to_tCK(5000, freq));
519 pctl_timing->tmod = max(12u, ps_to_tCK(15000, freq));
520 pctl_timing->trstl = ns_to_tCK(100, freq);
521 pctl_timing->tzqcl = max(256u, ps_to_tCK(320000, freq)); /* tZQoper */
522 pctl_timing->tmrr = 0;
523 pctl_timing->tckesr = pctl_timing->tcke + 1; /* JESD-79: tCKE + 1tCK */
524 pctl_timing->tdpd = 0; /* RK3368 TRM: "allowed values for DDR3: 0" */
525
526
527 /*
528 * The controller can represent tFAW as 4x, 5x or 6x tRRD only.
529 * We want to use the smallest multiplier that satisfies the tFAW
530 * requirements of the given speed-bin. If necessary, we stretch out
531 * tRRD to allow us to operate on a 6x multiplier for tFAW.
532 */
533 tfaw_as_ps = 40000; /* 40ns: tFAW for DDR3-1600K, 2KB page-size */
534 if (tCK_to_ps(pctl_timing->trrd * 6, freq) < tfaw_as_ps) {
535 /* If tFAW is > 6 x tRRD, we need to stretch tRRD */
536 pctl_timing->trrd = ps_to_tCK(DIV_ROUND_UP(40000, 6), freq);
537 params->tfaw_mult = TFAW_TRRD_MULT6;
538 } else if (tCK_to_ps(pctl_timing->trrd * 5, freq) < tfaw_as_ps) {
539 params->tfaw_mult = TFAW_TRRD_MULT6;
540 } else if (tCK_to_ps(pctl_timing->trrd * 4, freq) < tfaw_as_ps) {
541 params->tfaw_mult = TFAW_TRRD_MULT5;
542 } else {
543 params->tfaw_mult = TFAW_TRRD_MULT4;
544 }
545
546 return 0;
547 }
548
pctl_cfg(struct rk3368_ddr_pctl * pctl,struct rk3368_sdram_params * params,struct rk3368_grf * grf)549 static void pctl_cfg(struct rk3368_ddr_pctl *pctl,
550 struct rk3368_sdram_params *params,
551 struct rk3368_grf *grf)
552 {
553 /* Configure PCTL timing registers */
554 params->pctl_timing.trefi |= BIT(31); /* see PCTL_TREFI */
555 copy_to_reg(&pctl->togcnt1u, ¶ms->pctl_timing.togcnt1u,
556 sizeof(params->pctl_timing));
557 writel(params->trefi_mem_ddr3, &pctl->trefi_mem_ddr3);
558
559 /* Set up ODT write selector and ODT write length */
560 writel((RANK0_ODT_WRITE_SEL | RANK1_ODT_WRITE_SEL), &pctl->dfiodtcfg);
561 writel(7 << ODT_LEN_BL8_W_SHIFT, &pctl->dfiodtcfg1);
562
563 /* Set up the CL/CWL-dependent timings of DFI */
564 writel((params->pctl_timing.tcl - 1) / 2 - 1, &pctl->dfitrddataen);
565 writel((params->pctl_timing.tcwl - 1) / 2 - 1, &pctl->dfitphywrlat);
566
567 /* DDR3 */
568 writel(params->tfaw_mult | DDR3_EN | DDR2_DDR3_BL_8, &pctl->mcfg);
569 writel(0x001c0004, &grf->ddrc0_con0);
570
571 setbits_le32(&pctl->scfg, HW_LOW_POWER_EN);
572 }
573
ddrphy_data_training(struct rk3368_ddr_pctl * pctl,struct rk3368_ddrphy * ddrphy)574 static int ddrphy_data_training(struct rk3368_ddr_pctl *pctl,
575 struct rk3368_ddrphy *ddrphy)
576 {
577 const u32 trefi = readl(&pctl->trefi);
578 const ulong timeout_ms = 500;
579 ulong tmp;
580
581 /* disable auto-refresh */
582 writel(0 | BIT(31), &pctl->trefi);
583
584 clrsetbits_le32(&ddrphy->reg[2], 0x33, 0x20);
585 clrsetbits_le32(&ddrphy->reg[2], 0x33, 0x21);
586
587 tmp = get_timer(0);
588 do {
589 if (get_timer(tmp) > timeout_ms) {
590 pr_err("%s: did not complete within %ld ms\n",
591 __func__, timeout_ms);
592 return -ETIME;
593 }
594 } while ((readl(&ddrphy->reg[0xff]) & 0xf) != 0xf);
595
596 send_command(pctl, MCMD_RANK0 | MCMD_RANK1, PREA_CMD);
597 clrsetbits_le32(&ddrphy->reg[2], 0x33, 0x20);
598 /* resume auto-refresh */
599 writel(trefi | BIT(31), &pctl->trefi);
600
601 return 0;
602 }
603
sdram_col_row_detect(struct udevice * dev)604 static int sdram_col_row_detect(struct udevice *dev)
605 {
606 struct dram_info *priv = dev_get_priv(dev);
607 struct rk3368_sdram_params *params = dev_get_plat(dev);
608 struct rk3368_ddr_pctl *pctl = priv->pctl;
609 struct rk3368_msch *msch = priv->msch;
610 const u32 test_pattern = 0x5aa5f00f;
611 int row, col;
612 uintptr_t addr;
613
614 move_to_config_state(pctl);
615 writel(6, &msch->ddrconf);
616 move_to_access_state(pctl);
617
618 /* Detect col */
619 for (col = 11; col >= 9; col--) {
620 writel(0, CONFIG_SYS_SDRAM_BASE);
621 addr = CONFIG_SYS_SDRAM_BASE +
622 (1 << (col + params->chan.bw - 1));
623 writel(test_pattern, addr);
624 if ((readl(addr) == test_pattern) &&
625 (readl(CONFIG_SYS_SDRAM_BASE) == 0))
626 break;
627 }
628
629 if (col == 8) {
630 pr_err("%s: col detect error\n", __func__);
631 return -EINVAL;
632 }
633
634 move_to_config_state(pctl);
635 writel(15, &msch->ddrconf);
636 move_to_access_state(pctl);
637
638 /* Detect row*/
639 for (row = 16; row >= 12; row--) {
640 writel(0, CONFIG_SYS_SDRAM_BASE);
641 addr = CONFIG_SYS_SDRAM_BASE + (1 << (row + 15 - 1));
642 writel(test_pattern, addr);
643 if ((readl(addr) == test_pattern) &&
644 (readl(CONFIG_SYS_SDRAM_BASE) == 0))
645 break;
646 }
647
648 if (row == 11) {
649 pr_err("%s: row detect error\n", __func__);
650 return -EINVAL;
651 }
652
653 /* Record results */
654 debug("%s: col %d, row %d\n", __func__, col, row);
655 params->chan.col = col;
656 params->chan.cs0_row = row;
657 params->chan.cs1_row = row;
658 params->chan.row_3_4 = 0;
659
660 return 0;
661 }
662
msch_niu_config(struct rk3368_msch * msch,struct rk3368_sdram_params * params)663 static int msch_niu_config(struct rk3368_msch *msch,
664 struct rk3368_sdram_params *params)
665 {
666 int i;
667 const u8 cols = params->chan.col - ((params->chan.bw == 2) ? 0 : 1);
668 const u8 rows = params->chan.cs0_row;
669
670 /*
671 * The DDR address-translation table always assumes a 32bit
672 * bus and the comparison below takes care of adjusting for
673 * a 16bit bus (i.e. one column-address is consumed).
674 */
675 const struct {
676 u8 rows;
677 u8 columns;
678 u8 type;
679 } ddrconf_table[] = {
680 /*
681 * C-B-R-D patterns are first. For these we require an
682 * exact match for the columns and rows (as there's
683 * one entry per possible configuration).
684 */
685 [0] = { .rows = 13, .columns = 10, .type = DMC_MSCH_CBRD },
686 [1] = { .rows = 14, .columns = 10, .type = DMC_MSCH_CBRD },
687 [2] = { .rows = 15, .columns = 10, .type = DMC_MSCH_CBRD },
688 [3] = { .rows = 16, .columns = 10, .type = DMC_MSCH_CBRD },
689 [4] = { .rows = 14, .columns = 11, .type = DMC_MSCH_CBRD },
690 [5] = { .rows = 15, .columns = 11, .type = DMC_MSCH_CBRD },
691 [6] = { .rows = 16, .columns = 11, .type = DMC_MSCH_CBRD },
692 [7] = { .rows = 13, .columns = 9, .type = DMC_MSCH_CBRD },
693 [8] = { .rows = 14, .columns = 9, .type = DMC_MSCH_CBRD },
694 [9] = { .rows = 15, .columns = 9, .type = DMC_MSCH_CBRD },
695 [10] = { .rows = 16, .columns = 9, .type = DMC_MSCH_CBRD },
696 /*
697 * 11 through 13 are C-R-B-D patterns. These are
698 * matched for an exact number of columns and to
699 * ensure that the hardware uses at least as many rows
700 * as the pattern requires (i.e. we make sure that
701 * there's no gaps up until we hit the device/chip-select;
702 * however, these patterns can accept up to 16 rows,
703 * as the row-address continues right after the CS
704 * switching)
705 */
706 [11] = { .rows = 15, .columns = 10, .type = DMC_MSCH_CRBD },
707 [12] = { .rows = 14, .columns = 11, .type = DMC_MSCH_CRBD },
708 [13] = { .rows = 13, .columns = 10, .type = DMC_MSCH_CRBD },
709 /*
710 * 14 and 15 are catch-all variants using a C-B-D-R
711 * scheme (i.e. alternating the chip-select every time
712 * C-B overflows) and stuffing the remaining C-bits
713 * into the top. Matching needs to make sure that the
714 * number of columns is either an exact match (i.e. we
715 * can use less the the maximum number of rows) -or-
716 * that the columns exceed what is given in this table
717 * and the rows are an exact match (in which case the
718 * remaining C-bits will be stuffed onto the top after
719 * the device/chip-select switches).
720 */
721 [14] = { .rows = 16, .columns = 10, .type = DMC_MSCH_CBDR },
722 [15] = { .rows = 16, .columns = 9, .type = DMC_MSCH_CBDR },
723 };
724
725 /*
726 * For C-B-R-D, we need an exact match (i.e. both for the number of
727 * columns and rows), while for C-B-D-R, only the the number of
728 * columns needs to match.
729 */
730 for (i = 0; i < ARRAY_SIZE(ddrconf_table); i++) {
731 bool match = false;
732
733 /* If this entry if for a different matcher, then skip it */
734 if (ddrconf_table[i].type != params->memory_schedule)
735 continue;
736
737 /*
738 * Match according to the rules (exact/inexact/at-least)
739 * documented in the ddrconf_table above.
740 */
741 switch (params->memory_schedule) {
742 case DMC_MSCH_CBRD:
743 match = (ddrconf_table[i].columns == cols) &&
744 (ddrconf_table[i].rows == rows);
745 break;
746
747 case DMC_MSCH_CRBD:
748 match = (ddrconf_table[i].columns == cols) &&
749 (ddrconf_table[i].rows <= rows);
750 break;
751
752 case DMC_MSCH_CBDR:
753 match = (ddrconf_table[i].columns == cols) ||
754 ((ddrconf_table[i].columns <= cols) &&
755 (ddrconf_table[i].rows == rows));
756 break;
757
758 default:
759 break;
760 }
761
762 if (match) {
763 debug("%s: setting ddrconf 0x%x\n", __func__, i);
764 writel(i, &msch->ddrconf);
765 return 0;
766 }
767 }
768
769 pr_err("%s: ddrconf (NIU config) not found\n", __func__);
770 return -EINVAL;
771 }
772
dram_all_config(struct udevice * dev)773 static void dram_all_config(struct udevice *dev)
774 {
775 struct dram_info *priv = dev_get_priv(dev);
776 struct rk3368_pmu_grf *pmugrf = priv->pmugrf;
777 struct rk3368_sdram_params *params = dev_get_plat(dev);
778 const struct rk3288_sdram_channel *info = ¶ms->chan;
779 u32 sys_reg = 0;
780 const int chan = 0;
781
782 sys_reg |= DDR3 << SYS_REG_DDRTYPE_SHIFT;
783 sys_reg |= 0 << SYS_REG_NUM_CH_SHIFT;
784
785 sys_reg |= info->row_3_4 << SYS_REG_ROW_3_4_SHIFT(chan);
786 sys_reg |= 1 << SYS_REG_CHINFO_SHIFT(chan);
787 sys_reg |= (info->rank - 1) << SYS_REG_RANK_SHIFT(chan);
788 sys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(chan);
789 sys_reg |= info->bk == 3 ? 0 : 1 << SYS_REG_BK_SHIFT(chan);
790 sys_reg |= (info->cs0_row - 13) << SYS_REG_CS0_ROW_SHIFT(chan);
791 sys_reg |= (info->cs1_row - 13) << SYS_REG_CS1_ROW_SHIFT(chan);
792 sys_reg |= (2 >> info->bw) << SYS_REG_BW_SHIFT(chan);
793 sys_reg |= (2 >> info->dbw) << SYS_REG_DBW_SHIFT(chan);
794
795 writel(sys_reg, &pmugrf->os_reg[2]);
796 }
797
setup_sdram(struct udevice * dev)798 static int setup_sdram(struct udevice *dev)
799 {
800 struct dram_info *priv = dev_get_priv(dev);
801 struct rk3368_sdram_params *params = dev_get_plat(dev);
802
803 struct rk3368_ddr_pctl *pctl = priv->pctl;
804 struct rk3368_ddrphy *ddrphy = priv->phy;
805 struct rk3368_cru *cru = priv->cru;
806 struct rk3368_grf *grf = priv->grf;
807 struct rk3368_msch *msch = priv->msch;
808
809 int ret;
810
811 /* The input clock (i.e. DPLL) needs to be 2x the DRAM frequency */
812 ret = clk_set_rate(&priv->ddr_clk, 2 * params->ddr_freq);
813 if (ret < 0) {
814 debug("%s: could not set DDR clock: %d\n", __func__, ret);
815 return ret;
816 }
817
818 /* Update the read-latency for the RK3368 */
819 writel(0x32, &msch->readlatency);
820
821 /* Initialise the DDR PCTL and DDR PHY */
822 ddrctl_reset(cru);
823 ddrphy_reset(ddrphy);
824 ddrphy_config_delays(ddrphy, params->ddr_freq);
825 dfi_cfg(pctl);
826 /* Configure relative system information of grf_ddrc0_con0 register */
827 ddr_set_ddr3_mode(grf, true);
828 ddr_set_noc_spr_err_stall(grf, true);
829 /* Calculate timings */
830 pctl_calc_timings(params, params->ddr_freq);
831 /* Initialise the device timings in protocol controller */
832 pctl_cfg(pctl, params, grf);
833 /* Configure AL, CL ... information of PHY registers */
834 ddrphy_config(ddrphy,
835 params->pctl_timing.tcl,
836 params->pctl_timing.tal,
837 params->pctl_timing.tcwl);
838
839 /* Initialize DRAM and configure with mode-register values */
840 ret = memory_init(pctl, params);
841 if (ret)
842 goto error;
843
844 move_to_config_state(pctl);
845 /* Perform data-training */
846 ddrphy_data_training(pctl, ddrphy);
847 move_to_access_state(pctl);
848
849 /* TODO(prt): could detect rank in training... */
850 #ifdef CONFIG_TARGET_EVB_PX5
851 params->chan.rank = 1;
852 #else
853 params->chan.rank = 2;
854 #endif
855 /* TODO(prt): bus width is not auto-detected (yet)... */
856 params->chan.bw = 2; /* 32bit wide bus */
857 params->chan.dbw = params->chan.dbw; /* 32bit wide bus */
858
859 /* DDR3 is always 8 bank */
860 params->chan.bk = 3;
861 /* Detect col and row number */
862 ret = sdram_col_row_detect(dev);
863 if (ret)
864 goto error;
865
866 /* Configure NIU DDR configuration */
867 ret = msch_niu_config(msch, params);
868 if (ret)
869 goto error;
870
871 /* set up OS_REG to communicate w/ next stage and OS */
872 dram_all_config(dev);
873
874 return 0;
875
876 error:
877 printf("DRAM init failed!\n");
878 hang();
879 }
880 #endif
881
rk3368_dmc_of_to_plat(struct udevice * dev)882 static int rk3368_dmc_of_to_plat(struct udevice *dev)
883 {
884 int ret = 0;
885
886 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
887 struct rk3368_sdram_params *plat = dev_get_plat(dev);
888
889 ret = regmap_init_mem(dev_ofnode(dev), &plat->map);
890 if (ret)
891 return ret;
892 #endif
893
894 return ret;
895 }
896
897 #if CONFIG_IS_ENABLED(OF_PLATDATA)
conv_of_plat(struct udevice * dev)898 static int conv_of_plat(struct udevice *dev)
899 {
900 struct rk3368_sdram_params *plat = dev_get_plat(dev);
901 struct dtd_rockchip_rk3368_dmc *of_plat = &plat->of_plat;
902
903 plat->ddr_freq = of_plat->rockchip_ddr_frequency;
904 plat->ddr_speed_bin = of_plat->rockchip_ddr_speed_bin;
905 plat->memory_schedule = of_plat->rockchip_memory_schedule;
906
907 return 0;
908 }
909 #endif
910
rk3368_dmc_probe(struct udevice * dev)911 static int rk3368_dmc_probe(struct udevice *dev)
912 {
913 #ifdef CONFIG_TPL_BUILD
914 struct rk3368_sdram_params *plat = dev_get_plat(dev);
915 struct rk3368_ddr_pctl *pctl;
916 struct rk3368_ddrphy *ddrphy;
917 struct rk3368_cru *cru;
918 struct rk3368_grf *grf;
919 struct rk3368_msch *msch;
920 int ret;
921 struct udevice *dev_clk;
922 #endif
923 struct dram_info *priv = dev_get_priv(dev);
924
925 #if CONFIG_IS_ENABLED(OF_PLATDATA)
926 ret = conv_of_plat(dev);
927 if (ret)
928 return ret;
929 #endif
930
931 priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
932 debug("%s: pmugrf=%p\n", __func__, priv->pmugrf);
933
934 #ifdef CONFIG_TPL_BUILD
935 pctl = (struct rk3368_ddr_pctl *)plat->of_plat.reg[0];
936 ddrphy = (struct rk3368_ddrphy *)plat->of_plat.reg[2];
937 msch = syscon_get_first_range(ROCKCHIP_SYSCON_MSCH);
938 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
939
940 priv->pctl = pctl;
941 priv->phy = ddrphy;
942 priv->msch = msch;
943 priv->grf = grf;
944
945 ret = rockchip_get_clk(&dev_clk);
946 if (ret)
947 return ret;
948 priv->ddr_clk.id = CLK_DDR;
949 ret = clk_request(dev_clk, &priv->ddr_clk);
950 if (ret)
951 return ret;
952
953 cru = rockchip_get_cru();
954 priv->cru = cru;
955 if (IS_ERR(priv->cru))
956 return PTR_ERR(priv->cru);
957
958 ret = setup_sdram(dev);
959 if (ret)
960 return ret;
961 #endif
962
963 priv->info.base = 0;
964 priv->info.size =
965 rockchip_sdram_size((phys_addr_t)&priv->pmugrf->os_reg[2]);
966
967 /*
968 * we use the 0x00000000~0xfdffffff space since 0xff000000~0xffffffff
969 * is SoC register space (i.e. reserved), and 0xfe000000~0xfeffffff is
970 * inaccessible for some IP controller.
971 */
972 priv->info.size = min(priv->info.size, (size_t)0xfe000000);
973
974 return 0;
975 }
976
rk3368_dmc_get_info(struct udevice * dev,struct ram_info * info)977 static int rk3368_dmc_get_info(struct udevice *dev, struct ram_info *info)
978 {
979 struct dram_info *priv = dev_get_priv(dev);
980
981 *info = priv->info;
982 return 0;
983 }
984
985 static struct ram_ops rk3368_dmc_ops = {
986 .get_info = rk3368_dmc_get_info,
987 };
988
989
990 static const struct udevice_id rk3368_dmc_ids[] = {
991 { .compatible = "rockchip,rk3368-dmc" },
992 { }
993 };
994
995 U_BOOT_DRIVER(rockchip_rk3368_dmc) = {
996 .name = "rockchip_rk3368_dmc",
997 .id = UCLASS_RAM,
998 .of_match = rk3368_dmc_ids,
999 .ops = &rk3368_dmc_ops,
1000 .probe = rk3368_dmc_probe,
1001 .priv_auto = sizeof(struct dram_info),
1002 .of_to_plat = rk3368_dmc_of_to_plat,
1003 .probe = rk3368_dmc_probe,
1004 .priv_auto = sizeof(struct dram_info),
1005 .plat_auto = sizeof(struct rk3368_sdram_params),
1006 };
1007