1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright(C) 2019
4 * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
5 */
6
7 #include <common.h>
8 #include <clk.h>
9 #include <clk-uclass.h>
10 #include <dm.h>
11 #include <log.h>
12 #include <asm/arch/clock.h>
13 #include <asm/arch/imx-regs.h>
14 #include <dt-bindings/clock/imxrt1050-clock.h>
15
16 #include "clk.h"
17
imxrt1050_clk_get_rate(struct clk * clk)18 static ulong imxrt1050_clk_get_rate(struct clk *clk)
19 {
20 struct clk *c;
21 int ret;
22
23 debug("%s(#%lu)\n", __func__, clk->id);
24
25 ret = clk_get_by_id(clk->id, &c);
26 if (ret)
27 return ret;
28
29 return clk_get_rate(c);
30 }
31
imxrt1050_clk_set_rate(struct clk * clk,ulong rate)32 static ulong imxrt1050_clk_set_rate(struct clk *clk, ulong rate)
33 {
34 struct clk *c;
35 int ret;
36
37 debug("%s(#%lu), rate: %lu\n", __func__, clk->id, rate);
38
39 ret = clk_get_by_id(clk->id, &c);
40 if (ret)
41 return ret;
42
43 return clk_set_rate(c, rate);
44 }
45
__imxrt1050_clk_enable(struct clk * clk,bool enable)46 static int __imxrt1050_clk_enable(struct clk *clk, bool enable)
47 {
48 struct clk *c;
49 int ret;
50
51 debug("%s(#%lu) en: %d\n", __func__, clk->id, enable);
52
53 ret = clk_get_by_id(clk->id, &c);
54 if (ret)
55 return ret;
56
57 if (enable)
58 ret = clk_enable(c);
59 else
60 ret = clk_disable(c);
61
62 return ret;
63 }
64
imxrt1050_clk_disable(struct clk * clk)65 static int imxrt1050_clk_disable(struct clk *clk)
66 {
67 return __imxrt1050_clk_enable(clk, 0);
68 }
69
imxrt1050_clk_enable(struct clk * clk)70 static int imxrt1050_clk_enable(struct clk *clk)
71 {
72 return __imxrt1050_clk_enable(clk, 1);
73 }
74
imxrt1050_clk_set_parent(struct clk * clk,struct clk * parent)75 static int imxrt1050_clk_set_parent(struct clk *clk, struct clk *parent)
76 {
77 struct clk *c, *cp;
78 int ret;
79
80 debug("%s(#%lu), parent: %lu\n", __func__, clk->id, parent->id);
81
82 ret = clk_get_by_id(clk->id, &c);
83 if (ret)
84 return ret;
85
86 ret = clk_get_by_id(parent->id, &cp);
87 if (ret)
88 return ret;
89
90 return clk_set_parent(c, cp);
91 }
92
93 static struct clk_ops imxrt1050_clk_ops = {
94 .set_rate = imxrt1050_clk_set_rate,
95 .get_rate = imxrt1050_clk_get_rate,
96 .enable = imxrt1050_clk_enable,
97 .disable = imxrt1050_clk_disable,
98 .set_parent = imxrt1050_clk_set_parent,
99 };
100
101 static const char * const pll_ref_sels[] = {"osc", "dummy", };
102 static const char * const pll1_bypass_sels[] = {"pll1_arm", "pll1_arm_ref_sel", };
103 static const char * const pll2_bypass_sels[] = {"pll2_sys", "pll2_sys_ref_sel", };
104 static const char * const pll3_bypass_sels[] = {"pll3_usb_otg", "pll3_usb_otg_ref_sel", };
105 static const char * const pll5_bypass_sels[] = {"pll5_video", "pll5_video_ref_sel", };
106
107 static const char *const pre_periph_sels[] = { "pll2_sys", "pll2_pfd2_396m", "pll2_pfd0_352m", "arm_podf", };
108 static const char *const periph_sels[] = { "pre_periph_sel", "todo", };
109 static const char *const usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", };
110 static const char *const lpuart_sels[] = { "pll3_80m", "osc", };
111 static const char *const semc_alt_sels[] = { "pll2_pfd2_396m", "pll3_pfd1_664_62m", };
112 static const char *const semc_sels[] = { "periph_sel", "semc_alt_sel", };
113 static const char *const lcdif_sels[] = { "pll2_sys", "pll3_pfd3_454_74m", "pll5_video", "pll2_pfd0_352m", "pll2_pfd1_594m", "pll3_pfd1_664_62m"};
114
imxrt1050_clk_probe(struct udevice * dev)115 static int imxrt1050_clk_probe(struct udevice *dev)
116 {
117 void *base;
118
119 /* Anatop clocks */
120 base = (void *)ANATOP_BASE_ADDR;
121
122 clk_dm(IMXRT1050_CLK_PLL1_REF_SEL,
123 imx_clk_mux("pll1_arm_ref_sel", base + 0x0, 14, 2,
124 pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
125 clk_dm(IMXRT1050_CLK_PLL2_REF_SEL,
126 imx_clk_mux("pll2_sys_ref_sel", base + 0x30, 14, 2,
127 pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
128 clk_dm(IMXRT1050_CLK_PLL3_REF_SEL,
129 imx_clk_mux("pll3_usb_otg_ref_sel", base + 0x10, 14, 2,
130 pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
131 clk_dm(IMXRT1050_CLK_PLL5_REF_SEL,
132 imx_clk_mux("pll5_video_ref_sel", base + 0xa0, 14, 2,
133 pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
134
135 clk_dm(IMXRT1050_CLK_PLL1_ARM,
136 imx_clk_pllv3(IMX_PLLV3_SYS, "pll1_arm", "pll1_arm_ref_sel",
137 base + 0x0, 0x7f));
138 clk_dm(IMXRT1050_CLK_PLL2_SYS,
139 imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_sys", "pll2_sys_ref_sel",
140 base + 0x30, 0x1));
141 clk_dm(IMXRT1050_CLK_PLL3_USB_OTG,
142 imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg",
143 "pll3_usb_otg_ref_sel",
144 base + 0x10, 0x1));
145 clk_dm(IMXRT1050_CLK_PLL5_VIDEO,
146 imx_clk_pllv3(IMX_PLLV3_AV, "pll5_video", "pll5_video_ref_sel",
147 base + 0xa0, 0x7f));
148
149 /* PLL bypass out */
150 clk_dm(IMXRT1050_CLK_PLL1_BYPASS,
151 imx_clk_mux_flags("pll1_bypass", base + 0x0, 16, 1,
152 pll1_bypass_sels,
153 ARRAY_SIZE(pll1_bypass_sels),
154 CLK_SET_RATE_PARENT));
155 clk_dm(IMXRT1050_CLK_PLL2_BYPASS,
156 imx_clk_mux_flags("pll2_bypass", base + 0x30, 16, 1,
157 pll2_bypass_sels,
158 ARRAY_SIZE(pll2_bypass_sels),
159 CLK_SET_RATE_PARENT));
160 clk_dm(IMXRT1050_CLK_PLL3_BYPASS,
161 imx_clk_mux_flags("pll3_bypass", base + 0x10, 16, 1,
162 pll3_bypass_sels,
163 ARRAY_SIZE(pll3_bypass_sels),
164 CLK_SET_RATE_PARENT));
165 clk_dm(IMXRT1050_CLK_PLL5_BYPASS,
166 imx_clk_mux_flags("pll5_bypass", base + 0xa0, 16, 1,
167 pll5_bypass_sels,
168 ARRAY_SIZE(pll5_bypass_sels),
169 CLK_SET_RATE_PARENT));
170
171 clk_dm(IMXRT1050_CLK_VIDEO_POST_DIV_SEL,
172 imx_clk_divider("video_post_div_sel", "pll5_video",
173 base + 0xa0, 19, 2));
174 clk_dm(IMXRT1050_CLK_VIDEO_DIV,
175 imx_clk_divider("video_div", "video_post_div_sel",
176 base + 0x170, 30, 2));
177
178 clk_dm(IMXRT1050_CLK_PLL3_80M,
179 imx_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6));
180
181 clk_dm(IMXRT1050_CLK_PLL2_PFD0_352M,
182 imx_clk_pfd("pll2_pfd0_352m", "pll2_sys", base + 0x100, 0));
183 clk_dm(IMXRT1050_CLK_PLL2_PFD1_594M,
184 imx_clk_pfd("pll2_pfd1_594m", "pll2_sys", base + 0x100, 1));
185 clk_dm(IMXRT1050_CLK_PLL2_PFD2_396M,
186 imx_clk_pfd("pll2_pfd2_396m", "pll2_sys", base + 0x100, 2));
187 clk_dm(IMXRT1050_CLK_PLL3_PFD1_664_62M,
188 imx_clk_pfd("pll3_pfd1_664_62m", "pll3_usb_otg", base + 0xf0,
189 1));
190 clk_dm(IMXRT1050_CLK_PLL3_PFD3_454_74M,
191 imx_clk_pfd("pll3_pfd3_454_74m", "pll3_usb_otg", base + 0xf0,
192 3));
193
194 /* CCM clocks */
195 base = dev_read_addr_ptr(dev);
196 if (base == (void *)FDT_ADDR_T_NONE)
197 return -EINVAL;
198
199 clk_dm(IMXRT1050_CLK_ARM_PODF,
200 imx_clk_divider("arm_podf", "pll1_arm",
201 base + 0x10, 0, 3));
202
203 clk_dm(IMXRT1050_CLK_PRE_PERIPH_SEL,
204 imx_clk_mux("pre_periph_sel", base + 0x18, 18, 2,
205 pre_periph_sels, ARRAY_SIZE(pre_periph_sels)));
206 clk_dm(IMXRT1050_CLK_PERIPH_SEL,
207 imx_clk_mux("periph_sel", base + 0x14, 25, 1,
208 periph_sels, ARRAY_SIZE(periph_sels)));
209 clk_dm(IMXRT1050_CLK_USDHC1_SEL,
210 imx_clk_mux("usdhc1_sel", base + 0x1c, 16, 1,
211 usdhc_sels, ARRAY_SIZE(usdhc_sels)));
212 clk_dm(IMXRT1050_CLK_USDHC2_SEL,
213 imx_clk_mux("usdhc2_sel", base + 0x1c, 17, 1,
214 usdhc_sels, ARRAY_SIZE(usdhc_sels)));
215 clk_dm(IMXRT1050_CLK_LPUART_SEL,
216 imx_clk_mux("lpuart_sel", base + 0x24, 6, 1,
217 lpuart_sels, ARRAY_SIZE(lpuart_sels)));
218 clk_dm(IMXRT1050_CLK_SEMC_ALT_SEL,
219 imx_clk_mux("semc_alt_sel", base + 0x14, 7, 1,
220 semc_alt_sels, ARRAY_SIZE(semc_alt_sels)));
221 clk_dm(IMXRT1050_CLK_SEMC_SEL,
222 imx_clk_mux("semc_sel", base + 0x14, 6, 1,
223 semc_sels, ARRAY_SIZE(semc_sels)));
224 clk_dm(IMXRT1050_CLK_LCDIF_SEL,
225 imx_clk_mux("lcdif_sel", base + 0x38, 15, 3,
226 lcdif_sels, ARRAY_SIZE(lcdif_sels)));
227
228 clk_dm(IMXRT1050_CLK_AHB_PODF,
229 imx_clk_divider("ahb_podf", "periph_sel",
230 base + 0x14, 10, 3));
231 clk_dm(IMXRT1050_CLK_USDHC1_PODF,
232 imx_clk_divider("usdhc1_podf", "usdhc1_sel",
233 base + 0x24, 11, 3));
234 clk_dm(IMXRT1050_CLK_USDHC2_PODF,
235 imx_clk_divider("usdhc2_podf", "usdhc2_sel",
236 base + 0x24, 16, 3));
237 clk_dm(IMXRT1050_CLK_LPUART_PODF,
238 imx_clk_divider("lpuart_podf", "lpuart_sel",
239 base + 0x24, 0, 6));
240 clk_dm(IMXRT1050_CLK_SEMC_PODF,
241 imx_clk_divider("semc_podf", "semc_sel",
242 base + 0x14, 16, 3));
243 clk_dm(IMXRT1050_CLK_LCDIF_PRED,
244 imx_clk_divider("lcdif_pred", "lcdif_sel",
245 base + 0x38, 12, 3));
246 clk_dm(IMXRT1050_CLK_LCDIF_PODF,
247 imx_clk_divider("lcdif_podf", "lcdif_pred",
248 base + 0x18, 23, 3));
249
250 clk_dm(IMXRT1050_CLK_USDHC1,
251 imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2));
252 clk_dm(IMXRT1050_CLK_USDHC2,
253 imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4));
254 clk_dm(IMXRT1050_CLK_LPUART1,
255 imx_clk_gate2("lpuart1", "lpuart_podf", base + 0x7c, 24));
256 clk_dm(IMXRT1050_CLK_SEMC,
257 imx_clk_gate2("semc", "semc_podf", base + 0x74, 4));
258 clk_dm(IMXRT1050_CLK_LCDIF_APB,
259 imx_clk_gate2("lcdif", "lcdif_podf", base + 0x70, 28));
260 clk_dm(IMXRT1050_CLK_LCDIF_PIX,
261 imx_clk_gate2("lcdif_pix", "lcdif", base + 0x74, 10));
262 clk_dm(IMXRT1050_CLK_USBOH3,
263 imx_clk_gate2("usboh3", "pll3_usb_otg", base + 0x80, 0));
264
265 struct clk *clk, *clk1;
266
267 #ifdef CONFIG_SPL_BUILD
268 /* bypass pll1 before setting its rate */
269 clk_get_by_id(IMXRT1050_CLK_PLL1_REF_SEL, &clk);
270 clk_get_by_id(IMXRT1050_CLK_PLL1_BYPASS, &clk1);
271 clk_set_parent(clk1, clk);
272
273 clk_get_by_id(IMXRT1050_CLK_PLL1_ARM, &clk);
274 clk_enable(clk);
275 clk_set_rate(clk, 1056000000UL);
276
277 clk_get_by_id(IMXRT1050_CLK_PLL1_BYPASS, &clk1);
278 clk_set_parent(clk1, clk);
279
280 clk_get_by_id(IMXRT1050_CLK_SEMC_SEL, &clk1);
281 clk_get_by_id(IMXRT1050_CLK_SEMC_ALT_SEL, &clk);
282 clk_set_parent(clk1, clk);
283
284 clk_get_by_id(IMXRT1050_CLK_PLL2_SYS, &clk);
285 clk_enable(clk);
286 clk_set_rate(clk, 528000000UL);
287
288 clk_get_by_id(IMXRT1050_CLK_PLL2_BYPASS, &clk1);
289 clk_set_parent(clk1, clk);
290
291 /* Configure PLL3_USB_OTG to 480MHz */
292 clk_get_by_id(IMXRT1050_CLK_PLL3_USB_OTG, &clk);
293 clk_enable(clk);
294 clk_set_rate(clk, 480000000UL);
295
296 clk_get_by_id(IMXRT1050_CLK_PLL3_BYPASS, &clk1);
297 clk_set_parent(clk1, clk);
298 #else
299 /* Set PLL5 for LCDIF to its default 650Mhz */
300 clk_get_by_id(IMXRT1050_CLK_PLL5_VIDEO, &clk);
301 clk_enable(clk);
302 clk_set_rate(clk, 650000000UL);
303
304 clk_get_by_id(IMXRT1050_CLK_PLL5_BYPASS, &clk1);
305 clk_set_parent(clk1, clk);
306 #endif
307
308 return 0;
309 }
310
311 static const struct udevice_id imxrt1050_clk_ids[] = {
312 { .compatible = "fsl,imxrt1050-ccm" },
313 { },
314 };
315
316 U_BOOT_DRIVER(imxrt1050_clk) = {
317 .name = "clk_imxrt1050",
318 .id = UCLASS_CLK,
319 .of_match = imxrt1050_clk_ids,
320 .ops = &imxrt1050_clk_ops,
321 .probe = imxrt1050_clk_probe,
322 .flags = DM_FLAG_PRE_RELOC,
323 };
324