1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * K2L: SoC definitions 4 * 5 * (C) Copyright 2012-2014 6 * Texas Instruments Incorporated, <www.ti.com> 7 */ 8 9 #ifndef __ASM_ARCH_HARDWARE_K2L_H 10 #define __ASM_ARCH_HARDWARE_K2L_H 11 12 #ifndef __ASSEMBLY__ 13 #include <linux/bitops.h> 14 #endif 15 16 #define KS2_ARM_PLL_EN BIT(13) 17 18 /* PA SS Registers */ 19 #define KS2_PASS_BASE 0x26000000 20 21 /* Power and Sleep Controller (PSC) Domains */ 22 #define KS2_LPSC_MOD 0 23 #define KS2_LPSC_DFE_IQN_SYS 1 24 #define KS2_LPSC_USB 2 25 #define KS2_LPSC_EMIF25_SPI 3 26 #define KS2_LPSC_TSIP 4 27 #define KS2_LPSC_DEBUGSS_TRC 5 28 #define KS2_LPSC_TETB_TRC 6 29 #define KS2_LPSC_PKTPROC 7 30 #define KS2_LPSC_PA KS2_LPSC_PKTPROC 31 #define KS2_LPSC_SGMII 8 32 #define KS2_LPSC_CPGMAC KS2_LPSC_SGMII 33 #define KS2_LPSC_CRYPTO 9 34 #define KS2_LPSC_PCIE0 10 35 #define KS2_LPSC_PCIE1 11 36 #define KS2_LPSC_JESD_MISC 12 37 #define KS2_LPSC_CHIP_SRSS 13 38 #define KS2_LPSC_MSMC 14 39 #define KS2_LPSC_GEM_1 16 40 #define KS2_LPSC_GEM_2 17 41 #define KS2_LPSC_GEM_3 18 42 #define KS2_LPSC_EMIF4F_DDR3 23 43 #define KS2_LPSC_TAC 25 44 #define KS2_LPSC_RAC 26 45 #define KS2_LPSC_DDUC4X_CFR2X_BB 27 46 #define KS2_LPSC_FFTC_A 28 47 #define KS2_LPSC_OSR 34 48 #define KS2_LPSC_TCP3D_0 35 49 #define KS2_LPSC_TCP3D_1 37 50 #define KS2_LPSC_VCP2X4_A 39 51 #define KS2_LPSC_VCP2X4_B 40 52 #define KS2_LPSC_VCP2X4_C 41 53 #define KS2_LPSC_VCP2X4_D 42 54 #define KS2_LPSC_BCP 47 55 #define KS2_LPSC_DPD4X 48 56 #define KS2_LPSC_FFTC_B 49 57 #define KS2_LPSC_IQN_AIL 50 58 59 /* Chip Interrupt Controller */ 60 #define KS2_CIC2_DDR3_ECC_IRQ_NUM 0x0D3 61 #define KS2_CIC2_DDR3_ECC_CHAN_NUM 0x01D 62 63 /* OSR */ 64 #define KS2_OSR_DATA_BASE 0x70000000 /* OSR data base */ 65 #define KS2_OSR_CFG_BASE 0x02348c00 /* OSR config base */ 66 #define KS2_OSR_ECC_VEC 0x08 /* ECC Vector reg */ 67 #define KS2_OSR_ECC_CTRL 0x14 /* ECC control reg */ 68 69 /* OSR ECC Vector register */ 70 #define KS2_OSR_ECC_VEC_TRIG_RD BIT(15) /* trigger a read op */ 71 #define KS2_OSR_ECC_VEC_RD_DONE BIT(24) /* read complete */ 72 73 #define KS2_OSR_ECC_VEC_RAM_ID_SH 0 /* RAM ID shift */ 74 #define KS2_OSR_ECC_VEC_RD_ADDR_SH 16 /* read address shift */ 75 76 /* OSR ECC control register */ 77 #define KS2_OSR_ECC_CTRL_EN BIT(0) /* ECC enable bit */ 78 #define KS2_OSR_ECC_CTRL_CHK BIT(1) /* ECC check bit */ 79 #define KS2_OSR_ECC_CTRL_RMW BIT(2) /* ECC check bit */ 80 81 /* Number of OSR RAM banks */ 82 #define KS2_OSR_NUM_RAM_BANKS 4 83 84 /* OSR memory size */ 85 #define KS2_OSR_SIZE 0x100000 86 87 /* SGMII SerDes */ 88 #define KS2_SGMII_SERDES2_BASE 0x02320000 89 #define KS2_LANES_PER_SGMII_SERDES 2 90 91 /* Number of DSP cores */ 92 #define KS2_NUM_DSPS 4 93 94 /* NETCP pktdma */ 95 #define KS2_NETCP_PDMA_CTRL_BASE 0x26186000 96 #define KS2_NETCP_PDMA_TX_BASE 0x26187000 97 #define KS2_NETCP_PDMA_TX_CH_NUM 21 98 #define KS2_NETCP_PDMA_RX_BASE 0x26188000 99 #define KS2_NETCP_PDMA_RX_CH_NUM 91 100 #define KS2_NETCP_PDMA_SCHED_BASE 0x26186100 101 #define KS2_NETCP_PDMA_RX_FLOW_BASE 0x26189000 102 #define KS2_NETCP_PDMA_RX_FLOW_NUM 96 103 #define KS2_NETCP_PDMA_TX_SND_QUEUE 896 104 105 /* NETCP */ 106 #define KS2_NETCP_BASE 0x26000000 107 108 #ifndef __ASSEMBLY__ ddr3_get_size(void)109static inline int ddr3_get_size(void) 110 { 111 return 2; 112 } 113 #endif 114 115 #endif /* __ASM_ARCH_HARDWARE_K2L_H */ 116