1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2012 Altera Corporation <www.altera.com>
4 */
5
6 #include <common.h>
7 #include <hang.h>
8 #include <init.h>
9 #include <log.h>
10 #include <asm/global_data.h>
11 #include <asm/io.h>
12 #include <asm/u-boot.h>
13 #include <asm/utils.h>
14 #include <image.h>
15 #include <asm/arch/reset_manager.h>
16 #include <spl.h>
17 #include <asm/arch/system_manager.h>
18 #include <asm/arch/freeze_controller.h>
19 #include <asm/arch/clock_manager.h>
20 #include <asm/arch/misc.h>
21 #include <asm/arch/scan_manager.h>
22 #include <asm/arch/sdram.h>
23 #include <asm/sections.h>
24 #include <debug_uart.h>
25 #include <fdtdec.h>
26 #include <watchdog.h>
27 #include <dm/uclass.h>
28 #include <linux/bitops.h>
29
30 DECLARE_GLOBAL_DATA_PTR;
31
spl_boot_device(void)32 u32 spl_boot_device(void)
33 {
34 const u32 bsel = readl(socfpga_get_sysmgr_addr() +
35 SYSMGR_GEN5_BOOTINFO);
36
37 switch (SYSMGR_GET_BOOTINFO_BSEL(bsel)) {
38 case 0x1: /* FPGA (HPS2FPGA Bridge) */
39 return BOOT_DEVICE_RAM;
40 case 0x2: /* NAND Flash (1.8V) */
41 case 0x3: /* NAND Flash (3.0V) */
42 return BOOT_DEVICE_NAND;
43 case 0x4: /* SD/MMC External Transceiver (1.8V) */
44 case 0x5: /* SD/MMC Internal Transceiver (3.0V) */
45 return BOOT_DEVICE_MMC1;
46 case 0x6: /* QSPI Flash (1.8V) */
47 case 0x7: /* QSPI Flash (3.0V) */
48 return BOOT_DEVICE_SPI;
49 default:
50 printf("Invalid boot device (bsel=%08x)!\n", bsel);
51 hang();
52 }
53 }
54
55 #ifdef CONFIG_SPL_MMC_SUPPORT
spl_mmc_boot_mode(const u32 boot_device)56 u32 spl_mmc_boot_mode(const u32 boot_device)
57 {
58 #if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
59 return MMCSD_MODE_FS;
60 #else
61 return MMCSD_MODE_RAW;
62 #endif
63 }
64 #endif
65
board_init_f(ulong dummy)66 void board_init_f(ulong dummy)
67 {
68 const struct cm_config *cm_default_cfg = cm_get_default_config();
69 unsigned long reg;
70 int ret;
71 struct udevice *dev;
72
73 ret = spl_early_init();
74 if (ret)
75 hang();
76
77 socfpga_get_managers_addr();
78
79 /*
80 * Clear fake OCRAM ECC first as SBE
81 * and DBE might triggered during power on
82 */
83 reg = readl(socfpga_get_sysmgr_addr() + SYSMGR_GEN5_ECCGRP_OCRAM);
84 if (reg & SYSMGR_ECC_OCRAM_SERR)
85 writel(SYSMGR_ECC_OCRAM_SERR | SYSMGR_ECC_OCRAM_EN,
86 socfpga_get_sysmgr_addr() + SYSMGR_GEN5_ECCGRP_OCRAM);
87 if (reg & SYSMGR_ECC_OCRAM_DERR)
88 writel(SYSMGR_ECC_OCRAM_DERR | SYSMGR_ECC_OCRAM_EN,
89 socfpga_get_sysmgr_addr() + SYSMGR_GEN5_ECCGRP_OCRAM);
90
91 socfpga_sdram_remap_zero();
92 socfpga_pl310_clear();
93
94 debug("Freezing all I/O banks\n");
95 /* freeze all IO banks */
96 sys_mgr_frzctrl_freeze_req();
97
98 /* Put everything into reset but L4WD0. */
99 socfpga_per_reset_all();
100
101 if (!socfpga_is_booting_from_fpga()) {
102 /* Put FPGA bridges into reset too. */
103 socfpga_bridges_reset(1);
104 }
105
106 socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0);
107 timer_init();
108
109 debug("Reconfigure Clock Manager\n");
110 /* reconfigure the PLLs */
111 if (cm_basic_init(cm_default_cfg))
112 hang();
113
114 /* Enable bootrom to configure IOs. */
115 sysmgr_config_warmrstcfgio(1);
116
117 /* configure the IOCSR / IO buffer settings */
118 if (scan_mgr_configure_iocsr())
119 hang();
120
121 sysmgr_config_warmrstcfgio(0);
122
123 /* configure the pin muxing through system manager */
124 sysmgr_config_warmrstcfgio(1);
125 sysmgr_pinmux_init();
126 sysmgr_config_warmrstcfgio(0);
127
128 /* Set bridges handoff value */
129 socfpga_bridges_set_handoff_regs(true, true, true);
130
131 debug("Unfreezing/Thaw all I/O banks\n");
132 /* unfreeze / thaw all IO banks */
133 sys_mgr_frzctrl_thaw_req();
134
135 #ifdef CONFIG_DEBUG_UART
136 socfpga_per_reset(SOCFPGA_RESET(UART0), 0);
137 debug_uart_init();
138 #endif
139
140 ret = uclass_get_device(UCLASS_RESET, 0, &dev);
141 if (ret)
142 debug("Reset init failed: %d\n", ret);
143
144 #ifdef CONFIG_SPL_NAND_DENALI
145 clrbits_le32(SOCFPGA_RSTMGR_ADDRESS + RSTMGR_GEN5_PERMODRST, BIT(4));
146 #endif
147
148 /* enable console uart printing */
149 preloader_console_init();
150
151 ret = uclass_get_device(UCLASS_RAM, 0, &dev);
152 if (ret) {
153 debug("DRAM init failed: %d\n", ret);
154 hang();
155 }
156 }
157