1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (c) 2020, Cortina Access Inc..
4 */
5
6 #include <common.h>
7 #include <linux/delay.h>
8 #include <linux/bitops.h>
9 #include <linux/sizes.h>
10 #include <log.h>
11 #include <asm/io.h>
12 #include <memalign.h>
13 #include <nand.h>
14 #include <dm/device_compat.h>
15 #include <linux/bug.h>
16 #include <linux/delay.h>
17 #include <linux/iopoll.h>
18 #include <linux/errno.h>
19 #include <asm/gpio.h>
20 #include <fdtdec.h>
21 #include <bouncebuf.h>
22 #include <dm.h>
23 #include "cortina_nand.h"
24
25 static unsigned int *pread, *pwrite;
26
27 static const struct udevice_id cortina_nand_dt_ids[] = {
28 {
29 .compatible = "cortina,ca-nand",
30 },
31 { /* sentinel */ }
32 };
33
34 static struct nand_ecclayout eccoob;
35
36 /* Information about an attached NAND chip */
37 struct fdt_nand {
38 int enabled; /* 1 to enable, 0 to disable */
39 s32 width; /* bit width, must be 8 */
40 u32 nand_ecc_strength;
41 };
42
43 struct nand_drv {
44 u32 fifo_index;
45 struct nand_ctlr *reg;
46 struct dma_global *dma_glb;
47 struct dma_ssp *dma_nand;
48 struct tx_descriptor_t *tx_desc;
49 struct rx_descriptor_t *rx_desc;
50 struct fdt_nand config;
51 unsigned int flash_base;
52 };
53
54 struct ca_nand_info {
55 struct udevice *dev;
56 struct nand_drv nand_ctrl;
57 struct nand_chip nand_chip;
58 };
59
60 /**
61 * Wait for command completion
62 *
63 * @param reg nand_ctlr structure
64 * @return
65 * 1 - Command completed
66 * 0 - Timeout
67 */
nand_waitfor_cmd_completion(struct nand_ctlr * reg,unsigned int mask)68 static int nand_waitfor_cmd_completion(struct nand_ctlr *reg, unsigned int mask)
69 {
70 unsigned int reg_v = 0;
71
72 if (readl_poll_timeout(®->flash_flash_access_start, reg_v,
73 !(reg_v & mask), (FLASH_LONG_DELAY << 2))) {
74 pr_err("Nand CMD timeout!\n");
75 return 0;
76 }
77
78 return 1;
79 }
80
81 /**
82 * Read one byte from the chip
83 *
84 * @param mtd MTD device structure
85 * @return data byte
86 *
87 * Read function for 8bit bus-width
88 */
read_byte(struct mtd_info * mtd)89 static uint8_t read_byte(struct mtd_info *mtd)
90 {
91 struct nand_chip *chip = mtd_to_nand(mtd);
92 struct nand_drv *info;
93 u8 ret_v;
94
95 info = (struct nand_drv *)nand_get_controller_data(chip);
96
97 clrsetbits_le32(&info->reg->flash_flash_access_start, GENMASK(31, 0),
98 NFLASH_GO | NFLASH_RD);
99
100 if (!nand_waitfor_cmd_completion(info->reg, NFLASH_GO))
101 printf("%s: Command timeout\n", __func__);
102
103 ret_v = readl(&info->reg->flash_nf_data) >> (8 * info->fifo_index++);
104 info->fifo_index %= 4;
105
106 return (uint8_t)ret_v;
107 }
108
109 /**
110 * Read len bytes from the chip into a buffer
111 *
112 * @param mtd MTD device structure
113 * @param buf buffer to store data to
114 * @param len number of bytes to read
115 *
116 * Read function for 8bit bus-width
117 */
read_buf(struct mtd_info * mtd,uint8_t * buf,int len)118 static void read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
119 {
120 int i;
121 unsigned int reg;
122 struct nand_chip *chip = mtd_to_nand(mtd);
123 struct nand_drv *info =
124 (struct nand_drv *)nand_get_controller_data(chip);
125
126 for (i = 0; i < len; i++) {
127 clrsetbits_le32(&info->reg->flash_flash_access_start,
128 GENMASK(31, 0), NFLASH_GO | NFLASH_RD);
129
130 if (!nand_waitfor_cmd_completion(info->reg, NFLASH_GO))
131 printf("%s: Command timeout\n", __func__);
132
133 reg = readl(&info->reg->flash_nf_data) >>
134 (8 * info->fifo_index++);
135 memcpy(buf + i, ®, 1);
136 info->fifo_index %= 4;
137 }
138 }
139
140 /**
141 * Check READY pin status to see if it is ready or not
142 *
143 * @param mtd MTD device structure
144 * @return
145 * 1 - ready
146 * 0 - not ready
147 */
nand_dev_ready(struct mtd_info * mtd)148 static int nand_dev_ready(struct mtd_info *mtd)
149 {
150 struct nand_chip *chip = mtd_to_nand(mtd);
151 int reg_val;
152 struct nand_drv *info =
153 (struct nand_drv *)nand_get_controller_data(chip);
154
155 reg_val = readl(&info->reg->flash_status);
156 if (reg_val & NFLASH_READY)
157 return 1;
158 else
159 return 0;
160 }
161
162 /* Dummy implementation: we don't support multiple chips */
nand_select_chip(struct mtd_info * mtd,int chipnr)163 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
164 {
165 switch (chipnr) {
166 case -1:
167 case 0:
168 break;
169
170 default:
171 WARN_ON(chipnr);
172 }
173 }
174
init_nand_dma(struct nand_chip * nand)175 int init_nand_dma(struct nand_chip *nand)
176 {
177 int i;
178 struct nand_drv *info =
179 (struct nand_drv *)nand_get_controller_data(nand);
180
181 setbits_le32(&info->dma_glb->dma_glb_dma_lso_ctrl, TX_DMA_ENABLE);
182 setbits_le32(&info->dma_glb->dma_glb_dma_ssp_rx_ctrl,
183 TX_DMA_ENABLE | DMA_CHECK_OWNER);
184 setbits_le32(&info->dma_glb->dma_glb_dma_ssp_tx_ctrl,
185 RX_DMA_ENABLE | DMA_CHECK_OWNER);
186
187 info->tx_desc = malloc_cache_aligned((sizeof(struct tx_descriptor_t) *
188 CA_DMA_DESC_NUM));
189 info->rx_desc = malloc_cache_aligned((sizeof(struct rx_descriptor_t) *
190 CA_DMA_DESC_NUM));
191
192 if (!info->rx_desc && info->tx_desc) {
193 printf("Fail to alloc DMA descript!\n");
194 kfree(info->tx_desc);
195 return -ENOMEM;
196 } else if (info->rx_desc && !info->tx_desc) {
197 printf("Fail to alloc DMA descript!\n");
198 kfree(info->tx_desc);
199 return -ENOMEM;
200 }
201
202 /* set RX DMA base address and depth */
203 clrsetbits_le32(&info->dma_nand->dma_q_rxq_base_depth,
204 GENMASK(31, 4), (uintptr_t)info->rx_desc);
205 clrsetbits_le32(&info->dma_nand->dma_q_rxq_base_depth,
206 GENMASK(3, 0), CA_DMA_DEPTH);
207
208 /* set TX DMA base address and depth */
209 clrsetbits_le32(&info->dma_nand->dma_q_txq_base_depth,
210 GENMASK(31, 4), (uintptr_t)info->tx_desc);
211 clrsetbits_le32(&info->dma_nand->dma_q_txq_base_depth,
212 GENMASK(3, 0), CA_DMA_DEPTH);
213
214 memset((unsigned char *)info->tx_desc, 0,
215 (sizeof(struct tx_descriptor_t) * CA_DMA_DESC_NUM));
216 memset((unsigned char *)info->rx_desc, 0,
217 (sizeof(struct rx_descriptor_t) * CA_DMA_DESC_NUM));
218
219 for (i = 0; i < CA_DMA_DESC_NUM; i++) {
220 /* set owner bit as SW */
221 info->tx_desc[i].own = 1;
222 /* enable Scatter-Gather memory copy */
223 info->tx_desc[i].sgm = 0x1;
224 }
225
226 return 0;
227 }
228
229 /**
230 * Send command to NAND device
231 *
232 * @param mtd MTD device structure
233 * @param command the command to be sent
234 * @param column the column address for this command, -1 if none
235 * @param page_addr the page address for this command, -1 if none
236 */
ca_nand_command(struct mtd_info * mtd,unsigned int command,int column,int page_addr)237 static void ca_nand_command(struct mtd_info *mtd, unsigned int command,
238 int column, int page_addr)
239 {
240 struct nand_chip *chip = mtd_to_nand(mtd);
241 struct nand_drv *info;
242 unsigned int reg_v = 0;
243 u32 cmd = 0, cnt = 0, addr1 = 0, addr2 = 0;
244 int ret;
245
246 info = (struct nand_drv *)nand_get_controller_data(chip);
247 /*
248 * Write out the command to the device.
249 *
250 * Only command NAND_CMD_RESET or NAND_CMD_READID will come
251 * here before mtd->writesize is initialized.
252 */
253
254 /* Emulate NAND_CMD_READOOB */
255 if (command == NAND_CMD_READOOB) {
256 assert(mtd->writesize != 0);
257 column += mtd->writesize;
258 command = NAND_CMD_READ0;
259 }
260
261 /* Reset FIFO before issue new command */
262 clrsetbits_le32(&info->reg->flash_nf_ecc_reset, GENMASK(31, 0),
263 ECC_RESET_ALL);
264 ret =
265 readl_poll_timeout(&info->reg->flash_nf_ecc_reset, reg_v,
266 !(reg_v & RESET_NFLASH_FIFO), FLASH_SHORT_DELAY);
267 if (ret) {
268 printf("FIFO reset timeout\n");
269 clrsetbits_le32(&info->reg->flash_nf_ecc_reset, GENMASK(31, 0),
270 ECC_RESET_ALL);
271 udelay(10);
272 }
273
274 /* Reset FIFO index
275 * Next read start from flash_nf_data[0]
276 */
277 info->fifo_index = 0;
278
279 clrsetbits_le32(&info->reg->flash_nf_access, GENMASK(11, 10),
280 NFLASH_REG_WIDTH_8);
281
282 /*
283 * Program and erase have their own busy handlers
284 * status and sequential in needs no delay
285 */
286 switch (command) {
287 case NAND_CMD_READID:
288 /* Command */
289 clrsetbits_le32(&info->reg->flash_nf_command, GENMASK(31, 0),
290 NAND_CMD_READID);
291 /* 1 byte CMD cycle */
292 clrsetbits_le32(&info->reg->flash_nf_count, GENMASK(1, 0),
293 REG_CMD_COUNT_1TOGO);
294 /* 1 byte CMD cycle */
295 clrsetbits_le32(&info->reg->flash_nf_count, GENMASK(6, 4),
296 REG_ADDR_COUNT_1);
297 /* Data cycle */
298 clrsetbits_le32(&info->reg->flash_nf_count, GENMASK(21, 8),
299 REG_DATA_COUNT_DATA_4);
300 /* 0 OOB cycle */
301 clrsetbits_le32(&info->reg->flash_nf_count, GENMASK(31, 22),
302 REG_OOB_COUNT_EMPTY);
303
304 /* addresses */
305 clrsetbits_le32(&info->reg->flash_nf_address_1, GENMASK(31, 0),
306 column & ADDR1_MASK2);
307 clrsetbits_le32(&info->reg->flash_nf_address_2, GENMASK(31, 0),
308 0);
309
310 /* clear FLASH_NF_ACCESS */
311 clrsetbits_le32(&info->reg->flash_nf_access, GENMASK(31, 0),
312 DISABLE_AUTO_RESET);
313
314 break;
315 case NAND_CMD_PARAM:
316 /* Command */
317 clrsetbits_le32(&info->reg->flash_nf_command, GENMASK(31, 0),
318 NAND_CMD_PARAM);
319 /* 1 byte CMD cycle */
320 clrsetbits_le32(&info->reg->flash_nf_count, GENMASK(1, 0),
321 REG_CMD_COUNT_1TOGO);
322 /* 1 byte ADDR cycle */
323 clrsetbits_le32(&info->reg->flash_nf_count, GENMASK(6, 4),
324 REG_ADDR_COUNT_1);
325 /* Data cycle */
326 clrsetbits_le32(&info->reg->flash_nf_count, GENMASK(21, 8),
327 (SZ_4K - 1) << 8);
328 /* 0 OOB cycle */
329 clrsetbits_le32(&info->reg->flash_nf_count, GENMASK(31, 22),
330 REG_OOB_COUNT_EMPTY);
331
332 /* addresses */
333 clrsetbits_le32(&info->reg->flash_nf_address_1, GENMASK(31, 0),
334 column & ADDR1_MASK2);
335 clrsetbits_le32(&info->reg->flash_nf_address_2, GENMASK(31, 0),
336 0);
337
338 break;
339 case NAND_CMD_READ0:
340 if (chip->chipsize < SZ_32M) {
341 cmd = NAND_CMD_READ0;
342 cnt = REG_CMD_COUNT_1TOGO | REG_ADDR_COUNT_3;
343 addr1 = (((page_addr & ADDR1_MASK0) << 8));
344 addr2 = ((page_addr & ADDR2_MASK0) >> 24);
345 } else if (chip->chipsize >= SZ_32M &&
346 (chip->chipsize <= SZ_128M)) {
347 cmd = NAND_CMD_READ0;
348 cnt = REG_ADDR_COUNT_4;
349 if (mtd->writesize > (REG_DATA_COUNT_512_DATA >> 8)) {
350 cmd |= (NAND_CMD_READSTART << 8);
351 cnt |= REG_CMD_COUNT_2TOGO;
352 } else {
353 cnt |= REG_CMD_COUNT_1TOGO;
354 }
355 addr1 = ((page_addr << 16) | (column & ADDR1_MASK1));
356 addr2 = (page_addr >> 16);
357 } else {
358 cmd = NAND_CMD_READ0 | (NAND_CMD_READSTART << 8);
359 cnt = REG_CMD_COUNT_2TOGO | REG_ADDR_COUNT_5;
360 addr1 = ((page_addr << 16) | (column & ADDR1_MASK1));
361 addr2 = (page_addr >> 16);
362 }
363
364 /* Command */
365 clrsetbits_le32(&info->reg->flash_nf_command, GENMASK(31, 0),
366 cmd);
367 /* CMD & ADDR cycle */
368 clrsetbits_le32(&info->reg->flash_nf_count, GENMASK(7, 0), cnt);
369 /* Data cycle */
370 clrsetbits_le32(&info->reg->flash_nf_count, GENMASK(21, 8),
371 (mtd->writesize - 1) << 8);
372 /* OOB cycle */
373 clrsetbits_le32(&info->reg->flash_nf_count, GENMASK(31, 22),
374 (mtd->oobsize - 1) << 22);
375
376 /* addresses */
377 clrsetbits_le32(&info->reg->flash_nf_address_1, GENMASK(31, 0),
378 addr1);
379 clrsetbits_le32(&info->reg->flash_nf_address_2, GENMASK(31, 0),
380 addr2);
381
382 return;
383 case NAND_CMD_SEQIN:
384 if (chip->chipsize < SZ_32M) {
385 cnt = REG_CMD_COUNT_2TOGO | REG_ADDR_COUNT_3;
386 addr1 = (((page_addr & ADDR1_MASK0) << 8));
387 addr2 = ((page_addr & ADDR2_MASK0) >> 24);
388 } else if (chip->chipsize >= SZ_32M &&
389 (chip->chipsize <= SZ_128M)) {
390 cnt = REG_CMD_COUNT_2TOGO | REG_ADDR_COUNT_4;
391 addr1 = ((page_addr << 16) | (column & ADDR1_MASK1));
392 addr2 = (page_addr >> 16);
393 } else {
394 cnt = REG_CMD_COUNT_2TOGO | REG_ADDR_COUNT_5;
395 addr1 = ((page_addr << 16) | (column & ADDR1_MASK1));
396 addr2 = (page_addr >> 16);
397 }
398
399 /* Command */
400 clrsetbits_le32(&info->reg->flash_nf_command, GENMASK(31, 0),
401 NAND_CMD_SEQIN | (NAND_CMD_PAGEPROG << 8));
402 /* CMD cycle */
403 clrsetbits_le32(&info->reg->flash_nf_count, GENMASK(7, 0), cnt);
404 /* Data cycle */
405 clrsetbits_le32(&info->reg->flash_nf_count, GENMASK(21, 8),
406 (mtd->writesize - 1) << 8);
407 /* OOB cycle */
408 clrsetbits_le32(&info->reg->flash_nf_count, GENMASK(31, 22),
409 (mtd->oobsize - 1) << 22);
410
411 /* addresses */
412 clrsetbits_le32(&info->reg->flash_nf_address_1, GENMASK(31, 0),
413 addr1);
414 clrsetbits_le32(&info->reg->flash_nf_address_2, GENMASK(31, 0),
415 addr2);
416
417 return;
418 case NAND_CMD_PAGEPROG:
419 return;
420 case NAND_CMD_ERASE1:
421 /* Command */
422 clrsetbits_le32(&info->reg->flash_nf_command, GENMASK(31, 0),
423 NAND_CMD_ERASE1 | (NAND_CMD_ERASE2 << 8));
424 /* 2 byte CMD cycle */
425 clrsetbits_le32(&info->reg->flash_nf_count, GENMASK(1, 0),
426 REG_CMD_COUNT_2TOGO);
427 /* 3 byte ADDR cycle */
428 clrsetbits_le32(&info->reg->flash_nf_count, GENMASK(6, 4),
429 REG_ADDR_COUNT_3);
430 /* 0 Data cycle */
431 clrsetbits_le32(&info->reg->flash_nf_count, GENMASK(21, 8),
432 REG_DATA_COUNT_EMPTY);
433 /* 0 OOB cycle */
434 clrsetbits_le32(&info->reg->flash_nf_count, GENMASK(31, 22),
435 REG_OOB_COUNT_EMPTY);
436
437 /* addresses */
438 clrsetbits_le32(&info->reg->flash_nf_address_1, GENMASK(31, 0),
439 page_addr);
440 clrsetbits_le32(&info->reg->flash_nf_address_2, GENMASK(31, 0),
441 0);
442
443 /* Issue command */
444 clrsetbits_le32(&info->reg->flash_flash_access_start,
445 GENMASK(31, 0), NFLASH_GO | NFLASH_RD);
446 break;
447 case NAND_CMD_ERASE2:
448 return;
449 case NAND_CMD_STATUS:
450 /* Command */
451 clrsetbits_le32(&info->reg->flash_nf_command, GENMASK(31, 0),
452 NAND_CMD_STATUS);
453 /* 1 byte CMD cycle */
454 clrbits_le32(&info->reg->flash_nf_count, GENMASK(1, 0));
455 /* 0 byte Addr cycle */
456 clrsetbits_le32(&info->reg->flash_nf_count, GENMASK(6, 4),
457 REG_ADDR_COUNT_EMPTY);
458 /* 1 Data cycle */
459 clrbits_le32(&info->reg->flash_nf_count, GENMASK(21, 8));
460 /* 0 OOB cycle */
461 clrsetbits_le32(&info->reg->flash_nf_count, GENMASK(31, 22),
462 REG_OOB_COUNT_EMPTY);
463
464 break;
465 case NAND_CMD_RESET:
466 /* Command */
467 clrsetbits_le32(&info->reg->flash_nf_command, GENMASK(31, 0),
468 NAND_CMD_RESET);
469 /* 1 byte CMD cycle */
470 clrbits_le32(&info->reg->flash_nf_count, GENMASK(1, 0));
471 /* 0 byte Addr cycle */
472 clrsetbits_le32(&info->reg->flash_nf_count, GENMASK(6, 4),
473 REG_ADDR_COUNT_EMPTY);
474 /* 0 Data cycle */
475 clrsetbits_le32(&info->reg->flash_nf_count, GENMASK(21, 8),
476 REG_DATA_COUNT_EMPTY);
477 /* 0 OOB cycle */
478 clrsetbits_le32(&info->reg->flash_nf_count, GENMASK(31, 22),
479 REG_OOB_COUNT_EMPTY);
480
481 /* addresses */
482 clrsetbits_le32(&info->reg->flash_nf_address_1, GENMASK(31, 0),
483 column & ADDR1_MASK2);
484 clrsetbits_le32(&info->reg->flash_nf_address_2, GENMASK(31, 0),
485 0);
486
487 /* Issue command */
488 clrsetbits_le32(&info->reg->flash_flash_access_start,
489 GENMASK(31, 0), NFLASH_GO | NFLASH_WT);
490
491 break;
492 case NAND_CMD_RNDOUT:
493 default:
494 printf("%s: Unsupported command %d\n", __func__, command);
495 return;
496 }
497
498 if (!nand_waitfor_cmd_completion(info->reg, NFLASH_GO))
499 printf("Command 0x%02X timeout\n", command);
500 }
501
502 /**
503 * Set up NAND bus width and page size
504 *
505 * @param info nand_info structure
506 * @return 0 if ok, -1 on error
507 */
set_bus_width_page_size(struct mtd_info * mtd)508 static int set_bus_width_page_size(struct mtd_info *mtd)
509 {
510 struct nand_chip *chip = mtd_to_nand(mtd);
511 struct nand_drv *info =
512 (struct nand_drv *)nand_get_controller_data(chip);
513
514 if (info->config.width == SZ_8) {
515 clrsetbits_le32(&info->reg->flash_nf_access, GENMASK(31, 0),
516 NFLASH_REG_WIDTH_8);
517 } else if (info->config.width == SZ_16) {
518 clrsetbits_le32(&info->reg->flash_nf_access, GENMASK(31, 0),
519 NFLASH_REG_WIDTH_16);
520 } else {
521 debug("%s: Unsupported bus width %d\n", __func__,
522 info->config.width);
523 return -1;
524 }
525
526 if (mtd->writesize == SZ_512) {
527 setbits_le32(&info->reg->flash_type, FLASH_TYPE_512);
528 } else if (mtd->writesize == SZ_2K) {
529 setbits_le32(&info->reg->flash_type, FLASH_TYPE_2K);
530 } else if (mtd->writesize == SZ_4K) {
531 setbits_le32(&info->reg->flash_type, FLASH_TYPE_4K);
532 } else if (mtd->writesize == SZ_8K) {
533 setbits_le32(&info->reg->flash_type, FLASH_TYPE_8K);
534 } else {
535 debug("%s: Unsupported page size %d\n", __func__,
536 mtd->writesize);
537 return -1;
538 }
539
540 return 0;
541 }
542
ca_do_bch_correction(struct nand_chip * chip,unsigned int err_num,u8 * buff_ptr,int i)543 static int ca_do_bch_correction(struct nand_chip *chip,
544 unsigned int err_num, u8 *buff_ptr, int i)
545 {
546 struct nand_drv *info =
547 (struct nand_drv *)nand_get_controller_data(chip);
548 unsigned int reg_v, err_loc0, err_loc1;
549 int k, max_bitflips = 0;
550
551 for (k = 0; k < (err_num + 1) / 2; k++) {
552 reg_v = readl(&info->reg->flash_nf_bch_error_loc01 + k);
553 err_loc0 = reg_v & BCH_ERR_LOC_MASK;
554 err_loc1 = (reg_v >> 16) & BCH_ERR_LOC_MASK;
555
556 if (err_loc0 / 8 < BCH_DATA_UNIT) {
557 printf("pdata[%x]:%x =>", ((i / chip->ecc.bytes) *
558 chip->ecc.size + ((reg_v & 0x1fff) >> 3)),
559 buff_ptr[(reg_v & 0x1fff) >> 3]);
560
561 buff_ptr[err_loc0 / 8] ^=
562 (1 << (reg_v & BCH_CORRECT_LOC_MASK));
563
564 printf("%x\n", buff_ptr[(reg_v & 0x1fff) >> 3]);
565
566 max_bitflips++;
567 }
568
569 if (((k + 1) * 2) <= err_num && ((err_loc1 / 8) <
570 BCH_DATA_UNIT)) {
571 printf("pdata[%x]:%x =>", ((i / chip->ecc.bytes) *
572 chip->ecc.size + (((reg_v >> 16) & 0x1fff) >>
573 3)), buff_ptr[((reg_v >> 16) & 0x1fff) >> 3]);
574
575 buff_ptr[err_loc1 / 8] ^= (1 << ((reg_v >> 16) &
576 BCH_CORRECT_LOC_MASK));
577
578 printf("%x\n", buff_ptr[((reg_v >> 16) & 0x1fff) >> 3]);
579
580 max_bitflips++;
581 }
582 }
583
584 return max_bitflips;
585 }
586
ca_do_bch_decode(struct mtd_info * mtd,struct nand_chip * chip,const u8 * buf,int page,unsigned int addr)587 static int ca_do_bch_decode(struct mtd_info *mtd, struct nand_chip *chip,
588 const u8 *buf, int page, unsigned int addr)
589 {
590 struct nand_drv *info =
591 (struct nand_drv *)nand_get_controller_data(chip);
592 unsigned int reg_v, err_num;
593 unsigned char *ecc_code = chip->buffers->ecccode;
594 unsigned char *ecc_end_pos;
595 int ret, i, j, k, n, step, eccsteps, max_bitflips = 0;
596 u8 *buff_ptr = (u8 *)buf;
597
598 for (i = 0; i < chip->ecc.total; i++)
599 ecc_code[i] = chip->oob_poi[eccoob.eccpos[i]];
600
601 for (i = 0, eccsteps = chip->ecc.steps; eccsteps;
602 i += chip->ecc.bytes, eccsteps--) {
603 ecc_end_pos = ecc_code + chip->ecc.bytes;
604
605 for (j = 0, k = 0; j < chip->ecc.bytes; j += 4, k++) {
606 reg_v = 0;
607 for (n = 0; n < 4 && ecc_code != ecc_end_pos;
608 ++n, ++ecc_code) {
609 reg_v |= *ecc_code << (8 * n);
610 }
611 clrsetbits_le32(&info->reg->flash_nf_bch_oob0 + k,
612 GENMASK(31, 0), reg_v);
613 }
614
615 /* Clear ECC buffer */
616 setbits_le32(&info->reg->flash_nf_ecc_reset, RESET_NFLASH_ECC);
617 ret = readl_poll_timeout(&info->reg->flash_nf_ecc_reset, reg_v,
618 !(reg_v & RESET_NFLASH_ECC),
619 FLASH_SHORT_DELAY);
620 if (ret)
621 pr_err("Reset ECC buffer fail\n");
622
623 clrsetbits_le32(&info->reg->flash_nf_bch_control, GENMASK(8, 8),
624 BCH_DISABLE);
625
626 /* Start BCH */
627 step = i / chip->ecc.bytes;
628 clrsetbits_le32(&info->reg->flash_nf_bch_control,
629 GENMASK(6, 4), step << 4);
630 setbits_le32(&info->reg->flash_nf_bch_control, BCH_ENABLE);
631 udelay(10);
632 setbits_le32(&info->reg->flash_nf_bch_control, BCH_COMPARE);
633
634 ret = readl_poll_timeout(&info->reg->flash_nf_bch_status, reg_v,
635 (reg_v & BCH_DECO_DONE),
636 FLASH_SHORT_DELAY);
637 if (ret)
638 pr_err("ECC Decode timeout\n");
639
640 /* Stop compare */
641 clrbits_le32(&info->reg->flash_nf_bch_control, BCH_COMPARE);
642
643 reg_v = readl(&info->reg->flash_nf_bch_status);
644 err_num = (reg_v >> 8) & BCH_ERR_NUM_MASK;
645 reg_v &= BCH_ERR_MASK;
646
647 /* Uncorrectable */
648 if (reg_v == BCH_UNCORRECTABLE) {
649 max_bitflips =
650 nand_check_erased_ecc_chunk(buff_ptr,
651 chip->ecc.size,
652 &chip->buffers->ecccode[i],
653 chip->ecc.bytes,
654 NULL, 0,
655 chip->ecc.strength);
656
657 if (max_bitflips) {
658 mtd->ecc_stats.failed++;
659 pr_err("Uncorrectable error\n");
660 pr_err(" Page:%x step:%d\n", page, step);
661
662 return -1;
663 }
664 } else if (reg_v == BCH_CORRECTABLE_ERR) {
665 printf("Correctable error(%x)!! addr:%lx\n",
666 err_num, (unsigned long)addr - mtd->writesize);
667 printf("Dst buf: %p [ColSel:%x ]\n",
668 buff_ptr + reg_v * BCH_DATA_UNIT, step);
669
670 max_bitflips =
671 ca_do_bch_correction(chip, err_num, buff_ptr, i);
672 }
673
674 buff_ptr += BCH_DATA_UNIT;
675 }
676
677 /* Disable BCH */
678 clrsetbits_le32(&info->reg->flash_nf_bch_control, GENMASK(31, 0),
679 BCH_DISABLE);
680
681 return max_bitflips;
682 }
683
ca_do_bch_encode(struct mtd_info * mtd,struct nand_chip * chip,int page)684 static int ca_do_bch_encode(struct mtd_info *mtd, struct nand_chip *chip,
685 int page)
686 {
687 struct nand_drv *info;
688 unsigned int reg_v;
689 int i, j, n, eccsteps, gen_index;
690
691 info = (struct nand_drv *)nand_get_controller_data(chip);
692
693 for (i = 0, n = 0, eccsteps = chip->ecc.steps; eccsteps;
694 i += chip->ecc.bytes, eccsteps--, n++) {
695 gen_index = 0;
696 for (j = 0; j < chip->ecc.bytes; j += 4, gen_index++) {
697 reg_v =
698 readl(&info->reg->flash_nf_bch_gen0_0 + gen_index +
699 18 * n);
700 chip->oob_poi[eccoob.eccpos[i + j]] = reg_v & OOB_MASK;
701 chip->oob_poi[eccoob.eccpos[i + j + 1]] =
702 (reg_v >> 8) & OOB_MASK;
703 chip->oob_poi[eccoob.eccpos[i + j + 2]] =
704 (reg_v >> 16) & OOB_MASK;
705 chip->oob_poi[eccoob.eccpos[i + j + 3]] =
706 (reg_v >> 24) & OOB_MASK;
707 }
708 }
709
710 /* Disable BCH */
711 clrsetbits_le32(&info->reg->flash_nf_bch_control, GENMASK(8, 8),
712 BCH_DISABLE);
713
714 return 0;
715 }
716
717 /**
718 * Page read/write function
719 *
720 * @param mtd mtd info structure
721 * @param chip nand chip info structure
722 * @param buf data buffer
723 * @param page page number
724 * @param with_ecc 1 to enable ECC, 0 to disable ECC
725 * @param is_writing 0 for read, 1 for write
726 * @return 0 when successfully completed
727 * -ETIMEDOUT when command timeout
728 */
nand_rw_page(struct mtd_info * mtd,struct nand_chip * chip,const u8 * buf,int page,int with_ecc,int is_writing)729 static int nand_rw_page(struct mtd_info *mtd, struct nand_chip *chip,
730 const u8 *buf, int page, int with_ecc, int is_writing)
731 {
732 unsigned int reg_v, ext_addr, addr, dma_index;
733 struct tx_descriptor_t *tx_desc;
734 struct rx_descriptor_t *rx_desc;
735 struct nand_drv *info =
736 (struct nand_drv *)nand_get_controller_data(chip);
737 int ret;
738
739 /* reset ecc control */
740 clrsetbits_le32(&info->reg->flash_nf_ecc_reset, GENMASK(31, 0),
741 RESET_NFLASH_ECC);
742
743 /* flash interrupt */
744 clrsetbits_le32(&info->reg->flash_flash_interrupt, GENMASK(0, 0),
745 REGIRQ_CLEAR);
746
747 /* reset ecc control */
748 clrsetbits_le32(&info->reg->flash_nf_ecc_reset, GENMASK(31, 0),
749 RESET_NFLASH_ECC);
750
751 /* Disable TXQ */
752 clrbits_le32(&info->dma_nand->dma_q_txq_control, GENMASK(0, 0));
753
754 /* Clear interrupt */
755 setbits_le32(&info->dma_nand->dma_q_rxq_coal_interrupt, GENMASK(0, 0));
756 setbits_le32(&info->dma_nand->dma_q_txq_coal_interrupt, GENMASK(0, 0));
757
758 if (with_ecc == 1) {
759 switch (info->config.nand_ecc_strength) {
760 case ECC_STRENGTH_8:
761 reg_v = BCH_ERR_CAP_8;
762 break;
763 case ECC_STRENGTH_16:
764 reg_v = BCH_ERR_CAP_16;
765 break;
766 case ECC_STRENGTH_24:
767 reg_v = BCH_ERR_CAP_24;
768 break;
769 case ECC_STRENGTH_40:
770 reg_v = BCH_ERR_CAP_40;
771 break;
772 default:
773 reg_v = BCH_ERR_CAP_16;
774 break;
775 }
776 reg_v |= BCH_ENABLE;
777
778 /* BCH decode for flash read */
779 if (is_writing == 0)
780 reg_v |= BCH_DECODE;
781 clrsetbits_le32(&info->reg->flash_nf_bch_control,
782 GENMASK(31, 0), reg_v);
783 } else {
784 clrsetbits_le32(&info->reg->flash_nf_bch_control,
785 GENMASK(31, 0), 0);
786 }
787
788 /* Fill Extend address */
789 ext_addr = ((page << chip->page_shift) / EXT_ADDR_MASK);
790
791 clrsetbits_le32(&info->reg->flash_nf_access,
792 GENMASK(7, 0), (uintptr_t)ext_addr);
793
794 addr = (uintptr_t)((page << chip->page_shift) % EXT_ADDR_MASK);
795 addr = (uintptr_t)(addr + info->flash_base);
796
797 dma_index = readl(&info->dma_nand->dma_q_txq_wptr) & CA_DMA_Q_PTR_MASK;
798
799 tx_desc = info->tx_desc;
800 rx_desc = info->rx_desc;
801
802 /* TX/RX descriptor for page data */
803 tx_desc[dma_index].own = OWN_DMA;
804 tx_desc[dma_index].buf_len = mtd->writesize;
805 rx_desc[dma_index].own = OWN_DMA;
806 rx_desc[dma_index].buf_len = mtd->writesize;
807 if (is_writing == 0) {
808 tx_desc[dma_index].buf_adr = (uintptr_t)addr;
809 rx_desc[dma_index].buf_adr = (uintptr_t)(buf);
810 } else {
811 tx_desc[dma_index].buf_adr = (uintptr_t)buf;
812 rx_desc[dma_index].buf_adr = (uintptr_t)(addr);
813 }
814
815 dma_index++;
816 dma_index %= CA_DMA_DESC_NUM;
817
818 /* TX/RX descriptor for OOB area */
819 addr = (uintptr_t)(addr + mtd->writesize);
820 tx_desc[dma_index].own = OWN_DMA;
821 tx_desc[dma_index].buf_len = mtd->oobsize;
822 rx_desc[dma_index].own = OWN_DMA;
823 rx_desc[dma_index].buf_len = mtd->oobsize;
824 if (is_writing) {
825 tx_desc[dma_index].buf_adr = (uintptr_t)(chip->oob_poi);
826 rx_desc[dma_index].buf_adr = (uintptr_t)addr;
827 } else {
828 tx_desc[dma_index].buf_adr = (uintptr_t)addr;
829 rx_desc[dma_index].buf_adr = (uintptr_t)(chip->oob_poi);
830 dma_index++;
831 dma_index %= CA_DMA_DESC_NUM;
832 }
833
834 if (is_writing == 1) {
835 clrsetbits_le32(&info->reg->flash_fifo_control, GENMASK(1, 0),
836 FIFO_WRITE);
837 } else {
838 clrsetbits_le32(&info->reg->flash_fifo_control, GENMASK(1, 0),
839 FIFO_READ);
840 }
841
842 /* Start FIFO request */
843 clrsetbits_le32(&info->reg->flash_flash_access_start, GENMASK(2, 2),
844 NFLASH_FIFO_REQ);
845
846 /* Update DMA write pointer */
847 clrsetbits_le32(&info->dma_nand->dma_q_txq_wptr, GENMASK(12, 0),
848 dma_index);
849
850 /* Start DMA */
851 clrsetbits_le32(&info->dma_nand->dma_q_txq_control, GENMASK(0, 0),
852 TX_DMA_ENABLE);
853
854 /* Wait TX DMA done */
855 ret =
856 readl_poll_timeout(&info->dma_nand->dma_q_txq_coal_interrupt,
857 reg_v, (reg_v & 1), FLASH_LONG_DELAY);
858 if (ret) {
859 pr_err("TX DMA timeout\n");
860 return -ETIMEDOUT;
861 }
862 /* clear tx interrupt */
863 setbits_le32(&info->dma_nand->dma_q_txq_coal_interrupt, 1);
864
865 /* Wait RX DMA done */
866 ret =
867 readl_poll_timeout(&info->dma_nand->dma_q_rxq_coal_interrupt, reg_v,
868 (reg_v & 1), FLASH_LONG_DELAY);
869 if (ret) {
870 pr_err("RX DMA timeout\n");
871 return -ETIMEDOUT;
872 }
873 /* clear rx interrupt */
874 setbits_le32(&info->dma_nand->dma_q_rxq_coal_interrupt, 1);
875
876 /* wait NAND CMD done */
877 if (is_writing == 0) {
878 if (!nand_waitfor_cmd_completion(info->reg, NFLASH_FIFO_REQ))
879 printf("%s: Command timeout\n", __func__);
880 }
881
882 /* Update DMA read pointer */
883 clrsetbits_le32(&info->dma_nand->dma_q_rxq_rptr, GENMASK(12, 0),
884 dma_index);
885
886 /* ECC correction */
887 if (with_ecc == 1) {
888 ret =
889 readl_poll_timeout(&info->reg->flash_nf_bch_status,
890 reg_v, (reg_v & BCH_GEN_DONE),
891 FLASH_LONG_DELAY);
892
893 if (ret) {
894 pr_err("BCH_GEN timeout! flash_nf_bch_status=[0x%x]\n",
895 reg_v);
896 return -ETIMEDOUT;
897 }
898
899 if (is_writing == 0)
900 ca_do_bch_decode(mtd, chip, buf, page, addr);
901 else
902 ca_do_bch_encode(mtd, chip, page);
903 }
904
905 if (is_writing) {
906 dma_index++;
907 dma_index %= CA_DMA_DESC_NUM;
908
909 /* Update DMA R/W pointer */
910 clrsetbits_le32(&info->dma_nand->dma_q_txq_wptr, GENMASK(12, 0),
911 dma_index);
912
913 /* Wait TX DMA done */
914 ret =
915 readl_poll_timeout(&info->dma_nand->dma_q_txq_coal_interrupt,
916 reg_v, (reg_v & 1), FLASH_LONG_DELAY);
917 if (ret) {
918 pr_err("TX DMA timeout\n");
919 return -ETIMEDOUT;
920 }
921 /* clear tx interrupt */
922 setbits_le32(&info->dma_nand->dma_q_txq_coal_interrupt, 1);
923
924 /* Wait RX DMA done */
925 ret =
926 readl_poll_timeout(&info->dma_nand->dma_q_rxq_coal_interrupt,
927 reg_v, (reg_v & 1), FLASH_LONG_DELAY);
928 if (ret) {
929 pr_err("RX DMA timeout\n");
930 return -ETIMEDOUT;
931 }
932 /* clear rx interrupt */
933 setbits_le32(&info->dma_nand->dma_q_rxq_coal_interrupt, 1);
934
935 /* wait NAND CMD done */
936 if (!nand_waitfor_cmd_completion(info->reg, NFLASH_FIFO_REQ))
937 printf("%s: Command timeout\n", __func__);
938
939 /* Update DMA R/W pointer */
940 clrsetbits_le32(&info->dma_nand->dma_q_rxq_rptr, GENMASK(12, 0),
941 dma_index);
942 }
943
944 return 0;
945 }
946
947 /**
948 * Hardware ecc based page read function
949 *
950 * @param mtd mtd info structure
951 * @param chip nand chip info structure
952 * @param buf buffer to store read data
953 * @param page page number to read
954 * @return 0 when successfully completed
955 * -ETIMEDOUT when command timeout
956 */
nand_read_page_hwecc(struct mtd_info * mtd,struct nand_chip * chip,uint8_t * buf,int oob_required,int page)957 static int nand_read_page_hwecc(struct mtd_info *mtd,
958 struct nand_chip *chip, uint8_t *buf,
959 int oob_required, int page)
960 {
961 struct nand_drv *info =
962 (struct nand_drv *)nand_get_controller_data(chip);
963 int ret;
964
965 ret = nand_rw_page(mtd, chip, buf, page, 1, 0);
966 if (ret)
967 return ret;
968
969 /* Reset FIFO */
970 clrsetbits_le32(&info->reg->flash_nf_ecc_reset, GENMASK(31, 0),
971 ECC_RESET_ALL);
972
973 return 0;
974 }
975
976 /**
977 * Hardware ecc based page write function
978 *
979 * @param mtd mtd info structure
980 * @param chip nand chip info structure
981 * @param buf data buffer
982 * @return 0 when successfully completed
983 * -ETIMEDOUT when command timeout
984 */
nand_write_page_hwecc(struct mtd_info * mtd,struct nand_chip * chip,const uint8_t * buf,int oob_required,int page)985 static int nand_write_page_hwecc(struct mtd_info *mtd,
986 struct nand_chip *chip, const uint8_t *buf,
987 int oob_required, int page)
988 {
989 struct nand_drv *info =
990 (struct nand_drv *)nand_get_controller_data(chip);
991 int ret;
992
993 ret = nand_rw_page(mtd, chip, (uint8_t *)buf, page, 1, 1);
994 if (ret)
995 return ret;
996
997 /* Reset FIFO */
998 clrsetbits_le32(&info->reg->flash_nf_ecc_reset, GENMASK(31, 0),
999 ECC_RESET_ALL);
1000
1001 return 0;
1002 }
1003
1004 /**
1005 * Read raw page data without ecc
1006 *
1007 * @param mtd mtd info structure
1008 * @param chip nand chip info structure
1009 * @param buf buffer to store read data
1010 * @param page page number to read
1011 * @return 0 when successfully completed
1012 * -ETIMEDOUT when command timeout
1013 */
nand_read_page_raw(struct mtd_info * mtd,struct nand_chip * chip,uint8_t * buf,int oob_required,int page)1014 static int nand_read_page_raw(struct mtd_info *mtd,
1015 struct nand_chip *chip, uint8_t *buf,
1016 int oob_required, int page)
1017 {
1018 struct nand_drv *info =
1019 (struct nand_drv *)nand_get_controller_data(chip);
1020 int ret;
1021
1022 ret = nand_rw_page(mtd, chip, buf, page, 0, 0);
1023 if (ret)
1024 return ret;
1025
1026 /* Reset FIFO */
1027 clrsetbits_le32(&info->reg->flash_nf_ecc_reset, GENMASK(31, 0),
1028 ECC_RESET_ALL);
1029
1030 return 0;
1031 }
1032
1033 /**
1034 * Raw page write function
1035 *
1036 * @param mtd mtd info structure
1037 * @param chip nand chip info structure
1038 * @param buf data buffer
1039 * @return 0 when successfully completed
1040 * -ETIMEDOUT when command timeout
1041 */
nand_write_page_raw(struct mtd_info * mtd,struct nand_chip * chip,const uint8_t * buf,int oob_required,int page)1042 static int nand_write_page_raw(struct mtd_info *mtd,
1043 struct nand_chip *chip, const uint8_t *buf,
1044 int oob_required, int page)
1045 {
1046 struct nand_drv *info =
1047 (struct nand_drv *)nand_get_controller_data(chip);
1048 int ret;
1049
1050 ret = nand_rw_page(mtd, chip, buf, page, 0, 1);
1051 if (ret)
1052 return ret;
1053
1054 /* Reset FIFO */
1055 clrsetbits_le32(&info->reg->flash_nf_ecc_reset, GENMASK(31, 0),
1056 ECC_RESET_ALL);
1057
1058 return 0;
1059 }
1060
1061 /**
1062 * OOB data read/write function
1063 *
1064 * @param mtd mtd info structure
1065 * @param chip nand chip info structure
1066 * @param page page number to read
1067 * @param with_ecc 1 to enable ECC, 0 to disable ECC
1068 * @param is_writing 0 for read, 1 for write
1069 * @return 0 when successfully completed
1070 * -ETIMEDOUT when command timeout
1071 */
nand_rw_oob(struct mtd_info * mtd,struct nand_chip * chip,int page,int with_ecc,int is_writing)1072 static int nand_rw_oob(struct mtd_info *mtd, struct nand_chip *chip,
1073 int page, int with_ecc, int is_writing)
1074 {
1075 struct nand_drv *info =
1076 (struct nand_drv *)nand_get_controller_data(chip);
1077 u32 reg_val;
1078 int rw_index;
1079
1080 if (is_writing) {
1081 reg_val = NFLASH_GO | NFLASH_WT;
1082 pwrite = (unsigned int *)chip->oob_poi;
1083 } else {
1084 reg_val = NFLASH_GO | NFLASH_RD;
1085 pread = (unsigned int *)chip->oob_poi;
1086 }
1087
1088 for (rw_index = 0; rw_index < mtd->oobsize / 4; rw_index++) {
1089 clrsetbits_le32(&info->reg->flash_nf_access, GENMASK(31, 0),
1090 NFLASH_REG_WIDTH_32);
1091 if (is_writing)
1092 clrsetbits_le32(&info->reg->flash_nf_data,
1093 GENMASK(31, 0), pwrite[rw_index]);
1094
1095 clrsetbits_le32(&info->reg->flash_flash_access_start,
1096 GENMASK(11, 10), reg_val);
1097
1098 if (!nand_waitfor_cmd_completion(info->reg, NFLASH_GO))
1099 printf("%s: Command timeout\n", __func__);
1100
1101 if (!is_writing)
1102 pread[rw_index] = readl(&info->reg->flash_nf_data);
1103 }
1104 return 0;
1105 }
1106
1107 /**
1108 * OOB data read function
1109 *
1110 * @param mtd mtd info structure
1111 * @param chip nand chip info structure
1112 * @param page page number to read
1113 */
nand_read_oob(struct mtd_info * mtd,struct nand_chip * chip,int page)1114 static int nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip, int page)
1115 {
1116 struct nand_drv *info =
1117 (struct nand_drv *)nand_get_controller_data(chip);
1118 int ret;
1119
1120 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1121 if (mtd->writesize <= (REG_DATA_COUNT_512_DATA >> 8))
1122 clrsetbits_le32(&info->reg->flash_nf_command, GENMASK(7, 0),
1123 NAND_CMD_READOOB);
1124 ret = nand_rw_oob(mtd, chip, page, 0, 0);
1125
1126 /* Reset FIFO */
1127 clrsetbits_le32(&info->reg->flash_nf_ecc_reset,
1128 GENMASK(31, 0), ECC_RESET_ALL);
1129
1130 return ret;
1131 }
1132
1133 /**
1134 * OOB data write function
1135 *
1136 * @param mtd mtd info structure
1137 * @param chip nand chip info structure
1138 * @param page page number to write
1139 * @return 0 when successfully completed
1140 * -ETIMEDOUT when command timeout
1141 */
nand_write_oob(struct mtd_info * mtd,struct nand_chip * chip,int page)1142 static int nand_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
1143 int page)
1144 {
1145 struct nand_drv *info =
1146 (struct nand_drv *)nand_get_controller_data(chip);
1147 int ret;
1148
1149 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1150 if (mtd->writesize <= (REG_DATA_COUNT_512_DATA >> 8)) {
1151 clrsetbits_le32(&info->reg->flash_nf_command, GENMASK(31, 0),
1152 NAND_CMD_READOOB | (NAND_CMD_SEQIN << 8) |
1153 (NAND_CMD_PAGEPROG << 16));
1154 clrsetbits_le32(&info->reg->flash_nf_count, GENMASK(1, 0),
1155 REG_CMD_COUNT_3TOGO);
1156 }
1157 ret = nand_rw_oob(mtd, chip, page, 1, 1);
1158
1159 /* Reset FIFO */
1160 clrsetbits_le32(&info->reg->flash_nf_ecc_reset,
1161 GENMASK(31, 0), ECC_RESET_ALL);
1162
1163 return ret;
1164 }
1165
1166 /**
1167 * Decode NAND parameters from the device tree
1168 *
1169 * @param dev Driver model device
1170 * @param config Device tree NAND configuration
1171 */
fdt_decode_nand(struct udevice * dev,struct nand_drv * info)1172 static int fdt_decode_nand(struct udevice *dev, struct nand_drv *info)
1173 {
1174 int ecc_strength;
1175
1176 info->reg = (struct nand_ctlr *)dev_read_addr(dev);
1177 info->dma_glb = (struct dma_global *)dev_read_addr_index(dev, 1);
1178 info->dma_nand = (struct dma_ssp *)dev_read_addr_index(dev, 2);
1179 info->config.enabled = dev_read_enabled(dev);
1180 ecc_strength = dev_read_u32_default(dev, "nand-ecc-strength", 16);
1181 info->flash_base =
1182 dev_read_u32_default(dev, "nand_flash_base_addr", NAND_BASE_ADDR);
1183
1184 switch (ecc_strength) {
1185 case ECC_STRENGTH_8:
1186 info->config.nand_ecc_strength = ECC_STRENGTH_8;
1187 break;
1188 case ECC_STRENGTH_16:
1189 info->config.nand_ecc_strength = ECC_STRENGTH_16;
1190 break;
1191 case ECC_STRENGTH_24:
1192 info->config.nand_ecc_strength = ECC_STRENGTH_24;
1193 break;
1194 case ECC_STRENGTH_40:
1195 info->config.nand_ecc_strength = ECC_STRENGTH_40;
1196 break;
1197 default:
1198 info->config.nand_ecc_strength = ECC_STRENGTH_16;
1199 }
1200
1201 return 0;
1202 }
1203
1204 /**
1205 * config flash type
1206 *
1207 * @param chip nand chip info structure
1208 */
nand_config_flash_type(struct nand_chip * nand)1209 static void nand_config_flash_type(struct nand_chip *nand)
1210 {
1211 struct nand_drv *info =
1212 (struct nand_drv *)nand_get_controller_data(nand);
1213 struct mtd_info *mtd = nand_to_mtd(nand);
1214
1215 switch (mtd->writesize) {
1216 case WRITE_SIZE_512:
1217 clrsetbits_le32(&info->reg->flash_type, GENMASK(31, 0),
1218 FLASH_PIN | FLASH_TYPE_512);
1219 break;
1220 case WRITE_SIZE_2048:
1221 clrsetbits_le32(&info->reg->flash_type, GENMASK(31, 0),
1222 FLASH_PIN | FLASH_TYPE_2K);
1223 break;
1224 case WRITE_SIZE_4096:
1225 clrsetbits_le32(&info->reg->flash_type, GENMASK(31, 0),
1226 FLASH_PIN | FLASH_TYPE_4K);
1227 break;
1228 case WRITE_SIZE_8192:
1229 clrsetbits_le32(&info->reg->flash_type, GENMASK(31, 0),
1230 FLASH_PIN | FLASH_TYPE_8K);
1231 break;
1232 default:
1233 pr_err("Unsupported page size(0x%x)!", nand->ecc.size);
1234 }
1235 }
1236
1237 /**
1238 * config oob layout
1239 *
1240 * @param chip nand chip info structure
1241 * @return 0 when successfully completed
1242 * -EINVAL when ECC bytes exceed OOB size
1243 */
nand_config_oob_layout(struct nand_chip * nand)1244 static int nand_config_oob_layout(struct nand_chip *nand)
1245 {
1246 int i, ecc_start_offset;
1247 struct mtd_info *mtd = nand_to_mtd(nand);
1248
1249 /* Calculate byte count for ECC */
1250 eccoob.eccbytes = mtd->writesize / nand->ecc.size * nand->ecc.bytes;
1251
1252 if (mtd->oobsize < eccoob.eccbytes) {
1253 pr_err("Spare area(%d) too small for BCH%d\n", nand->ecc.bytes,
1254 nand->ecc.strength / 8);
1255 pr_err("page_sz: %d\n", nand->ecc.size);
1256 pr_err("oob_sz: %d\n", nand->ecc.bytes);
1257 return -EINVAL;
1258 }
1259
1260 /* Update OOB layout */
1261 ecc_start_offset = mtd->oobsize - eccoob.eccbytes;
1262 memset(eccoob.eccpos, 0, sizeof(eccoob.eccpos));
1263 for (i = 0; i < eccoob.eccbytes; ++i)
1264 eccoob.eccpos[i] = i + ecc_start_offset;
1265
1266 /* Unused spare area
1267 * OOB[0] is bad block marker.
1268 * Extra two byte is reserved as
1269 * erase marker just right before ECC code.
1270 */
1271 eccoob.oobavail = nand->ecc.bytes - eccoob.eccbytes - 2;
1272 eccoob.oobfree[0].offset = 2;
1273 eccoob.oobfree[0].length =
1274 mtd->oobsize - eccoob.eccbytes - eccoob.oobfree[0].offset - 1;
1275
1276 return 0;
1277 }
1278
ca_nand_probe(struct udevice * dev)1279 static int ca_nand_probe(struct udevice *dev)
1280 {
1281 struct ca_nand_info *ca_nand = dev_get_priv(dev);
1282 struct nand_chip *nand = &ca_nand->nand_chip;
1283 struct nand_drv *info = &ca_nand->nand_ctrl;
1284 struct fdt_nand *config = &info->config;
1285 struct mtd_info *our_mtd;
1286 int ret;
1287
1288 if (fdt_decode_nand(dev, info)) {
1289 printf("Could not decode nand-flash in device tree\n");
1290 return -1;
1291 }
1292 if (!config->enabled)
1293 return -1;
1294
1295 nand->ecc.mode = NAND_ECC_HW;
1296 nand->ecc.layout = &eccoob;
1297
1298 nand->cmdfunc = ca_nand_command;
1299 nand->read_byte = read_byte;
1300 nand->read_buf = read_buf;
1301 nand->ecc.read_page = nand_read_page_hwecc;
1302 nand->ecc.write_page = nand_write_page_hwecc;
1303 nand->ecc.read_page_raw = nand_read_page_raw;
1304 nand->ecc.write_page_raw = nand_write_page_raw;
1305 nand->ecc.read_oob = nand_read_oob;
1306 nand->ecc.write_oob = nand_write_oob;
1307 nand->ecc.strength = config->nand_ecc_strength;
1308 nand->select_chip = nand_select_chip;
1309 nand->dev_ready = nand_dev_ready;
1310 nand_set_controller_data(nand, &ca_nand->nand_ctrl);
1311
1312 /* Disable subpage writes as we do not provide ecc->hwctl */
1313 nand->options |= NAND_NO_SUBPAGE_WRITE | NAND_SKIP_BBTSCAN;
1314
1315 /* Configure flash type as P-NAND */
1316 clrsetbits_le32(&info->reg->flash_type, FLASH_PIN,
1317 FLASH_TYPE_4K | FLASH_SIZE_436OOB);
1318 config->width = FLASH_WIDTH;
1319
1320 our_mtd = nand_to_mtd(nand);
1321 ret = nand_scan_ident(our_mtd, CONFIG_SYS_NAND_MAX_CHIPS, NULL);
1322 if (ret)
1323 return ret;
1324
1325 nand->ecc.size = BCH_DATA_UNIT;
1326 nand->ecc.bytes = BCH_GF_PARAM_M * (nand->ecc.strength / 8);
1327
1328 /* Reconfig flash type according to ONFI */
1329 nand_config_flash_type(nand);
1330
1331 ret = set_bus_width_page_size(our_mtd);
1332 if (ret)
1333 return ret;
1334
1335 /* Set the bad block position */
1336 nand->badblockpos =
1337 our_mtd->writesize >
1338 512 ? NAND_LARGE_BADBLOCK_POS : NAND_SMALL_BADBLOCK_POS;
1339
1340 /* Arrange OOB layout */
1341 ret = nand_config_oob_layout(nand);
1342 if (ret)
1343 return ret;
1344
1345 /* Init DMA descriptor ring */
1346 ret = init_nand_dma(nand);
1347 if (ret)
1348 return ret;
1349
1350 ret = nand_scan_tail(our_mtd);
1351 if (ret)
1352 return ret;
1353
1354 ret = nand_register(0, our_mtd);
1355 if (ret) {
1356 dev_err(dev, "Failed to register MTD: %d\n", ret);
1357 return ret;
1358 }
1359
1360 ret = set_bus_width_page_size(our_mtd);
1361 if (ret)
1362 return ret;
1363
1364 printf("P-NAND : %s\n", our_mtd->name);
1365 printf("Chip Size: %lldMB\n", nand->chipsize / (1024 * 1024));
1366 printf("Block Size: %dKB\n", our_mtd->erasesize / 1024);
1367 printf("Page Size: %dB\n", our_mtd->writesize);
1368 printf("OOB Size: %dB\n", our_mtd->oobsize);
1369
1370 return 0;
1371 }
1372
1373 U_BOOT_DRIVER(cortina_nand) = {
1374 .name = "CA-PNAND",
1375 .id = UCLASS_MTD,
1376 .of_match = cortina_nand_dt_ids,
1377 .probe = ca_nand_probe,
1378 .priv_auto = sizeof(struct ca_nand_info),
1379 };
1380
board_nand_init(void)1381 void board_nand_init(void)
1382 {
1383 struct udevice *dev;
1384 int ret;
1385
1386 ret = uclass_get_device_by_driver(UCLASS_MTD,
1387 DM_DRIVER_GET(cortina_nand), &dev);
1388 if (ret && ret != -ENODEV)
1389 pr_err("Failed to initialize %s. (error %d)\n", dev->name, ret);
1390 }
1391