1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * FSL UPM NAND driver
4 *
5 * Copyright (C) 2007 MontaVista Software, Inc.
6 * Anton Vorontsov <avorontsov@ru.mvista.com>
7 */
8
9 #include <config.h>
10 #include <common.h>
11 #include <log.h>
12 #include <asm/io.h>
13 #include <linux/delay.h>
14 #include <linux/errno.h>
15 #include <linux/mtd/mtd.h>
16 #include <linux/mtd/fsl_upm.h>
17 #include <nand.h>
18
fsl_upm_start_pattern(struct fsl_upm * upm,u32 pat_offset)19 static void fsl_upm_start_pattern(struct fsl_upm *upm, u32 pat_offset)
20 {
21 clrsetbits_be32(upm->mxmr, MxMR_MAD_MSK, MxMR_OP_RUNP | pat_offset);
22 (void)in_be32(upm->mxmr);
23 }
24
fsl_upm_end_pattern(struct fsl_upm * upm)25 static void fsl_upm_end_pattern(struct fsl_upm *upm)
26 {
27 clrbits_be32(upm->mxmr, MxMR_OP_RUNP);
28
29 while (in_be32(upm->mxmr) & MxMR_OP_RUNP)
30 eieio();
31 }
32
fsl_upm_run_pattern(struct fsl_upm * upm,int width,void __iomem * io_addr,u32 mar)33 static void fsl_upm_run_pattern(struct fsl_upm *upm, int width,
34 void __iomem *io_addr, u32 mar)
35 {
36 out_be32(upm->mar, mar);
37 (void)in_be32(upm->mar);
38 switch (width) {
39 case 8:
40 out_8(io_addr, 0x0);
41 break;
42 case 16:
43 out_be16(io_addr, 0x0);
44 break;
45 case 32:
46 out_be32(io_addr, 0x0);
47 break;
48 }
49 }
50
fun_wait(struct fsl_upm_nand * fun)51 static void fun_wait(struct fsl_upm_nand *fun)
52 {
53 if (fun->dev_ready) {
54 while (!fun->dev_ready(fun->chip_nr))
55 debug("unexpected busy state\n");
56 } else {
57 /*
58 * If the R/B pin is not connected,
59 * a short delay is necessary.
60 */
61 udelay(1);
62 }
63 }
64
65 #if CONFIG_SYS_NAND_MAX_CHIPS > 1
fun_select_chip(struct mtd_info * mtd,int chip_nr)66 static void fun_select_chip(struct mtd_info *mtd, int chip_nr)
67 {
68 struct nand_chip *chip = mtd_to_nand(mtd);
69 struct fsl_upm_nand *fun = nand_get_controller_data(chip);
70
71 if (chip_nr >= 0) {
72 fun->chip_nr = chip_nr;
73 chip->IO_ADDR_R = chip->IO_ADDR_W =
74 fun->upm.io_addr + fun->chip_offset * chip_nr;
75 } else if (chip_nr == -1) {
76 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
77 }
78 }
79 #endif
80
fun_cmd_ctrl(struct mtd_info * mtd,int cmd,unsigned int ctrl)81 static void fun_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
82 {
83 struct nand_chip *chip = mtd_to_nand(mtd);
84 struct fsl_upm_nand *fun = nand_get_controller_data(chip);
85 void __iomem *io_addr;
86 u32 mar;
87
88 if (!(ctrl & fun->last_ctrl)) {
89 fsl_upm_end_pattern(&fun->upm);
90
91 if (cmd == NAND_CMD_NONE)
92 return;
93
94 fun->last_ctrl = ctrl & (NAND_ALE | NAND_CLE);
95 }
96
97 if (ctrl & NAND_CTRL_CHANGE) {
98 if (ctrl & NAND_ALE)
99 fsl_upm_start_pattern(&fun->upm, fun->upm_addr_offset);
100 else if (ctrl & NAND_CLE)
101 fsl_upm_start_pattern(&fun->upm, fun->upm_cmd_offset);
102 }
103
104 mar = cmd << (32 - fun->width);
105 io_addr = fun->upm.io_addr;
106 #if CONFIG_SYS_NAND_MAX_CHIPS > 1
107 if (fun->chip_nr > 0) {
108 io_addr += fun->chip_offset * fun->chip_nr;
109 if (fun->upm_mar_chip_offset)
110 mar |= fun->upm_mar_chip_offset * fun->chip_nr;
111 }
112 #endif
113 fsl_upm_run_pattern(&fun->upm, fun->width, io_addr, mar);
114
115 /*
116 * Some boards/chips needs this. At least the MPC8360E-RDK
117 * needs it. Probably weird chip, because I don't see any
118 * need for this on MPC8555E + Samsung K9F1G08U0A. Usually
119 * here are 0-2 unexpected busy states per block read.
120 */
121 if (fun->wait_flags & FSL_UPM_WAIT_RUN_PATTERN)
122 fun_wait(fun);
123 }
124
upm_nand_read_byte(struct mtd_info * mtd)125 static u8 upm_nand_read_byte(struct mtd_info *mtd)
126 {
127 struct nand_chip *chip = mtd_to_nand(mtd);
128
129 return in_8(chip->IO_ADDR_R);
130 }
131
upm_nand_write_buf(struct mtd_info * mtd,const u_char * buf,int len)132 static void upm_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
133 {
134 int i;
135 struct nand_chip *chip = mtd_to_nand(mtd);
136 struct fsl_upm_nand *fun = nand_get_controller_data(chip);
137
138 for (i = 0; i < len; i++) {
139 out_8(chip->IO_ADDR_W, buf[i]);
140 if (fun->wait_flags & FSL_UPM_WAIT_WRITE_BYTE)
141 fun_wait(fun);
142 }
143
144 if (fun->wait_flags & FSL_UPM_WAIT_WRITE_BUFFER)
145 fun_wait(fun);
146 }
147
upm_nand_read_buf(struct mtd_info * mtd,u_char * buf,int len)148 static void upm_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
149 {
150 int i;
151 struct nand_chip *chip = mtd_to_nand(mtd);
152
153 for (i = 0; i < len; i++)
154 buf[i] = in_8(chip->IO_ADDR_R);
155 }
156
nand_dev_ready(struct mtd_info * mtd)157 static int nand_dev_ready(struct mtd_info *mtd)
158 {
159 struct nand_chip *chip = mtd_to_nand(mtd);
160 struct fsl_upm_nand *fun = nand_get_controller_data(chip);
161
162 return fun->dev_ready(fun->chip_nr);
163 }
164
fsl_upm_nand_init(struct nand_chip * chip,struct fsl_upm_nand * fun)165 int fsl_upm_nand_init(struct nand_chip *chip, struct fsl_upm_nand *fun)
166 {
167 if (fun->width != 8 && fun->width != 16 && fun->width != 32)
168 return -ENOSYS;
169
170 fun->last_ctrl = NAND_CLE;
171
172 nand_set_controller_data(chip, fun);
173 chip->chip_delay = fun->chip_delay;
174 chip->ecc.mode = NAND_ECC_SOFT;
175 chip->cmd_ctrl = fun_cmd_ctrl;
176 #if CONFIG_SYS_NAND_MAX_CHIPS > 1
177 chip->select_chip = fun_select_chip;
178 #endif
179 chip->read_byte = upm_nand_read_byte;
180 chip->read_buf = upm_nand_read_buf;
181 chip->write_buf = upm_nand_write_buf;
182 if (fun->dev_ready)
183 chip->dev_ready = nand_dev_ready;
184
185 return 0;
186 }
187