1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2017-2018 NXP 4 */ 5 6 #ifndef __LS1088_COMMON_H 7 #define __LS1088_COMMON_H 8 9 /* SPL build */ 10 #ifdef CONFIG_SPL_BUILD 11 #define SPL_NO_BOARDINFO 12 #define SPL_NO_QIXIS 13 #define SPL_NO_PCI 14 #define SPL_NO_ENV 15 #define SPL_NO_RTC 16 #define SPL_NO_USB 17 #define SPL_NO_SATA 18 #define SPL_NO_QSPI 19 #define SPL_NO_IFC 20 #undef CONFIG_DISPLAY_CPUINFO 21 #endif 22 23 #define CONFIG_REMAKE_ELF 24 25 #include <asm/arch/stream_id_lsch3.h> 26 #include <asm/arch/config.h> 27 #include <asm/arch/soc.h> 28 29 #define LS1088ARDB_PB_BOARD 0x4A 30 /* Link Definitions */ 31 #ifdef CONFIG_TFABOOT 32 #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE 33 #else 34 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) 35 #endif 36 37 /* Link Definitions */ 38 #define CONFIG_SYS_FSL_QSPI_BASE 0x20000000 39 40 #define CONFIG_SKIP_LOWLEVEL_INIT 41 42 #define CONFIG_VERY_BIG_RAM 43 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL 44 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 45 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 46 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL 47 #define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 1 48 /* 49 * SMP Definitinos 50 */ 51 #define CPU_RELEASE_ADDR secondary_boot_addr 52 53 /* Size of malloc() pool */ 54 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024) 55 56 /* GPIO */ 57 #ifdef CONFIG_DM_GPIO 58 #ifndef CONFIG_MPC8XXX_GPIO 59 #define CONFIG_MPC8XXX_GPIO 60 #endif 61 #endif 62 63 /* I2C */ 64 #if !CONFIG_IS_ENABLED(DM_I2C) 65 #define CONFIG_SYS_I2C 66 #endif 67 68 69 /* Serial Port */ 70 #define CONFIG_SYS_NS16550_SERIAL 71 #define CONFIG_SYS_NS16550_REG_SIZE 1 72 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2) 73 74 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 75 76 #if !defined(SPL_NO_IFC) || defined(CONFIG_TARGET_LS1088AQDS) 77 /* IFC */ 78 #define CONFIG_FSL_IFC 79 #endif 80 81 /* 82 * During booting, IFC is mapped at the region of 0x30000000. 83 * But this region is limited to 256MB. To accommodate NOR, promjet 84 * and FPGA. This region is divided as below: 85 * 0x30000000 - 0x37ffffff : 128MB : NOR flash 86 * 0x38000000 - 0x3BFFFFFF : 64MB : Promjet 87 * 0x3C000000 - 0x40000000 : 64MB : FPGA etc 88 * 89 * To accommodate bigger NOR flash and other devices, we will map IFC 90 * chip selects to as below: 91 * 0x5_1000_0000..0x5_1fff_ffff Memory Hole 92 * 0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB) 93 * 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB 94 * 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet) 95 * 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet) 96 * 97 * For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation. 98 * CONFIG_SYS_FLASH_BASE has the final address (core view) 99 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view) 100 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address 101 * CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting 102 */ 103 104 #define CONFIG_SYS_FLASH_BASE 0x580000000ULL 105 #define CONFIG_SYS_FLASH_BASE_PHYS 0x80000000 106 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 107 108 #define CONFIG_SYS_FLASH1_BASE_PHYS 0xC0000000 109 #define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000 110 111 #ifndef __ASSEMBLY__ 112 unsigned long long get_qixis_addr(void); 113 #endif 114 115 #define QIXIS_BASE get_qixis_addr() 116 #define QIXIS_BASE_PHYS 0x20000000 117 #define QIXIS_BASE_PHYS_EARLY 0xC000000 118 119 120 #define CONFIG_SYS_NAND_BASE 0x530000000ULL 121 #define CONFIG_SYS_NAND_BASE_PHYS 0x30000000 122 123 124 /* MC firmware */ 125 /* TODO Actual DPL max length needs to be confirmed with the MC FW team */ 126 #define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000 127 #define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000 128 #define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000 129 #define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000 130 #define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000 131 #define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000 132 133 /* Define phy_reset function to boot the MC based on mcinitcmd. 134 * This happens late enough to properly fixup u-boot env MAC addresses. 135 */ 136 #define CONFIG_RESET_PHY_R 137 138 /* 139 * Carve out a DDR region which will not be used by u-boot/Linux 140 * 141 * It will be used by MC and Debug Server. The MC region must be 142 * 512MB aligned, so the min size to hide is 512MB. 143 */ 144 145 #if defined(CONFIG_FSL_MC_ENET) 146 #define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (128UL * 1024 * 1024) 147 #endif 148 149 /* Miscellaneous configurable options */ 150 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) 151 152 /* SATA */ 153 #ifdef CONFIG_SCSI 154 #define CONFIG_SCSI_AHCI_PLAT 155 #define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1 156 157 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 158 #define CONFIG_SYS_SCSI_MAX_LUN 1 159 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ 160 CONFIG_SYS_SCSI_MAX_LUN) 161 #endif 162 163 /* Physical Memory Map */ 164 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 165 166 #define CONFIG_HWCONFIG 167 #define HWCONFIG_BUFFER_SIZE 128 168 169 /* #define CONFIG_DISPLAY_CPUINFO */ 170 171 #ifndef SPL_NO_ENV 172 /* Initial environment variables */ 173 #define CONFIG_EXTRA_ENV_SETTINGS \ 174 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 175 "loadaddr=0x80100000\0" \ 176 "kernel_addr=0x100000\0" \ 177 "ramdisk_addr=0x800000\0" \ 178 "ramdisk_size=0x2000000\0" \ 179 "fdt_high=0xa0000000\0" \ 180 "initrd_high=0xffffffffffffffff\0" \ 181 "kernel_start=0x581000000\0" \ 182 "kernel_load=0xa0000000\0" \ 183 "kernel_size=0x2800000\0" \ 184 "console=ttyAMA0,38400n8\0" \ 185 "mcinitcmd=fsl_mc start mc 0x580a00000" \ 186 " 0x580e00000 \0" 187 188 #ifndef CONFIG_TFABOOT 189 #if defined(CONFIG_QSPI_BOOT) 190 #define CONFIG_BOOTCOMMAND "sf probe 0:0;" \ 191 "sf read 0x80001000 0xd00000 0x100000;"\ 192 " fsl_mc lazyapply dpl 0x80001000 &&" \ 193 " sf read $kernel_load $kernel_start" \ 194 " $kernel_size && bootm $kernel_load" 195 #elif defined(CONFIG_SD_BOOT) 196 #define CONFIG_BOOTCOMMAND "mmcinfo;mmc read 0x80001000 0x6800 0x800;"\ 197 " fsl_mc lazyapply dpl 0x80001000 &&" \ 198 " mmc read $kernel_load $kernel_start" \ 199 " $kernel_size && bootm $kernel_load" 200 #else /* NOR BOOT*/ 201 #define CONFIG_BOOTCOMMAND "fsl_mc lazyapply dpl 0x580d00000 &&" \ 202 " cp.b $kernel_start $kernel_load" \ 203 " $kernel_size && bootm $kernel_load" 204 #endif 205 #endif /* CONFIG_TFABOOT */ 206 #endif 207 208 /* Monitor Command Prompt */ 209 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 210 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 211 sizeof(CONFIG_SYS_PROMPT) + 16) 212 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */ 213 #define CONFIG_SYS_MAXARGS 64 /* max command args */ 214 215 #ifdef CONFIG_SPL 216 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 217 #define CONFIG_SPL_BSS_MAX_SIZE 0x00100000 218 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" 219 #define CONFIG_SPL_MAX_SIZE 0x16000 220 #define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0) 221 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 222 223 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000 224 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000 225 226 #ifdef CONFIG_NXP_ESBC 227 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) 228 /* 229 * HDR would be appended at end of image and copied to DDR along 230 * with U-Boot image. Here u-boot max. size is 512K. So if binary 231 * size increases then increase this size in case of secure boot as 232 * it uses raw u-boot image instead of fit image. 233 */ 234 #define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE) 235 #else 236 #define CONFIG_SYS_MONITOR_LEN 0x100000 237 #endif /* ifdef CONFIG_NXP_ESBC */ 238 239 #endif 240 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 241 242 #endif /* __LS1088_COMMON_H */ 243