1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2008-2014 Freescale Semiconductor, Inc.
4 * Copyright 2018 NXP
5 *
6 * Based on CAAM driver in drivers/crypto/caam in Linux
7 */
8
9 #include <common.h>
10 #include <cpu_func.h>
11 #include <linux/kernel.h>
12 #include <log.h>
13 #include <malloc.h>
14 #include "fsl_sec.h"
15 #include "jr.h"
16 #include "jobdesc.h"
17 #include "desc_constr.h"
18 #include <time.h>
19 #include <asm/cache.h>
20 #ifdef CONFIG_FSL_CORENET
21 #include <asm/cache.h>
22 #include <asm/fsl_pamu.h>
23 #endif
24 #include <dm/lists.h>
25 #include <linux/delay.h>
26
27 #define CIRC_CNT(head, tail, size) (((head) - (tail)) & (size - 1))
28 #define CIRC_SPACE(head, tail, size) CIRC_CNT((tail), (head) + 1, (size))
29
30 uint32_t sec_offset[CONFIG_SYS_FSL_MAX_NUM_OF_SEC] = {
31 0,
32 #if defined(CONFIG_ARCH_C29X)
33 CONFIG_SYS_FSL_SEC_IDX_OFFSET,
34 2 * CONFIG_SYS_FSL_SEC_IDX_OFFSET
35 #endif
36 };
37
38 #define SEC_ADDR(idx) \
39 (ulong)((CONFIG_SYS_FSL_SEC_ADDR + sec_offset[idx]))
40
41 #define SEC_JR0_ADDR(idx) \
42 (ulong)(SEC_ADDR(idx) + \
43 (CONFIG_SYS_FSL_JR0_OFFSET - CONFIG_SYS_FSL_SEC_OFFSET))
44
45 struct jobring jr0[CONFIG_SYS_FSL_MAX_NUM_OF_SEC];
46
start_jr0(uint8_t sec_idx)47 static inline void start_jr0(uint8_t sec_idx)
48 {
49 ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
50 u32 ctpr_ms = sec_in32(&sec->ctpr_ms);
51 u32 scfgr = sec_in32(&sec->scfgr);
52
53 if (ctpr_ms & SEC_CTPR_MS_VIRT_EN_INCL) {
54 /* VIRT_EN_INCL = 1 & VIRT_EN_POR = 1 or
55 * VIRT_EN_INCL = 1 & VIRT_EN_POR = 0 & SEC_SCFGR_VIRT_EN = 1
56 */
57 if ((ctpr_ms & SEC_CTPR_MS_VIRT_EN_POR) ||
58 (scfgr & SEC_SCFGR_VIRT_EN))
59 sec_out32(&sec->jrstartr, CONFIG_JRSTARTR_JR0);
60 } else {
61 /* VIRT_EN_INCL = 0 && VIRT_EN_POR_VALUE = 1 */
62 if (ctpr_ms & SEC_CTPR_MS_VIRT_EN_POR)
63 sec_out32(&sec->jrstartr, CONFIG_JRSTARTR_JR0);
64 }
65 }
66
jr_reset_liodn(uint8_t sec_idx)67 static inline void jr_reset_liodn(uint8_t sec_idx)
68 {
69 ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
70 sec_out32(&sec->jrliodnr[0].ls, 0);
71 }
72
jr_disable_irq(uint8_t sec_idx)73 static inline void jr_disable_irq(uint8_t sec_idx)
74 {
75 struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
76 uint32_t jrcfg = sec_in32(®s->jrcfg1);
77
78 jrcfg = jrcfg | JR_INTMASK;
79
80 sec_out32(®s->jrcfg1, jrcfg);
81 }
82
jr_initregs(uint8_t sec_idx)83 static void jr_initregs(uint8_t sec_idx)
84 {
85 struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
86 struct jobring *jr = &jr0[sec_idx];
87 caam_dma_addr_t ip_base = virt_to_phys((void *)jr->input_ring);
88 caam_dma_addr_t op_base = virt_to_phys((void *)jr->output_ring);
89
90 #ifdef CONFIG_CAAM_64BIT
91 sec_out32(®s->irba_h, ip_base >> 32);
92 #else
93 sec_out32(®s->irba_h, 0x0);
94 #endif
95 sec_out32(®s->irba_l, (uint32_t)ip_base);
96 #ifdef CONFIG_CAAM_64BIT
97 sec_out32(®s->orba_h, op_base >> 32);
98 #else
99 sec_out32(®s->orba_h, 0x0);
100 #endif
101 sec_out32(®s->orba_l, (uint32_t)op_base);
102 sec_out32(®s->ors, JR_SIZE);
103 sec_out32(®s->irs, JR_SIZE);
104
105 if (!jr->irq)
106 jr_disable_irq(sec_idx);
107 }
108
jr_init(uint8_t sec_idx)109 static int jr_init(uint8_t sec_idx)
110 {
111 struct jobring *jr = &jr0[sec_idx];
112
113 memset(jr, 0, sizeof(struct jobring));
114
115 jr->jq_id = DEFAULT_JR_ID;
116 jr->irq = DEFAULT_IRQ;
117
118 #ifdef CONFIG_FSL_CORENET
119 jr->liodn = DEFAULT_JR_LIODN;
120 #endif
121 jr->size = JR_SIZE;
122 jr->input_ring = (caam_dma_addr_t *)memalign(ARCH_DMA_MINALIGN,
123 JR_SIZE * sizeof(caam_dma_addr_t));
124 if (!jr->input_ring)
125 return -1;
126
127 jr->op_size = roundup(JR_SIZE * sizeof(struct op_ring),
128 ARCH_DMA_MINALIGN);
129 jr->output_ring =
130 (struct op_ring *)memalign(ARCH_DMA_MINALIGN, jr->op_size);
131 if (!jr->output_ring)
132 return -1;
133
134 memset(jr->input_ring, 0, JR_SIZE * sizeof(caam_dma_addr_t));
135 memset(jr->output_ring, 0, jr->op_size);
136
137 start_jr0(sec_idx);
138
139 jr_initregs(sec_idx);
140
141 return 0;
142 }
143
jr_sw_cleanup(uint8_t sec_idx)144 static int jr_sw_cleanup(uint8_t sec_idx)
145 {
146 struct jobring *jr = &jr0[sec_idx];
147
148 jr->head = 0;
149 jr->tail = 0;
150 jr->read_idx = 0;
151 jr->write_idx = 0;
152 memset(jr->info, 0, sizeof(jr->info));
153 memset(jr->input_ring, 0, jr->size * sizeof(caam_dma_addr_t));
154 memset(jr->output_ring, 0, jr->size * sizeof(struct op_ring));
155
156 return 0;
157 }
158
jr_hw_reset(uint8_t sec_idx)159 static int jr_hw_reset(uint8_t sec_idx)
160 {
161 struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
162 uint32_t timeout = 100000;
163 uint32_t jrint, jrcr;
164
165 sec_out32(®s->jrcr, JRCR_RESET);
166 do {
167 jrint = sec_in32(®s->jrint);
168 } while (((jrint & JRINT_ERR_HALT_MASK) ==
169 JRINT_ERR_HALT_INPROGRESS) && --timeout);
170
171 jrint = sec_in32(®s->jrint);
172 if (((jrint & JRINT_ERR_HALT_MASK) !=
173 JRINT_ERR_HALT_INPROGRESS) && timeout == 0)
174 return -1;
175
176 timeout = 100000;
177 sec_out32(®s->jrcr, JRCR_RESET);
178 do {
179 jrcr = sec_in32(®s->jrcr);
180 } while ((jrcr & JRCR_RESET) && --timeout);
181
182 if (timeout == 0)
183 return -1;
184
185 return 0;
186 }
187
188 /* -1 --- error, can't enqueue -- no space available */
jr_enqueue(uint32_t * desc_addr,void (* callback)(uint32_t status,void * arg),void * arg,uint8_t sec_idx)189 static int jr_enqueue(uint32_t *desc_addr,
190 void (*callback)(uint32_t status, void *arg),
191 void *arg, uint8_t sec_idx)
192 {
193 struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
194 struct jobring *jr = &jr0[sec_idx];
195 int head = jr->head;
196 uint32_t desc_word;
197 int length = desc_len(desc_addr);
198 int i;
199 #ifdef CONFIG_CAAM_64BIT
200 uint32_t *addr_hi, *addr_lo;
201 #endif
202
203 /* The descriptor must be submitted to SEC block as per endianness
204 * of the SEC Block.
205 * So, if the endianness of Core and SEC block is different, each word
206 * of the descriptor will be byte-swapped.
207 */
208 for (i = 0; i < length; i++) {
209 desc_word = desc_addr[i];
210 sec_out32((uint32_t *)&desc_addr[i], desc_word);
211 }
212
213 caam_dma_addr_t desc_phys_addr = virt_to_phys(desc_addr);
214
215 jr->info[head].desc_phys_addr = desc_phys_addr;
216 jr->info[head].callback = (void *)callback;
217 jr->info[head].arg = arg;
218 jr->info[head].op_done = 0;
219
220 unsigned long start = (unsigned long)&jr->info[head] &
221 ~(ARCH_DMA_MINALIGN - 1);
222 unsigned long end = ALIGN((unsigned long)&jr->info[head] +
223 sizeof(struct jr_info), ARCH_DMA_MINALIGN);
224 flush_dcache_range(start, end);
225
226 #ifdef CONFIG_CAAM_64BIT
227 /* Write the 64 bit Descriptor address on Input Ring.
228 * The 32 bit hign and low part of the address will
229 * depend on endianness of SEC block.
230 */
231 #ifdef CONFIG_SYS_FSL_SEC_LE
232 addr_lo = (uint32_t *)(&jr->input_ring[head]);
233 addr_hi = (uint32_t *)(&jr->input_ring[head]) + 1;
234 #elif defined(CONFIG_SYS_FSL_SEC_BE)
235 addr_hi = (uint32_t *)(&jr->input_ring[head]);
236 addr_lo = (uint32_t *)(&jr->input_ring[head]) + 1;
237 #endif /* ifdef CONFIG_SYS_FSL_SEC_LE */
238
239 sec_out32(addr_hi, (uint32_t)(desc_phys_addr >> 32));
240 sec_out32(addr_lo, (uint32_t)(desc_phys_addr));
241
242 #else
243 /* Write the 32 bit Descriptor address on Input Ring. */
244 sec_out32(&jr->input_ring[head], desc_phys_addr);
245 #endif /* ifdef CONFIG_CAAM_64BIT */
246
247 start = (unsigned long)&jr->input_ring[head] & ~(ARCH_DMA_MINALIGN - 1);
248 end = ALIGN((unsigned long)&jr->input_ring[head] +
249 sizeof(caam_dma_addr_t), ARCH_DMA_MINALIGN);
250 flush_dcache_range(start, end);
251
252 jr->head = (head + 1) & (jr->size - 1);
253
254 /* Invalidate output ring */
255 start = (unsigned long)jr->output_ring &
256 ~(ARCH_DMA_MINALIGN - 1);
257 end = ALIGN((unsigned long)jr->output_ring + jr->op_size,
258 ARCH_DMA_MINALIGN);
259 invalidate_dcache_range(start, end);
260
261 sec_out32(®s->irja, 1);
262
263 return 0;
264 }
265
jr_dequeue(int sec_idx)266 static int jr_dequeue(int sec_idx)
267 {
268 struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
269 struct jobring *jr = &jr0[sec_idx];
270 int head = jr->head;
271 int tail = jr->tail;
272 int idx, i, found;
273 void (*callback)(uint32_t status, void *arg);
274 void *arg = NULL;
275 #ifdef CONFIG_CAAM_64BIT
276 uint32_t *addr_hi, *addr_lo;
277 #else
278 uint32_t *addr;
279 #endif
280
281 while (sec_in32(®s->orsf) && CIRC_CNT(jr->head, jr->tail,
282 jr->size)) {
283
284 found = 0;
285
286 caam_dma_addr_t op_desc;
287 #ifdef CONFIG_CAAM_64BIT
288 /* Read the 64 bit Descriptor address from Output Ring.
289 * The 32 bit hign and low part of the address will
290 * depend on endianness of SEC block.
291 */
292 #ifdef CONFIG_SYS_FSL_SEC_LE
293 addr_lo = (uint32_t *)(&jr->output_ring[jr->tail].desc);
294 addr_hi = (uint32_t *)(&jr->output_ring[jr->tail].desc) + 1;
295 #elif defined(CONFIG_SYS_FSL_SEC_BE)
296 addr_hi = (uint32_t *)(&jr->output_ring[jr->tail].desc);
297 addr_lo = (uint32_t *)(&jr->output_ring[jr->tail].desc) + 1;
298 #endif /* ifdef CONFIG_SYS_FSL_SEC_LE */
299
300 op_desc = ((u64)sec_in32(addr_hi) << 32) |
301 ((u64)sec_in32(addr_lo));
302
303 #else
304 /* Read the 32 bit Descriptor address from Output Ring. */
305 addr = (uint32_t *)&jr->output_ring[jr->tail].desc;
306 op_desc = sec_in32(addr);
307 #endif /* ifdef CONFIG_CAAM_64BIT */
308
309 uint32_t status = sec_in32(&jr->output_ring[jr->tail].status);
310
311 for (i = 0; CIRC_CNT(head, tail + i, jr->size) >= 1; i++) {
312 idx = (tail + i) & (jr->size - 1);
313 if (op_desc == jr->info[idx].desc_phys_addr) {
314 found = 1;
315 break;
316 }
317 }
318
319 /* Error condition if match not found */
320 if (!found)
321 return -1;
322
323 jr->info[idx].op_done = 1;
324 callback = (void *)jr->info[idx].callback;
325 arg = jr->info[idx].arg;
326
327 /* When the job on tail idx gets done, increment
328 * tail till the point where job completed out of oredr has
329 * been taken into account
330 */
331 if (idx == tail)
332 do {
333 tail = (tail + 1) & (jr->size - 1);
334 } while (jr->info[tail].op_done);
335
336 jr->tail = tail;
337 jr->read_idx = (jr->read_idx + 1) & (jr->size - 1);
338
339 sec_out32(®s->orjr, 1);
340 jr->info[idx].op_done = 0;
341
342 callback(status, arg);
343 }
344
345 return 0;
346 }
347
desc_done(uint32_t status,void * arg)348 static void desc_done(uint32_t status, void *arg)
349 {
350 struct result *x = arg;
351 x->status = status;
352 #ifndef CONFIG_SPL_BUILD
353 caam_jr_strstatus(status);
354 #endif
355 x->done = 1;
356 }
357
run_descriptor_jr_idx(uint32_t * desc,uint8_t sec_idx)358 static inline int run_descriptor_jr_idx(uint32_t *desc, uint8_t sec_idx)
359 {
360 unsigned long long timeval = 0;
361 unsigned long long timeout = CONFIG_USEC_DEQ_TIMEOUT;
362 struct result op;
363 int ret = 0;
364
365 memset(&op, 0, sizeof(op));
366
367 ret = jr_enqueue(desc, desc_done, &op, sec_idx);
368 if (ret) {
369 debug("Error in SEC enq\n");
370 ret = JQ_ENQ_ERR;
371 goto out;
372 }
373
374 while (op.done != 1) {
375 udelay(1);
376 timeval += 1;
377
378 ret = jr_dequeue(sec_idx);
379 if (ret) {
380 debug("Error in SEC deq\n");
381 ret = JQ_DEQ_ERR;
382 goto out;
383 }
384
385 if (timeval > timeout) {
386 debug("SEC Dequeue timed out\n");
387 ret = JQ_DEQ_TO_ERR;
388 goto out;
389 }
390 }
391
392 if (op.status) {
393 debug("Error %x\n", op.status);
394 ret = op.status;
395 }
396 out:
397 return ret;
398 }
399
run_descriptor_jr(uint32_t * desc)400 int run_descriptor_jr(uint32_t *desc)
401 {
402 return run_descriptor_jr_idx(desc, 0);
403 }
404
jr_reset_sec(uint8_t sec_idx)405 static inline int jr_reset_sec(uint8_t sec_idx)
406 {
407 if (jr_hw_reset(sec_idx) < 0)
408 return -1;
409
410 /* Clean up the jobring structure maintained by software */
411 jr_sw_cleanup(sec_idx);
412
413 return 0;
414 }
415
jr_reset(void)416 int jr_reset(void)
417 {
418 return jr_reset_sec(0);
419 }
420
sec_reset_idx(uint8_t sec_idx)421 static inline int sec_reset_idx(uint8_t sec_idx)
422 {
423 ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
424 uint32_t mcfgr = sec_in32(&sec->mcfgr);
425 uint32_t timeout = 100000;
426
427 mcfgr |= MCFGR_SWRST;
428 sec_out32(&sec->mcfgr, mcfgr);
429
430 mcfgr |= MCFGR_DMA_RST;
431 sec_out32(&sec->mcfgr, mcfgr);
432 do {
433 mcfgr = sec_in32(&sec->mcfgr);
434 } while ((mcfgr & MCFGR_DMA_RST) == MCFGR_DMA_RST && --timeout);
435
436 if (timeout == 0)
437 return -1;
438
439 timeout = 100000;
440 do {
441 mcfgr = sec_in32(&sec->mcfgr);
442 } while ((mcfgr & MCFGR_SWRST) == MCFGR_SWRST && --timeout);
443
444 if (timeout == 0)
445 return -1;
446
447 return 0;
448 }
sec_reset(void)449 int sec_reset(void)
450 {
451 return sec_reset_idx(0);
452 }
453 #ifndef CONFIG_SPL_BUILD
deinstantiate_rng(u8 sec_idx,int state_handle_mask)454 static int deinstantiate_rng(u8 sec_idx, int state_handle_mask)
455 {
456 u32 *desc;
457 int sh_idx, ret = 0;
458 int desc_size = ALIGN(sizeof(u32) * 2, ARCH_DMA_MINALIGN);
459
460 desc = memalign(ARCH_DMA_MINALIGN, desc_size);
461 if (!desc) {
462 debug("cannot allocate RNG init descriptor memory\n");
463 return -ENOMEM;
464 }
465
466 for (sh_idx = 0; sh_idx < RNG4_MAX_HANDLES; sh_idx++) {
467 /*
468 * If the corresponding bit is set, then it means the state
469 * handle was initialized by us, and thus it needs to be
470 * deinitialized as well
471 */
472
473 if (state_handle_mask & RDSTA_IF(sh_idx)) {
474 /*
475 * Create the descriptor for deinstantating this state
476 * handle.
477 */
478 inline_cnstr_jobdesc_rng_deinstantiation(desc, sh_idx);
479 flush_dcache_range((unsigned long)desc,
480 (unsigned long)desc + desc_size);
481
482 ret = run_descriptor_jr_idx(desc, sec_idx);
483 if (ret) {
484 printf("SEC%u: RNG4 SH%d deinstantiation failed with error 0x%x\n",
485 sec_idx, sh_idx, ret);
486 ret = -EIO;
487 break;
488 }
489
490 printf("SEC%u: Deinstantiated RNG4 SH%d\n",
491 sec_idx, sh_idx);
492 }
493 }
494
495 free(desc);
496 return ret;
497 }
498
instantiate_rng(u8 sec_idx,int gen_sk)499 static int instantiate_rng(u8 sec_idx, int gen_sk)
500 {
501 u32 *desc;
502 u32 rdsta_val;
503 int ret = 0, sh_idx, size;
504 ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem *)SEC_ADDR(sec_idx);
505 struct rng4tst __iomem *rng =
506 (struct rng4tst __iomem *)&sec->rng;
507
508 desc = memalign(ARCH_DMA_MINALIGN, sizeof(uint32_t) * 6);
509 if (!desc) {
510 printf("cannot allocate RNG init descriptor memory\n");
511 return -1;
512 }
513
514 for (sh_idx = 0; sh_idx < RNG4_MAX_HANDLES; sh_idx++) {
515 /*
516 * If the corresponding bit is set, this state handle
517 * was initialized by somebody else, so it's left alone.
518 */
519 rdsta_val = sec_in32(&rng->rdsta);
520 if (rdsta_val & (RDSTA_IF(sh_idx))) {
521 if (rdsta_val & RDSTA_PR(sh_idx))
522 continue;
523
524 printf("SEC%u: RNG4 SH%d was instantiated w/o prediction resistance. Tearing it down\n",
525 sec_idx, sh_idx);
526
527 ret = deinstantiate_rng(sec_idx, RDSTA_IF(sh_idx));
528 if (ret)
529 break;
530 }
531
532 inline_cnstr_jobdesc_rng_instantiation(desc, sh_idx, gen_sk);
533 size = roundup(sizeof(uint32_t) * 6, ARCH_DMA_MINALIGN);
534 flush_dcache_range((unsigned long)desc,
535 (unsigned long)desc + size);
536
537 ret = run_descriptor_jr_idx(desc, sec_idx);
538
539 if (ret)
540 printf("SEC%u: RNG4 SH%d instantiation failed with error 0x%x\n",
541 sec_idx, sh_idx, ret);
542
543 rdsta_val = sec_in32(&rng->rdsta);
544 if (!(rdsta_val & RDSTA_IF(sh_idx))) {
545 free(desc);
546 return -1;
547 }
548
549 memset(desc, 0, sizeof(uint32_t) * 6);
550 }
551
552 free(desc);
553
554 return ret;
555 }
556
get_rng_vid(uint8_t sec_idx)557 static u8 get_rng_vid(uint8_t sec_idx)
558 {
559 ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
560 u8 vid;
561
562 if (caam_get_era() < 10) {
563 vid = (sec_in32(&sec->chavid_ls) & SEC_CHAVID_RNG_LS_MASK)
564 >> SEC_CHAVID_LS_RNG_SHIFT;
565 } else {
566 vid = (sec_in32(&sec->vreg.rng) & CHA_VER_VID_MASK)
567 >> CHA_VER_VID_SHIFT;
568 }
569
570 return vid;
571 }
572
573 /*
574 * By default, the TRNG runs for 200 clocks per sample;
575 * 1200 clocks per sample generates better entropy.
576 */
kick_trng(int ent_delay,uint8_t sec_idx)577 static void kick_trng(int ent_delay, uint8_t sec_idx)
578 {
579 ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem *)SEC_ADDR(sec_idx);
580 struct rng4tst __iomem *rng =
581 (struct rng4tst __iomem *)&sec->rng;
582 u32 val;
583
584 /* put RNG4 into program mode */
585 sec_setbits32(&rng->rtmctl, RTMCTL_PRGM);
586 /* rtsdctl bits 0-15 contain "Entropy Delay, which defines the
587 * length (in system clocks) of each Entropy sample taken
588 * */
589 val = sec_in32(&rng->rtsdctl);
590 val = (val & ~RTSDCTL_ENT_DLY_MASK) |
591 (ent_delay << RTSDCTL_ENT_DLY_SHIFT);
592 sec_out32(&rng->rtsdctl, val);
593 /* min. freq. count, equal to 1/4 of the entropy sample length */
594 sec_out32(&rng->rtfreqmin, ent_delay >> 2);
595 /* disable maximum frequency count */
596 sec_out32(&rng->rtfreqmax, RTFRQMAX_DISABLE);
597 /*
598 * select raw sampling in both entropy shifter
599 * and statistical checker
600 */
601 sec_setbits32(&rng->rtmctl, RTMCTL_SAMP_MODE_RAW_ES_SC);
602 /* put RNG4 into run mode */
603 sec_clrbits32(&rng->rtmctl, RTMCTL_PRGM);
604 }
605
rng_init(uint8_t sec_idx)606 static int rng_init(uint8_t sec_idx)
607 {
608 int ret, gen_sk, ent_delay = RTSDCTL_ENT_DLY_MIN;
609 ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem *)SEC_ADDR(sec_idx);
610 struct rng4tst __iomem *rng =
611 (struct rng4tst __iomem *)&sec->rng;
612 u32 inst_handles;
613
614 gen_sk = !(sec_in32(&rng->rdsta) & RDSTA_SKVN);
615 do {
616 inst_handles = sec_in32(&rng->rdsta) & RDSTA_MASK;
617
618 /*
619 * If either of the SH's were instantiated by somebody else
620 * then it is assumed that the entropy
621 * parameters are properly set and thus the function
622 * setting these (kick_trng(...)) is skipped.
623 * Also, if a handle was instantiated, do not change
624 * the TRNG parameters.
625 */
626 if (!inst_handles) {
627 kick_trng(ent_delay, sec_idx);
628 ent_delay += 400;
629 }
630 /*
631 * if instantiate_rng(...) fails, the loop will rerun
632 * and the kick_trng(...) function will modfiy the
633 * upper and lower limits of the entropy sampling
634 * interval, leading to a sucessful initialization of
635 * the RNG.
636 */
637 ret = instantiate_rng(sec_idx, gen_sk);
638 } while ((ret == -1) && (ent_delay < RTSDCTL_ENT_DLY_MAX));
639 if (ret) {
640 printf("SEC%u: Failed to instantiate RNG\n", sec_idx);
641 return ret;
642 }
643
644 /* Enable RDB bit so that RNG works faster */
645 sec_setbits32(&sec->scfgr, SEC_SCFGR_RDBENABLE);
646
647 return ret;
648 }
649 #endif
sec_init_idx(uint8_t sec_idx)650 int sec_init_idx(uint8_t sec_idx)
651 {
652 ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
653 uint32_t mcr = sec_in32(&sec->mcfgr);
654 int ret = 0;
655
656 #ifdef CONFIG_FSL_CORENET
657 uint32_t liodnr;
658 uint32_t liodn_ns;
659 uint32_t liodn_s;
660 #endif
661
662 if (!(sec_idx < CONFIG_SYS_FSL_MAX_NUM_OF_SEC)) {
663 printf("SEC%u: initialization failed\n", sec_idx);
664 return -1;
665 }
666
667 /*
668 * Modifying CAAM Read/Write Attributes
669 * For LS2080A
670 * For AXI Write - Cacheable, Write Back, Write allocate
671 * For AXI Read - Cacheable, Read allocate
672 * Only For LS2080a, to solve CAAM coherency issues
673 */
674 #ifdef CONFIG_ARCH_LS2080A
675 mcr = (mcr & ~MCFGR_AWCACHE_MASK) | (0xb << MCFGR_AWCACHE_SHIFT);
676 mcr = (mcr & ~MCFGR_ARCACHE_MASK) | (0x6 << MCFGR_ARCACHE_SHIFT);
677 #else
678 mcr = (mcr & ~MCFGR_AWCACHE_MASK) | (0x2 << MCFGR_AWCACHE_SHIFT);
679 #endif
680
681 #ifdef CONFIG_CAAM_64BIT
682 mcr |= (1 << MCFGR_PS_SHIFT);
683 #endif
684 sec_out32(&sec->mcfgr, mcr);
685
686 #ifdef CONFIG_FSL_CORENET
687 #ifdef CONFIG_SPL_BUILD
688 /*
689 * For SPL Build, Set the Liodns in SEC JR0 for
690 * creating PAMU entries corresponding to these.
691 * For normal build, these are set in set_liodns().
692 */
693 liodn_ns = CONFIG_SPL_JR0_LIODN_NS & JRNSLIODN_MASK;
694 liodn_s = CONFIG_SPL_JR0_LIODN_S & JRSLIODN_MASK;
695
696 liodnr = sec_in32(&sec->jrliodnr[0].ls) &
697 ~(JRNSLIODN_MASK | JRSLIODN_MASK);
698 liodnr = liodnr |
699 (liodn_ns << JRNSLIODN_SHIFT) |
700 (liodn_s << JRSLIODN_SHIFT);
701 sec_out32(&sec->jrliodnr[0].ls, liodnr);
702 #else
703 liodnr = sec_in32(&sec->jrliodnr[0].ls);
704 liodn_ns = (liodnr & JRNSLIODN_MASK) >> JRNSLIODN_SHIFT;
705 liodn_s = (liodnr & JRSLIODN_MASK) >> JRSLIODN_SHIFT;
706 #endif
707 #endif
708
709 ret = jr_init(sec_idx);
710 if (ret < 0) {
711 printf("SEC%u: initialization failed\n", sec_idx);
712 return -1;
713 }
714
715 #ifdef CONFIG_FSL_CORENET
716 ret = sec_config_pamu_table(liodn_ns, liodn_s);
717 if (ret < 0)
718 return -1;
719
720 pamu_enable();
721 #endif
722 #ifndef CONFIG_SPL_BUILD
723 if (get_rng_vid(sec_idx) >= 4) {
724 if (rng_init(sec_idx) < 0) {
725 printf("SEC%u: RNG instantiation failed\n", sec_idx);
726 return -1;
727 }
728
729 if (IS_ENABLED(CONFIG_DM_RNG)) {
730 ret = device_bind_driver(NULL, "caam-rng", "caam-rng",
731 NULL);
732 if (ret)
733 printf("Couldn't bind rng driver (%d)\n", ret);
734 }
735
736 printf("SEC%u: RNG instantiated\n", sec_idx);
737 }
738 #endif
739 return ret;
740 }
741
sec_init(void)742 int sec_init(void)
743 {
744 return sec_init_idx(0);
745 }
746