1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2005-2006 Atmel Corporation
4 */
5 #include <common.h>
6 #include <clk.h>
7 #include <cpu_func.h>
8 #include <dm.h>
9 #include <log.h>
10 #include <asm/global_data.h>
11 #include <linux/delay.h>
12
13 /*
14 * The u-boot networking stack is a little weird. It seems like the
15 * networking core allocates receive buffers up front without any
16 * regard to the hardware that's supposed to actually receive those
17 * packets.
18 *
19 * The MACB receives packets into 128-byte receive buffers, so the
20 * buffers allocated by the core isn't very practical to use. We'll
21 * allocate our own, but we need one such buffer in case a packet
22 * wraps around the DMA ring so that we have to copy it.
23 *
24 * Therefore, define CONFIG_SYS_RX_ETH_BUFFER to 1 in the board-specific
25 * configuration header. This way, the core allocates one RX buffer
26 * and one TX buffer, each of which can hold a ethernet packet of
27 * maximum size.
28 *
29 * For some reason, the networking core unconditionally specifies a
30 * 32-byte packet "alignment" (which really should be called
31 * "padding"). MACB shouldn't need that, but we'll refrain from any
32 * core modifications here...
33 */
34
35 #include <net.h>
36 #ifndef CONFIG_DM_ETH
37 #include <netdev.h>
38 #endif
39 #include <malloc.h>
40 #include <miiphy.h>
41
42 #include <linux/mii.h>
43 #include <asm/io.h>
44 #include <linux/dma-mapping.h>
45 #include <asm/arch/clk.h>
46 #include <linux/errno.h>
47
48 #include "macb.h"
49
50 DECLARE_GLOBAL_DATA_PTR;
51
52 /*
53 * These buffer sizes must be power of 2 and divisible
54 * by RX_BUFFER_MULTIPLE
55 */
56 #define MACB_RX_BUFFER_SIZE 128
57 #define GEM_RX_BUFFER_SIZE 2048
58 #define RX_BUFFER_MULTIPLE 64
59
60 #define MACB_RX_RING_SIZE 32
61 #define MACB_TX_RING_SIZE 16
62
63 #define MACB_TX_TIMEOUT 1000
64 #define MACB_AUTONEG_TIMEOUT 5000000
65
66 #ifdef CONFIG_MACB_ZYNQ
67 /* INCR4 AHB bursts */
68 #define MACB_ZYNQ_GEM_DMACR_BLENGTH 0x00000004
69 /* Use full configured addressable space (8 Kb) */
70 #define MACB_ZYNQ_GEM_DMACR_RXSIZE 0x00000300
71 /* Use full configured addressable space (4 Kb) */
72 #define MACB_ZYNQ_GEM_DMACR_TXSIZE 0x00000400
73 /* Set RXBUF with use of 128 byte */
74 #define MACB_ZYNQ_GEM_DMACR_RXBUF 0x00020000
75 #define MACB_ZYNQ_GEM_DMACR_INIT \
76 (MACB_ZYNQ_GEM_DMACR_BLENGTH | \
77 MACB_ZYNQ_GEM_DMACR_RXSIZE | \
78 MACB_ZYNQ_GEM_DMACR_TXSIZE | \
79 MACB_ZYNQ_GEM_DMACR_RXBUF)
80 #endif
81
82 struct macb_dma_desc {
83 u32 addr;
84 u32 ctrl;
85 };
86
87 struct macb_dma_desc_64 {
88 u32 addrh;
89 u32 unused;
90 };
91
92 #define HW_DMA_CAP_32B 0
93 #define HW_DMA_CAP_64B 1
94
95 #define DMA_DESC_SIZE 16
96 #define DMA_DESC_BYTES(n) ((n) * DMA_DESC_SIZE)
97 #define MACB_TX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_TX_RING_SIZE))
98 #define MACB_RX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_RX_RING_SIZE))
99 #define MACB_TX_DUMMY_DMA_DESC_SIZE (DMA_DESC_BYTES(1))
100
101 #define RXBUF_FRMLEN_MASK 0x00000fff
102 #define TXBUF_FRMLEN_MASK 0x000007ff
103
104 struct macb_device {
105 void *regs;
106
107 bool is_big_endian;
108
109 const struct macb_config *config;
110
111 unsigned int rx_tail;
112 unsigned int tx_head;
113 unsigned int tx_tail;
114 unsigned int next_rx_tail;
115 bool wrapped;
116
117 void *rx_buffer;
118 void *tx_buffer;
119 struct macb_dma_desc *rx_ring;
120 struct macb_dma_desc *tx_ring;
121 size_t rx_buffer_size;
122
123 unsigned long rx_buffer_dma;
124 unsigned long rx_ring_dma;
125 unsigned long tx_ring_dma;
126
127 struct macb_dma_desc *dummy_desc;
128 unsigned long dummy_desc_dma;
129
130 const struct device *dev;
131 #ifndef CONFIG_DM_ETH
132 struct eth_device netdev;
133 #endif
134 unsigned short phy_addr;
135 struct mii_dev *bus;
136 #ifdef CONFIG_PHYLIB
137 struct phy_device *phydev;
138 #endif
139
140 #ifdef CONFIG_DM_ETH
141 #ifdef CONFIG_CLK
142 unsigned long pclk_rate;
143 #endif
144 phy_interface_t phy_interface;
145 #endif
146 };
147
148 struct macb_usrio_cfg {
149 unsigned int mii;
150 unsigned int rmii;
151 unsigned int rgmii;
152 unsigned int clken;
153 };
154
155 struct macb_config {
156 unsigned int dma_burst_length;
157 unsigned int hw_dma_cap;
158 unsigned int caps;
159
160 int (*clk_init)(struct udevice *dev, ulong rate);
161 const struct macb_usrio_cfg *usrio;
162 };
163
164 #ifndef CONFIG_DM_ETH
165 #define to_macb(_nd) container_of(_nd, struct macb_device, netdev)
166 #endif
167
macb_is_gem(struct macb_device * macb)168 static int macb_is_gem(struct macb_device *macb)
169 {
170 return MACB_BFEXT(IDNUM, macb_readl(macb, MID)) >= 0x2;
171 }
172
173 #ifndef cpu_is_sama5d2
174 #define cpu_is_sama5d2() 0
175 #endif
176
177 #ifndef cpu_is_sama5d4
178 #define cpu_is_sama5d4() 0
179 #endif
180
gem_is_gigabit_capable(struct macb_device * macb)181 static int gem_is_gigabit_capable(struct macb_device *macb)
182 {
183 /*
184 * The GEM controllers embedded in SAMA5D2 and SAMA5D4 are
185 * configured to support only 10/100.
186 */
187 return macb_is_gem(macb) && !cpu_is_sama5d2() && !cpu_is_sama5d4();
188 }
189
macb_mdio_write(struct macb_device * macb,u8 phy_adr,u8 reg,u16 value)190 static void macb_mdio_write(struct macb_device *macb, u8 phy_adr, u8 reg,
191 u16 value)
192 {
193 unsigned long netctl;
194 unsigned long netstat;
195 unsigned long frame;
196
197 netctl = macb_readl(macb, NCR);
198 netctl |= MACB_BIT(MPE);
199 macb_writel(macb, NCR, netctl);
200
201 frame = (MACB_BF(SOF, 1)
202 | MACB_BF(RW, 1)
203 | MACB_BF(PHYA, phy_adr)
204 | MACB_BF(REGA, reg)
205 | MACB_BF(CODE, 2)
206 | MACB_BF(DATA, value));
207 macb_writel(macb, MAN, frame);
208
209 do {
210 netstat = macb_readl(macb, NSR);
211 } while (!(netstat & MACB_BIT(IDLE)));
212
213 netctl = macb_readl(macb, NCR);
214 netctl &= ~MACB_BIT(MPE);
215 macb_writel(macb, NCR, netctl);
216 }
217
macb_mdio_read(struct macb_device * macb,u8 phy_adr,u8 reg)218 static u16 macb_mdio_read(struct macb_device *macb, u8 phy_adr, u8 reg)
219 {
220 unsigned long netctl;
221 unsigned long netstat;
222 unsigned long frame;
223
224 netctl = macb_readl(macb, NCR);
225 netctl |= MACB_BIT(MPE);
226 macb_writel(macb, NCR, netctl);
227
228 frame = (MACB_BF(SOF, 1)
229 | MACB_BF(RW, 2)
230 | MACB_BF(PHYA, phy_adr)
231 | MACB_BF(REGA, reg)
232 | MACB_BF(CODE, 2));
233 macb_writel(macb, MAN, frame);
234
235 do {
236 netstat = macb_readl(macb, NSR);
237 } while (!(netstat & MACB_BIT(IDLE)));
238
239 frame = macb_readl(macb, MAN);
240
241 netctl = macb_readl(macb, NCR);
242 netctl &= ~MACB_BIT(MPE);
243 macb_writel(macb, NCR, netctl);
244
245 return MACB_BFEXT(DATA, frame);
246 }
247
arch_get_mdio_control(const char * name)248 void __weak arch_get_mdio_control(const char *name)
249 {
250 return;
251 }
252
253 #if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
254
macb_miiphy_read(struct mii_dev * bus,int phy_adr,int devad,int reg)255 int macb_miiphy_read(struct mii_dev *bus, int phy_adr, int devad, int reg)
256 {
257 u16 value = 0;
258 #ifdef CONFIG_DM_ETH
259 struct udevice *dev = eth_get_dev_by_name(bus->name);
260 struct macb_device *macb = dev_get_priv(dev);
261 #else
262 struct eth_device *dev = eth_get_dev_by_name(bus->name);
263 struct macb_device *macb = to_macb(dev);
264 #endif
265
266 arch_get_mdio_control(bus->name);
267 value = macb_mdio_read(macb, phy_adr, reg);
268
269 return value;
270 }
271
macb_miiphy_write(struct mii_dev * bus,int phy_adr,int devad,int reg,u16 value)272 int macb_miiphy_write(struct mii_dev *bus, int phy_adr, int devad, int reg,
273 u16 value)
274 {
275 #ifdef CONFIG_DM_ETH
276 struct udevice *dev = eth_get_dev_by_name(bus->name);
277 struct macb_device *macb = dev_get_priv(dev);
278 #else
279 struct eth_device *dev = eth_get_dev_by_name(bus->name);
280 struct macb_device *macb = to_macb(dev);
281 #endif
282
283 arch_get_mdio_control(bus->name);
284 macb_mdio_write(macb, phy_adr, reg, value);
285
286 return 0;
287 }
288 #endif
289
290 #define RX 1
291 #define TX 0
macb_invalidate_ring_desc(struct macb_device * macb,bool rx)292 static inline void macb_invalidate_ring_desc(struct macb_device *macb, bool rx)
293 {
294 if (rx)
295 invalidate_dcache_range(macb->rx_ring_dma,
296 ALIGN(macb->rx_ring_dma + MACB_RX_DMA_DESC_SIZE,
297 PKTALIGN));
298 else
299 invalidate_dcache_range(macb->tx_ring_dma,
300 ALIGN(macb->tx_ring_dma + MACB_TX_DMA_DESC_SIZE,
301 PKTALIGN));
302 }
303
macb_flush_ring_desc(struct macb_device * macb,bool rx)304 static inline void macb_flush_ring_desc(struct macb_device *macb, bool rx)
305 {
306 if (rx)
307 flush_dcache_range(macb->rx_ring_dma, macb->rx_ring_dma +
308 ALIGN(MACB_RX_DMA_DESC_SIZE, PKTALIGN));
309 else
310 flush_dcache_range(macb->tx_ring_dma, macb->tx_ring_dma +
311 ALIGN(MACB_TX_DMA_DESC_SIZE, PKTALIGN));
312 }
313
macb_flush_rx_buffer(struct macb_device * macb)314 static inline void macb_flush_rx_buffer(struct macb_device *macb)
315 {
316 flush_dcache_range(macb->rx_buffer_dma, macb->rx_buffer_dma +
317 ALIGN(macb->rx_buffer_size * MACB_RX_RING_SIZE,
318 PKTALIGN));
319 }
320
macb_invalidate_rx_buffer(struct macb_device * macb)321 static inline void macb_invalidate_rx_buffer(struct macb_device *macb)
322 {
323 invalidate_dcache_range(macb->rx_buffer_dma, macb->rx_buffer_dma +
324 ALIGN(macb->rx_buffer_size * MACB_RX_RING_SIZE,
325 PKTALIGN));
326 }
327
328 #if defined(CONFIG_CMD_NET)
329
macb_64b_desc(struct macb_dma_desc * desc)330 static struct macb_dma_desc_64 *macb_64b_desc(struct macb_dma_desc *desc)
331 {
332 return (struct macb_dma_desc_64 *)((void *)desc
333 + sizeof(struct macb_dma_desc));
334 }
335
macb_set_addr(struct macb_device * macb,struct macb_dma_desc * desc,ulong addr)336 static void macb_set_addr(struct macb_device *macb, struct macb_dma_desc *desc,
337 ulong addr)
338 {
339 struct macb_dma_desc_64 *desc_64;
340
341 if (macb->config->hw_dma_cap & HW_DMA_CAP_64B) {
342 desc_64 = macb_64b_desc(desc);
343 desc_64->addrh = upper_32_bits(addr);
344 }
345 desc->addr = lower_32_bits(addr);
346 }
347
_macb_send(struct macb_device * macb,const char * name,void * packet,int length)348 static int _macb_send(struct macb_device *macb, const char *name, void *packet,
349 int length)
350 {
351 unsigned long paddr, ctrl;
352 unsigned int tx_head = macb->tx_head;
353 int i;
354
355 paddr = dma_map_single(packet, length, DMA_TO_DEVICE);
356
357 ctrl = length & TXBUF_FRMLEN_MASK;
358 ctrl |= MACB_BIT(TX_LAST);
359 if (tx_head == (MACB_TX_RING_SIZE - 1)) {
360 ctrl |= MACB_BIT(TX_WRAP);
361 macb->tx_head = 0;
362 } else {
363 macb->tx_head++;
364 }
365
366 if (macb->config->hw_dma_cap & HW_DMA_CAP_64B)
367 tx_head = tx_head * 2;
368
369 macb->tx_ring[tx_head].ctrl = ctrl;
370 macb_set_addr(macb, &macb->tx_ring[tx_head], paddr);
371
372 barrier();
373 macb_flush_ring_desc(macb, TX);
374 macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(TSTART));
375
376 /*
377 * I guess this is necessary because the networking core may
378 * re-use the transmit buffer as soon as we return...
379 */
380 for (i = 0; i <= MACB_TX_TIMEOUT; i++) {
381 barrier();
382 macb_invalidate_ring_desc(macb, TX);
383 ctrl = macb->tx_ring[tx_head].ctrl;
384 if (ctrl & MACB_BIT(TX_USED))
385 break;
386 udelay(1);
387 }
388
389 dma_unmap_single(paddr, length, DMA_TO_DEVICE);
390
391 if (i <= MACB_TX_TIMEOUT) {
392 if (ctrl & MACB_BIT(TX_UNDERRUN))
393 printf("%s: TX underrun\n", name);
394 if (ctrl & MACB_BIT(TX_BUF_EXHAUSTED))
395 printf("%s: TX buffers exhausted in mid frame\n", name);
396 } else {
397 printf("%s: TX timeout\n", name);
398 }
399
400 /* No one cares anyway */
401 return 0;
402 }
403
reclaim_rx_buffers(struct macb_device * macb,unsigned int new_tail)404 static void reclaim_rx_buffers(struct macb_device *macb,
405 unsigned int new_tail)
406 {
407 unsigned int i;
408 unsigned int count;
409
410 i = macb->rx_tail;
411
412 macb_invalidate_ring_desc(macb, RX);
413 while (i > new_tail) {
414 if (macb->config->hw_dma_cap & HW_DMA_CAP_64B)
415 count = i * 2;
416 else
417 count = i;
418 macb->rx_ring[count].addr &= ~MACB_BIT(RX_USED);
419 i++;
420 if (i > MACB_RX_RING_SIZE)
421 i = 0;
422 }
423
424 while (i < new_tail) {
425 if (macb->config->hw_dma_cap & HW_DMA_CAP_64B)
426 count = i * 2;
427 else
428 count = i;
429 macb->rx_ring[count].addr &= ~MACB_BIT(RX_USED);
430 i++;
431 }
432
433 barrier();
434 macb_flush_ring_desc(macb, RX);
435 macb->rx_tail = new_tail;
436 }
437
_macb_recv(struct macb_device * macb,uchar ** packetp)438 static int _macb_recv(struct macb_device *macb, uchar **packetp)
439 {
440 unsigned int next_rx_tail = macb->next_rx_tail;
441 void *buffer;
442 int length;
443 u32 status;
444 u8 flag = false;
445
446 macb->wrapped = false;
447 for (;;) {
448 macb_invalidate_ring_desc(macb, RX);
449
450 if (macb->config->hw_dma_cap & HW_DMA_CAP_64B)
451 next_rx_tail = next_rx_tail * 2;
452
453 if (!(macb->rx_ring[next_rx_tail].addr & MACB_BIT(RX_USED)))
454 return -EAGAIN;
455
456 status = macb->rx_ring[next_rx_tail].ctrl;
457 if (status & MACB_BIT(RX_SOF)) {
458 if (macb->config->hw_dma_cap & HW_DMA_CAP_64B) {
459 next_rx_tail = next_rx_tail / 2;
460 flag = true;
461 }
462
463 if (next_rx_tail != macb->rx_tail)
464 reclaim_rx_buffers(macb, next_rx_tail);
465 macb->wrapped = false;
466 }
467
468 if (status & MACB_BIT(RX_EOF)) {
469 buffer = macb->rx_buffer +
470 macb->rx_buffer_size * macb->rx_tail;
471 length = status & RXBUF_FRMLEN_MASK;
472
473 macb_invalidate_rx_buffer(macb);
474 if (macb->wrapped) {
475 unsigned int headlen, taillen;
476
477 headlen = macb->rx_buffer_size *
478 (MACB_RX_RING_SIZE - macb->rx_tail);
479 taillen = length - headlen;
480 memcpy((void *)net_rx_packets[0],
481 buffer, headlen);
482 memcpy((void *)net_rx_packets[0] + headlen,
483 macb->rx_buffer, taillen);
484 *packetp = (void *)net_rx_packets[0];
485 } else {
486 *packetp = buffer;
487 }
488
489 if (macb->config->hw_dma_cap & HW_DMA_CAP_64B) {
490 if (!flag)
491 next_rx_tail = next_rx_tail / 2;
492 }
493
494 if (++next_rx_tail >= MACB_RX_RING_SIZE)
495 next_rx_tail = 0;
496 macb->next_rx_tail = next_rx_tail;
497 return length;
498 } else {
499 if (macb->config->hw_dma_cap & HW_DMA_CAP_64B) {
500 if (!flag)
501 next_rx_tail = next_rx_tail / 2;
502 flag = false;
503 }
504
505 if (++next_rx_tail >= MACB_RX_RING_SIZE) {
506 macb->wrapped = true;
507 next_rx_tail = 0;
508 }
509 }
510 barrier();
511 }
512 }
513
macb_phy_reset(struct macb_device * macb,const char * name)514 static void macb_phy_reset(struct macb_device *macb, const char *name)
515 {
516 int i;
517 u16 status, adv;
518
519 adv = ADVERTISE_CSMA | ADVERTISE_ALL;
520 macb_mdio_write(macb, macb->phy_addr, MII_ADVERTISE, adv);
521 printf("%s: Starting autonegotiation...\n", name);
522 macb_mdio_write(macb, macb->phy_addr, MII_BMCR, (BMCR_ANENABLE
523 | BMCR_ANRESTART));
524
525 for (i = 0; i < MACB_AUTONEG_TIMEOUT / 100; i++) {
526 status = macb_mdio_read(macb, macb->phy_addr, MII_BMSR);
527 if (status & BMSR_ANEGCOMPLETE)
528 break;
529 udelay(100);
530 }
531
532 if (status & BMSR_ANEGCOMPLETE)
533 printf("%s: Autonegotiation complete\n", name);
534 else
535 printf("%s: Autonegotiation timed out (status=0x%04x)\n",
536 name, status);
537 }
538
macb_phy_find(struct macb_device * macb,const char * name)539 static int macb_phy_find(struct macb_device *macb, const char *name)
540 {
541 int i;
542 u16 phy_id;
543
544 phy_id = macb_mdio_read(macb, macb->phy_addr, MII_PHYSID1);
545 if (phy_id != 0xffff) {
546 printf("%s: PHY present at %d\n", name, macb->phy_addr);
547 return 0;
548 }
549
550 /* Search for PHY... */
551 for (i = 0; i < 32; i++) {
552 macb->phy_addr = i;
553 phy_id = macb_mdio_read(macb, macb->phy_addr, MII_PHYSID1);
554 if (phy_id != 0xffff) {
555 printf("%s: PHY present at %d\n", name, i);
556 return 0;
557 }
558 }
559
560 /* PHY isn't up to snuff */
561 printf("%s: PHY not found\n", name);
562
563 return -ENODEV;
564 }
565
566 /**
567 * macb_linkspd_cb - Linkspeed change callback function
568 * @dev/@regs: MACB udevice (DM version) or
569 * Base Register of MACB devices (non-DM version)
570 * @speed: Linkspeed
571 * Returns 0 when operation success and negative errno number
572 * when operation failed.
573 */
574 #ifdef CONFIG_DM_ETH
macb_sifive_clk_init(struct udevice * dev,ulong rate)575 static int macb_sifive_clk_init(struct udevice *dev, ulong rate)
576 {
577 fdt_addr_t addr;
578 void *gemgxl_regs;
579
580 addr = dev_read_addr_index(dev, 1);
581 if (addr == FDT_ADDR_T_NONE)
582 return -ENODEV;
583
584 gemgxl_regs = (void __iomem *)addr;
585 if (!gemgxl_regs)
586 return -ENODEV;
587
588 /*
589 * SiFive GEMGXL TX clock operation mode:
590 *
591 * 0 = GMII mode. Use 125 MHz gemgxlclk from PRCI in TX logic
592 * and output clock on GMII output signal GTX_CLK
593 * 1 = MII mode. Use MII input signal TX_CLK in TX logic
594 */
595 writel(rate != 125000000, gemgxl_regs);
596 return 0;
597 }
598
macb_sama7g5_clk_init(struct udevice * dev,ulong rate)599 static int macb_sama7g5_clk_init(struct udevice *dev, ulong rate)
600 {
601 struct clk clk;
602 int ret;
603
604 ret = clk_get_by_name(dev, "tx_clk", &clk);
605 if (ret)
606 return ret;
607
608 /*
609 * This is for using GCK. Clock rate is addressed via assigned-clock
610 * property, so only clock enable is needed here. The switching to
611 * proper clock rate depending on link speed is managed by IP logic.
612 */
613 return clk_enable(&clk);
614 }
615
macb_linkspd_cb(struct udevice * dev,unsigned int speed)616 int __weak macb_linkspd_cb(struct udevice *dev, unsigned int speed)
617 {
618 #ifdef CONFIG_CLK
619 struct macb_device *macb = dev_get_priv(dev);
620 struct clk tx_clk;
621 ulong rate;
622 int ret;
623
624 switch (speed) {
625 case _10BASET:
626 rate = 2500000; /* 2.5 MHz */
627 break;
628 case _100BASET:
629 rate = 25000000; /* 25 MHz */
630 break;
631 case _1000BASET:
632 rate = 125000000; /* 125 MHz */
633 break;
634 default:
635 /* does not change anything */
636 return 0;
637 }
638
639 if (macb->config->clk_init)
640 return macb->config->clk_init(dev, rate);
641
642 /*
643 * "tx_clk" is an optional clock source for MACB.
644 * Ignore if it does not exist in DT.
645 */
646 ret = clk_get_by_name(dev, "tx_clk", &tx_clk);
647 if (ret)
648 return 0;
649
650 if (tx_clk.dev) {
651 ret = clk_set_rate(&tx_clk, rate);
652 if (ret < 0)
653 return ret;
654 }
655 #endif
656
657 return 0;
658 }
659 #else
macb_linkspd_cb(void * regs,unsigned int speed)660 int __weak macb_linkspd_cb(void *regs, unsigned int speed)
661 {
662 return 0;
663 }
664 #endif
665
666 #ifdef CONFIG_DM_ETH
macb_phy_init(struct udevice * dev,const char * name)667 static int macb_phy_init(struct udevice *dev, const char *name)
668 #else
669 static int macb_phy_init(struct macb_device *macb, const char *name)
670 #endif
671 {
672 #ifdef CONFIG_DM_ETH
673 struct macb_device *macb = dev_get_priv(dev);
674 #endif
675 u32 ncfgr;
676 u16 phy_id, status, adv, lpa;
677 int media, speed, duplex;
678 int ret;
679 int i;
680
681 arch_get_mdio_control(name);
682 /* Auto-detect phy_addr */
683 ret = macb_phy_find(macb, name);
684 if (ret)
685 return ret;
686
687 /* Check if the PHY is up to snuff... */
688 phy_id = macb_mdio_read(macb, macb->phy_addr, MII_PHYSID1);
689 if (phy_id == 0xffff) {
690 printf("%s: No PHY present\n", name);
691 return -ENODEV;
692 }
693
694 #ifdef CONFIG_PHYLIB
695 #ifdef CONFIG_DM_ETH
696 macb->phydev = phy_connect(macb->bus, macb->phy_addr, dev,
697 macb->phy_interface);
698 #else
699 /* need to consider other phy interface mode */
700 macb->phydev = phy_connect(macb->bus, macb->phy_addr, &macb->netdev,
701 PHY_INTERFACE_MODE_RGMII);
702 #endif
703 if (!macb->phydev) {
704 printf("phy_connect failed\n");
705 return -ENODEV;
706 }
707
708 phy_config(macb->phydev);
709 #endif
710
711 status = macb_mdio_read(macb, macb->phy_addr, MII_BMSR);
712 if (!(status & BMSR_LSTATUS)) {
713 /* Try to re-negotiate if we don't have link already. */
714 macb_phy_reset(macb, name);
715
716 for (i = 0; i < MACB_AUTONEG_TIMEOUT / 100; i++) {
717 status = macb_mdio_read(macb, macb->phy_addr, MII_BMSR);
718 if (status & BMSR_LSTATUS) {
719 /*
720 * Delay a bit after the link is established,
721 * so that the next xfer does not fail
722 */
723 mdelay(10);
724 break;
725 }
726 udelay(100);
727 }
728 }
729
730 if (!(status & BMSR_LSTATUS)) {
731 printf("%s: link down (status: 0x%04x)\n",
732 name, status);
733 return -ENETDOWN;
734 }
735
736 /* First check for GMAC and that it is GiB capable */
737 if (gem_is_gigabit_capable(macb)) {
738 lpa = macb_mdio_read(macb, macb->phy_addr, MII_STAT1000);
739
740 if (lpa & (LPA_1000FULL | LPA_1000HALF | LPA_1000XFULL |
741 LPA_1000XHALF)) {
742 duplex = ((lpa & (LPA_1000FULL | LPA_1000XFULL)) ?
743 1 : 0);
744
745 printf("%s: link up, 1000Mbps %s-duplex (lpa: 0x%04x)\n",
746 name,
747 duplex ? "full" : "half",
748 lpa);
749
750 ncfgr = macb_readl(macb, NCFGR);
751 ncfgr &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
752 ncfgr |= GEM_BIT(GBE);
753
754 if (duplex)
755 ncfgr |= MACB_BIT(FD);
756
757 macb_writel(macb, NCFGR, ncfgr);
758
759 #ifdef CONFIG_DM_ETH
760 ret = macb_linkspd_cb(dev, _1000BASET);
761 #else
762 ret = macb_linkspd_cb(macb->regs, _1000BASET);
763 #endif
764 if (ret)
765 return ret;
766
767 return 0;
768 }
769 }
770
771 /* fall back for EMAC checking */
772 adv = macb_mdio_read(macb, macb->phy_addr, MII_ADVERTISE);
773 lpa = macb_mdio_read(macb, macb->phy_addr, MII_LPA);
774 media = mii_nway_result(lpa & adv);
775 speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF)
776 ? 1 : 0);
777 duplex = (media & ADVERTISE_FULL) ? 1 : 0;
778 printf("%s: link up, %sMbps %s-duplex (lpa: 0x%04x)\n",
779 name,
780 speed ? "100" : "10",
781 duplex ? "full" : "half",
782 lpa);
783
784 ncfgr = macb_readl(macb, NCFGR);
785 ncfgr &= ~(MACB_BIT(SPD) | MACB_BIT(FD) | GEM_BIT(GBE));
786 if (speed) {
787 ncfgr |= MACB_BIT(SPD);
788 #ifdef CONFIG_DM_ETH
789 ret = macb_linkspd_cb(dev, _100BASET);
790 #else
791 ret = macb_linkspd_cb(macb->regs, _100BASET);
792 #endif
793 } else {
794 #ifdef CONFIG_DM_ETH
795 ret = macb_linkspd_cb(dev, _10BASET);
796 #else
797 ret = macb_linkspd_cb(macb->regs, _10BASET);
798 #endif
799 }
800
801 if (ret)
802 return ret;
803
804 if (duplex)
805 ncfgr |= MACB_BIT(FD);
806 macb_writel(macb, NCFGR, ncfgr);
807
808 return 0;
809 }
810
gmac_init_multi_queues(struct macb_device * macb)811 static int gmac_init_multi_queues(struct macb_device *macb)
812 {
813 int i, num_queues = 1;
814 u32 queue_mask;
815 unsigned long paddr;
816
817 /* bit 0 is never set but queue 0 always exists */
818 queue_mask = gem_readl(macb, DCFG6) & 0xff;
819 queue_mask |= 0x1;
820
821 for (i = 1; i < MACB_MAX_QUEUES; i++)
822 if (queue_mask & (1 << i))
823 num_queues++;
824
825 macb->dummy_desc->ctrl = MACB_BIT(TX_USED);
826 macb->dummy_desc->addr = 0;
827 flush_dcache_range(macb->dummy_desc_dma, macb->dummy_desc_dma +
828 ALIGN(MACB_TX_DUMMY_DMA_DESC_SIZE, PKTALIGN));
829 paddr = macb->dummy_desc_dma;
830
831 for (i = 1; i < num_queues; i++) {
832 gem_writel_queue_TBQP(macb, lower_32_bits(paddr), i - 1);
833 gem_writel_queue_RBQP(macb, lower_32_bits(paddr), i - 1);
834 if (macb->config->hw_dma_cap & HW_DMA_CAP_64B) {
835 gem_writel_queue_TBQPH(macb, upper_32_bits(paddr),
836 i - 1);
837 gem_writel_queue_RBQPH(macb, upper_32_bits(paddr),
838 i - 1);
839 }
840 }
841 return 0;
842 }
843
gmac_configure_dma(struct macb_device * macb)844 static void gmac_configure_dma(struct macb_device *macb)
845 {
846 u32 buffer_size;
847 u32 dmacfg;
848
849 buffer_size = macb->rx_buffer_size / RX_BUFFER_MULTIPLE;
850 dmacfg = gem_readl(macb, DMACFG) & ~GEM_BF(RXBS, -1L);
851 dmacfg |= GEM_BF(RXBS, buffer_size);
852
853 if (macb->config->dma_burst_length)
854 dmacfg = GEM_BFINS(FBLDO,
855 macb->config->dma_burst_length, dmacfg);
856
857 dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L);
858 dmacfg &= ~GEM_BIT(ENDIA_PKT);
859
860 if (macb->is_big_endian)
861 dmacfg |= GEM_BIT(ENDIA_DESC); /* CPU in big endian */
862 else
863 dmacfg &= ~GEM_BIT(ENDIA_DESC);
864
865 dmacfg &= ~GEM_BIT(ADDR64);
866 if (macb->config->hw_dma_cap & HW_DMA_CAP_64B)
867 dmacfg |= GEM_BIT(ADDR64);
868
869 gem_writel(macb, DMACFG, dmacfg);
870 }
871
872 #ifdef CONFIG_DM_ETH
_macb_init(struct udevice * dev,const char * name)873 static int _macb_init(struct udevice *dev, const char *name)
874 #else
875 static int _macb_init(struct macb_device *macb, const char *name)
876 #endif
877 {
878 #ifdef CONFIG_DM_ETH
879 struct macb_device *macb = dev_get_priv(dev);
880 unsigned int val = 0;
881 #endif
882 unsigned long paddr;
883 int ret;
884 int i;
885 int count;
886
887 /*
888 * macb_halt should have been called at some point before now,
889 * so we'll assume the controller is idle.
890 */
891
892 /* initialize DMA descriptors */
893 paddr = macb->rx_buffer_dma;
894 for (i = 0; i < MACB_RX_RING_SIZE; i++) {
895 if (i == (MACB_RX_RING_SIZE - 1))
896 paddr |= MACB_BIT(RX_WRAP);
897 if (macb->config->hw_dma_cap & HW_DMA_CAP_64B)
898 count = i * 2;
899 else
900 count = i;
901 macb->rx_ring[count].ctrl = 0;
902 macb_set_addr(macb, &macb->rx_ring[count], paddr);
903 paddr += macb->rx_buffer_size;
904 }
905 macb_flush_ring_desc(macb, RX);
906 macb_flush_rx_buffer(macb);
907
908 for (i = 0; i < MACB_TX_RING_SIZE; i++) {
909 if (macb->config->hw_dma_cap & HW_DMA_CAP_64B)
910 count = i * 2;
911 else
912 count = i;
913 macb_set_addr(macb, &macb->tx_ring[count], 0);
914 if (i == (MACB_TX_RING_SIZE - 1))
915 macb->tx_ring[count].ctrl = MACB_BIT(TX_USED) |
916 MACB_BIT(TX_WRAP);
917 else
918 macb->tx_ring[count].ctrl = MACB_BIT(TX_USED);
919 }
920 macb_flush_ring_desc(macb, TX);
921
922 macb->rx_tail = 0;
923 macb->tx_head = 0;
924 macb->tx_tail = 0;
925 macb->next_rx_tail = 0;
926
927 #ifdef CONFIG_MACB_ZYNQ
928 gem_writel(macb, DMACFG, MACB_ZYNQ_GEM_DMACR_INIT);
929 #endif
930
931 macb_writel(macb, RBQP, lower_32_bits(macb->rx_ring_dma));
932 macb_writel(macb, TBQP, lower_32_bits(macb->tx_ring_dma));
933 if (macb->config->hw_dma_cap & HW_DMA_CAP_64B) {
934 macb_writel(macb, RBQPH, upper_32_bits(macb->rx_ring_dma));
935 macb_writel(macb, TBQPH, upper_32_bits(macb->tx_ring_dma));
936 }
937
938 if (macb_is_gem(macb)) {
939 /* Initialize DMA properties */
940 gmac_configure_dma(macb);
941 /* Check the multi queue and initialize the queue for tx */
942 gmac_init_multi_queues(macb);
943
944 /*
945 * When the GMAC IP with GE feature, this bit is used to
946 * select interface between RGMII and GMII.
947 * When the GMAC IP without GE feature, this bit is used
948 * to select interface between RMII and MII.
949 */
950 #ifdef CONFIG_DM_ETH
951 if (macb->phy_interface == PHY_INTERFACE_MODE_RGMII ||
952 macb->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
953 macb->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID ||
954 macb->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID)
955 val = macb->config->usrio->rgmii;
956 else if (macb->phy_interface == PHY_INTERFACE_MODE_RMII)
957 val = macb->config->usrio->rmii;
958 else if (macb->phy_interface == PHY_INTERFACE_MODE_MII)
959 val = macb->config->usrio->mii;
960
961 if (macb->config->caps & MACB_CAPS_USRIO_HAS_CLKEN)
962 val |= macb->config->usrio->clken;
963
964 gem_writel(macb, USRIO, val);
965
966 if (macb->phy_interface == PHY_INTERFACE_MODE_SGMII) {
967 unsigned int ncfgr = macb_readl(macb, NCFGR);
968
969 ncfgr |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL);
970 macb_writel(macb, NCFGR, ncfgr);
971 }
972 #else
973 #if defined(CONFIG_RGMII) || defined(CONFIG_RMII)
974 gem_writel(macb, USRIO, macb->config->usrio->rgmii);
975 #else
976 gem_writel(macb, USRIO, 0);
977 #endif
978 #endif
979 } else {
980 /* choose RMII or MII mode. This depends on the board */
981 #ifdef CONFIG_DM_ETH
982 #ifdef CONFIG_AT91FAMILY
983 if (macb->phy_interface == PHY_INTERFACE_MODE_RMII) {
984 macb_writel(macb, USRIO,
985 macb->config->usrio->rmii |
986 macb->config->usrio->clken);
987 } else {
988 macb_writel(macb, USRIO, macb->config->usrio->clken);
989 }
990 #else
991 if (macb->phy_interface == PHY_INTERFACE_MODE_RMII)
992 macb_writel(macb, USRIO, 0);
993 else
994 macb_writel(macb, USRIO, macb->config->usrio->mii);
995 #endif
996 #else
997 #ifdef CONFIG_RMII
998 #ifdef CONFIG_AT91FAMILY
999 macb_writel(macb, USRIO, macb->config->usrio->rmii |
1000 macb->config->usrio->clken);
1001 #else
1002 macb_writel(macb, USRIO, 0);
1003 #endif
1004 #else
1005 #ifdef CONFIG_AT91FAMILY
1006 macb_writel(macb, USRIO, macb->config->usrio->clken);
1007 #else
1008 macb_writel(macb, USRIO, macb->config->usrio->mii);
1009 #endif
1010 #endif /* CONFIG_RMII */
1011 #endif
1012 }
1013
1014 #ifdef CONFIG_DM_ETH
1015 ret = macb_phy_init(dev, name);
1016 #else
1017 ret = macb_phy_init(macb, name);
1018 #endif
1019 if (ret)
1020 return ret;
1021
1022 /* Enable TX and RX */
1023 macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE));
1024
1025 return 0;
1026 }
1027
_macb_halt(struct macb_device * macb)1028 static void _macb_halt(struct macb_device *macb)
1029 {
1030 u32 ncr, tsr;
1031
1032 /* Halt the controller and wait for any ongoing transmission to end. */
1033 ncr = macb_readl(macb, NCR);
1034 ncr |= MACB_BIT(THALT);
1035 macb_writel(macb, NCR, ncr);
1036
1037 do {
1038 tsr = macb_readl(macb, TSR);
1039 } while (tsr & MACB_BIT(TGO));
1040
1041 /* Disable TX and RX, and clear statistics */
1042 macb_writel(macb, NCR, MACB_BIT(CLRSTAT));
1043 }
1044
_macb_write_hwaddr(struct macb_device * macb,unsigned char * enetaddr)1045 static int _macb_write_hwaddr(struct macb_device *macb, unsigned char *enetaddr)
1046 {
1047 u32 hwaddr_bottom;
1048 u16 hwaddr_top;
1049
1050 /* set hardware address */
1051 hwaddr_bottom = enetaddr[0] | enetaddr[1] << 8 |
1052 enetaddr[2] << 16 | enetaddr[3] << 24;
1053 macb_writel(macb, SA1B, hwaddr_bottom);
1054 hwaddr_top = enetaddr[4] | enetaddr[5] << 8;
1055 macb_writel(macb, SA1T, hwaddr_top);
1056 return 0;
1057 }
1058
macb_mdc_clk_div(int id,struct macb_device * macb)1059 static u32 macb_mdc_clk_div(int id, struct macb_device *macb)
1060 {
1061 u32 config;
1062 #if defined(CONFIG_DM_ETH) && defined(CONFIG_CLK)
1063 unsigned long macb_hz = macb->pclk_rate;
1064 #else
1065 unsigned long macb_hz = get_macb_pclk_rate(id);
1066 #endif
1067
1068 if (macb_hz < 20000000)
1069 config = MACB_BF(CLK, MACB_CLK_DIV8);
1070 else if (macb_hz < 40000000)
1071 config = MACB_BF(CLK, MACB_CLK_DIV16);
1072 else if (macb_hz < 80000000)
1073 config = MACB_BF(CLK, MACB_CLK_DIV32);
1074 else
1075 config = MACB_BF(CLK, MACB_CLK_DIV64);
1076
1077 return config;
1078 }
1079
gem_mdc_clk_div(int id,struct macb_device * macb)1080 static u32 gem_mdc_clk_div(int id, struct macb_device *macb)
1081 {
1082 u32 config;
1083
1084 #if defined(CONFIG_DM_ETH) && defined(CONFIG_CLK)
1085 unsigned long macb_hz = macb->pclk_rate;
1086 #else
1087 unsigned long macb_hz = get_macb_pclk_rate(id);
1088 #endif
1089
1090 if (macb_hz < 20000000)
1091 config = GEM_BF(CLK, GEM_CLK_DIV8);
1092 else if (macb_hz < 40000000)
1093 config = GEM_BF(CLK, GEM_CLK_DIV16);
1094 else if (macb_hz < 80000000)
1095 config = GEM_BF(CLK, GEM_CLK_DIV32);
1096 else if (macb_hz < 120000000)
1097 config = GEM_BF(CLK, GEM_CLK_DIV48);
1098 else if (macb_hz < 160000000)
1099 config = GEM_BF(CLK, GEM_CLK_DIV64);
1100 else if (macb_hz < 240000000)
1101 config = GEM_BF(CLK, GEM_CLK_DIV96);
1102 else if (macb_hz < 320000000)
1103 config = GEM_BF(CLK, GEM_CLK_DIV128);
1104 else
1105 config = GEM_BF(CLK, GEM_CLK_DIV224);
1106
1107 return config;
1108 }
1109
1110 /*
1111 * Get the DMA bus width field of the network configuration register that we
1112 * should program. We find the width from decoding the design configuration
1113 * register to find the maximum supported data bus width.
1114 */
macb_dbw(struct macb_device * macb)1115 static u32 macb_dbw(struct macb_device *macb)
1116 {
1117 switch (GEM_BFEXT(DBWDEF, gem_readl(macb, DCFG1))) {
1118 case 4:
1119 return GEM_BF(DBW, GEM_DBW128);
1120 case 2:
1121 return GEM_BF(DBW, GEM_DBW64);
1122 case 1:
1123 default:
1124 return GEM_BF(DBW, GEM_DBW32);
1125 }
1126 }
1127
_macb_eth_initialize(struct macb_device * macb)1128 static void _macb_eth_initialize(struct macb_device *macb)
1129 {
1130 int id = 0; /* This is not used by functions we call */
1131 u32 ncfgr;
1132
1133 if (macb_is_gem(macb))
1134 macb->rx_buffer_size = GEM_RX_BUFFER_SIZE;
1135 else
1136 macb->rx_buffer_size = MACB_RX_BUFFER_SIZE;
1137
1138 /* TODO: we need check the rx/tx_ring_dma is dcache line aligned */
1139 macb->rx_buffer = dma_alloc_coherent(macb->rx_buffer_size *
1140 MACB_RX_RING_SIZE,
1141 &macb->rx_buffer_dma);
1142 macb->rx_ring = dma_alloc_coherent(MACB_RX_DMA_DESC_SIZE,
1143 &macb->rx_ring_dma);
1144 macb->tx_ring = dma_alloc_coherent(MACB_TX_DMA_DESC_SIZE,
1145 &macb->tx_ring_dma);
1146 macb->dummy_desc = dma_alloc_coherent(MACB_TX_DUMMY_DMA_DESC_SIZE,
1147 &macb->dummy_desc_dma);
1148
1149 /*
1150 * Do some basic initialization so that we at least can talk
1151 * to the PHY
1152 */
1153 if (macb_is_gem(macb)) {
1154 ncfgr = gem_mdc_clk_div(id, macb);
1155 ncfgr |= macb_dbw(macb);
1156 } else {
1157 ncfgr = macb_mdc_clk_div(id, macb);
1158 }
1159
1160 macb_writel(macb, NCFGR, ncfgr);
1161 }
1162
1163 #ifndef CONFIG_DM_ETH
macb_send(struct eth_device * netdev,void * packet,int length)1164 static int macb_send(struct eth_device *netdev, void *packet, int length)
1165 {
1166 struct macb_device *macb = to_macb(netdev);
1167
1168 return _macb_send(macb, netdev->name, packet, length);
1169 }
1170
macb_recv(struct eth_device * netdev)1171 static int macb_recv(struct eth_device *netdev)
1172 {
1173 struct macb_device *macb = to_macb(netdev);
1174 uchar *packet;
1175 int length;
1176
1177 macb->wrapped = false;
1178 for (;;) {
1179 macb->next_rx_tail = macb->rx_tail;
1180 length = _macb_recv(macb, &packet);
1181 if (length >= 0) {
1182 net_process_received_packet(packet, length);
1183 reclaim_rx_buffers(macb, macb->next_rx_tail);
1184 } else {
1185 return length;
1186 }
1187 }
1188 }
1189
macb_init(struct eth_device * netdev,struct bd_info * bd)1190 static int macb_init(struct eth_device *netdev, struct bd_info *bd)
1191 {
1192 struct macb_device *macb = to_macb(netdev);
1193
1194 return _macb_init(macb, netdev->name);
1195 }
1196
macb_halt(struct eth_device * netdev)1197 static void macb_halt(struct eth_device *netdev)
1198 {
1199 struct macb_device *macb = to_macb(netdev);
1200
1201 return _macb_halt(macb);
1202 }
1203
macb_write_hwaddr(struct eth_device * netdev)1204 static int macb_write_hwaddr(struct eth_device *netdev)
1205 {
1206 struct macb_device *macb = to_macb(netdev);
1207
1208 return _macb_write_hwaddr(macb, netdev->enetaddr);
1209 }
1210
macb_eth_initialize(int id,void * regs,unsigned int phy_addr)1211 int macb_eth_initialize(int id, void *regs, unsigned int phy_addr)
1212 {
1213 struct macb_device *macb;
1214 struct eth_device *netdev;
1215
1216 macb = malloc(sizeof(struct macb_device));
1217 if (!macb) {
1218 printf("Error: Failed to allocate memory for MACB%d\n", id);
1219 return -1;
1220 }
1221 memset(macb, 0, sizeof(struct macb_device));
1222
1223 netdev = &macb->netdev;
1224
1225 macb->regs = regs;
1226 macb->phy_addr = phy_addr;
1227
1228 if (macb_is_gem(macb))
1229 sprintf(netdev->name, "gmac%d", id);
1230 else
1231 sprintf(netdev->name, "macb%d", id);
1232
1233 netdev->init = macb_init;
1234 netdev->halt = macb_halt;
1235 netdev->send = macb_send;
1236 netdev->recv = macb_recv;
1237 netdev->write_hwaddr = macb_write_hwaddr;
1238
1239 _macb_eth_initialize(macb);
1240
1241 eth_register(netdev);
1242
1243 #if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
1244 int retval;
1245 struct mii_dev *mdiodev = mdio_alloc();
1246 if (!mdiodev)
1247 return -ENOMEM;
1248 strncpy(mdiodev->name, netdev->name, MDIO_NAME_LEN);
1249 mdiodev->read = macb_miiphy_read;
1250 mdiodev->write = macb_miiphy_write;
1251
1252 retval = mdio_register(mdiodev);
1253 if (retval < 0)
1254 return retval;
1255 macb->bus = miiphy_get_dev_by_name(netdev->name);
1256 #endif
1257 return 0;
1258 }
1259 #endif /* !CONFIG_DM_ETH */
1260
1261 #ifdef CONFIG_DM_ETH
1262
macb_start(struct udevice * dev)1263 static int macb_start(struct udevice *dev)
1264 {
1265 return _macb_init(dev, dev->name);
1266 }
1267
macb_send(struct udevice * dev,void * packet,int length)1268 static int macb_send(struct udevice *dev, void *packet, int length)
1269 {
1270 struct macb_device *macb = dev_get_priv(dev);
1271
1272 return _macb_send(macb, dev->name, packet, length);
1273 }
1274
macb_recv(struct udevice * dev,int flags,uchar ** packetp)1275 static int macb_recv(struct udevice *dev, int flags, uchar **packetp)
1276 {
1277 struct macb_device *macb = dev_get_priv(dev);
1278
1279 macb->next_rx_tail = macb->rx_tail;
1280 macb->wrapped = false;
1281
1282 return _macb_recv(macb, packetp);
1283 }
1284
macb_free_pkt(struct udevice * dev,uchar * packet,int length)1285 static int macb_free_pkt(struct udevice *dev, uchar *packet, int length)
1286 {
1287 struct macb_device *macb = dev_get_priv(dev);
1288
1289 reclaim_rx_buffers(macb, macb->next_rx_tail);
1290
1291 return 0;
1292 }
1293
macb_stop(struct udevice * dev)1294 static void macb_stop(struct udevice *dev)
1295 {
1296 struct macb_device *macb = dev_get_priv(dev);
1297
1298 _macb_halt(macb);
1299 }
1300
macb_write_hwaddr(struct udevice * dev)1301 static int macb_write_hwaddr(struct udevice *dev)
1302 {
1303 struct eth_pdata *plat = dev_get_plat(dev);
1304 struct macb_device *macb = dev_get_priv(dev);
1305
1306 return _macb_write_hwaddr(macb, plat->enetaddr);
1307 }
1308
1309 static const struct eth_ops macb_eth_ops = {
1310 .start = macb_start,
1311 .send = macb_send,
1312 .recv = macb_recv,
1313 .stop = macb_stop,
1314 .free_pkt = macb_free_pkt,
1315 .write_hwaddr = macb_write_hwaddr,
1316 };
1317
1318 #ifdef CONFIG_CLK
macb_enable_clk(struct udevice * dev)1319 static int macb_enable_clk(struct udevice *dev)
1320 {
1321 struct macb_device *macb = dev_get_priv(dev);
1322 struct clk clk;
1323 ulong clk_rate;
1324 int ret;
1325
1326 ret = clk_get_by_index(dev, 0, &clk);
1327 if (ret)
1328 return -EINVAL;
1329
1330 /*
1331 * If clock driver didn't support enable or disable then
1332 * we get -ENOSYS from clk_enable(). To handle this, we
1333 * don't fail for ret == -ENOSYS.
1334 */
1335 ret = clk_enable(&clk);
1336 if (ret && ret != -ENOSYS)
1337 return ret;
1338
1339 clk_rate = clk_get_rate(&clk);
1340 if (!clk_rate)
1341 return -EINVAL;
1342
1343 macb->pclk_rate = clk_rate;
1344
1345 return 0;
1346 }
1347 #endif
1348
1349 static const struct macb_usrio_cfg macb_default_usrio = {
1350 .mii = MACB_BIT(MII),
1351 .rmii = MACB_BIT(RMII),
1352 .rgmii = GEM_BIT(RGMII),
1353 .clken = MACB_BIT(CLKEN),
1354 };
1355
1356 static const struct macb_config default_gem_config = {
1357 .dma_burst_length = 16,
1358 .hw_dma_cap = HW_DMA_CAP_32B,
1359 .clk_init = NULL,
1360 .usrio = &macb_default_usrio,
1361 };
1362
macb_eth_probe(struct udevice * dev)1363 static int macb_eth_probe(struct udevice *dev)
1364 {
1365 struct eth_pdata *pdata = dev_get_plat(dev);
1366 struct macb_device *macb = dev_get_priv(dev);
1367 struct ofnode_phandle_args phandle_args;
1368 const char *phy_mode;
1369 int ret;
1370
1371 phy_mode = dev_read_prop(dev, "phy-mode", NULL);
1372
1373 if (phy_mode)
1374 macb->phy_interface = phy_get_interface_by_name(phy_mode);
1375 if (macb->phy_interface == -1) {
1376 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
1377 return -EINVAL;
1378 }
1379
1380 /* Read phyaddr from DT */
1381 if (!dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
1382 &phandle_args))
1383 macb->phy_addr = ofnode_read_u32_default(phandle_args.node,
1384 "reg", -1);
1385
1386 macb->regs = (void *)pdata->iobase;
1387
1388 macb->is_big_endian = (cpu_to_be32(0x12345678) == 0x12345678);
1389
1390 macb->config = (struct macb_config *)dev_get_driver_data(dev);
1391 if (!macb->config)
1392 macb->config = &default_gem_config;
1393
1394 #ifdef CONFIG_CLK
1395 ret = macb_enable_clk(dev);
1396 if (ret)
1397 return ret;
1398 #endif
1399
1400 _macb_eth_initialize(macb);
1401
1402 #if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
1403 macb->bus = mdio_alloc();
1404 if (!macb->bus)
1405 return -ENOMEM;
1406 strncpy(macb->bus->name, dev->name, MDIO_NAME_LEN);
1407 macb->bus->read = macb_miiphy_read;
1408 macb->bus->write = macb_miiphy_write;
1409
1410 ret = mdio_register(macb->bus);
1411 if (ret < 0)
1412 return ret;
1413 macb->bus = miiphy_get_dev_by_name(dev->name);
1414 #endif
1415
1416 return 0;
1417 }
1418
macb_eth_remove(struct udevice * dev)1419 static int macb_eth_remove(struct udevice *dev)
1420 {
1421 struct macb_device *macb = dev_get_priv(dev);
1422
1423 #ifdef CONFIG_PHYLIB
1424 free(macb->phydev);
1425 #endif
1426 mdio_unregister(macb->bus);
1427 mdio_free(macb->bus);
1428
1429 return 0;
1430 }
1431
1432 /**
1433 * macb_late_eth_of_to_plat
1434 * @dev: udevice struct
1435 * Returns 0 when operation success and negative errno number
1436 * when operation failed.
1437 */
macb_late_eth_of_to_plat(struct udevice * dev)1438 int __weak macb_late_eth_of_to_plat(struct udevice *dev)
1439 {
1440 return 0;
1441 }
1442
macb_eth_of_to_plat(struct udevice * dev)1443 static int macb_eth_of_to_plat(struct udevice *dev)
1444 {
1445 struct eth_pdata *pdata = dev_get_plat(dev);
1446
1447 pdata->iobase = (phys_addr_t)dev_remap_addr(dev);
1448 if (!pdata->iobase)
1449 return -EINVAL;
1450
1451 return macb_late_eth_of_to_plat(dev);
1452 }
1453
1454 static const struct macb_usrio_cfg sama7g5_usrio = {
1455 .mii = 0,
1456 .rmii = 1,
1457 .rgmii = 2,
1458 .clken = BIT(2),
1459 };
1460
1461 static const struct macb_config microchip_config = {
1462 .dma_burst_length = 16,
1463 .hw_dma_cap = HW_DMA_CAP_64B,
1464 .clk_init = NULL,
1465 .usrio = &macb_default_usrio,
1466 };
1467
1468 static const struct macb_config sama5d4_config = {
1469 .dma_burst_length = 4,
1470 .hw_dma_cap = HW_DMA_CAP_32B,
1471 .clk_init = NULL,
1472 .usrio = &macb_default_usrio,
1473 };
1474
1475 static const struct macb_config sifive_config = {
1476 .dma_burst_length = 16,
1477 .hw_dma_cap = HW_DMA_CAP_32B,
1478 .clk_init = macb_sifive_clk_init,
1479 .usrio = &macb_default_usrio,
1480 };
1481
1482 static const struct macb_config sama7g5_gmac_config = {
1483 .dma_burst_length = 16,
1484 .hw_dma_cap = HW_DMA_CAP_32B,
1485 .clk_init = macb_sama7g5_clk_init,
1486 .usrio = &sama7g5_usrio,
1487 };
1488
1489 static const struct macb_config sama7g5_emac_config = {
1490 .caps = MACB_CAPS_USRIO_HAS_CLKEN,
1491 .dma_burst_length = 16,
1492 .hw_dma_cap = HW_DMA_CAP_32B,
1493 .usrio = &sama7g5_usrio,
1494 };
1495
1496 static const struct udevice_id macb_eth_ids[] = {
1497 { .compatible = "cdns,macb" },
1498 { .compatible = "cdns,at91sam9260-macb" },
1499 { .compatible = "cdns,sam9x60-macb" },
1500 { .compatible = "cdns,sama7g5-gem",
1501 .data = (ulong)&sama7g5_gmac_config },
1502 { .compatible = "cdns,sama7g5-emac",
1503 .data = (ulong)&sama7g5_emac_config },
1504 { .compatible = "atmel,sama5d2-gem" },
1505 { .compatible = "atmel,sama5d3-gem" },
1506 { .compatible = "atmel,sama5d4-gem", .data = (ulong)&sama5d4_config },
1507 { .compatible = "cdns,zynq-gem" },
1508 { .compatible = "sifive,fu540-c000-gem",
1509 .data = (ulong)&sifive_config },
1510 { .compatible = "microchip,mpfs-mss-gem",
1511 .data = (ulong)µchip_config },
1512 { }
1513 };
1514
1515 U_BOOT_DRIVER(eth_macb) = {
1516 .name = "eth_macb",
1517 .id = UCLASS_ETH,
1518 .of_match = macb_eth_ids,
1519 .of_to_plat = macb_eth_of_to_plat,
1520 .probe = macb_eth_probe,
1521 .remove = macb_eth_remove,
1522 .ops = &macb_eth_ops,
1523 .priv_auto = sizeof(struct macb_device),
1524 .plat_auto = sizeof(struct eth_pdata),
1525 };
1526 #endif
1527
1528 #endif
1529