1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Designware master SPI core controller driver
4 *
5 * Copyright (C) 2014 Stefan Roese <sr@denx.de>
6 * Copyright (C) 2020 Sean Anderson <seanga2@gmail.com>
7 *
8 * Very loosely based on the Linux driver:
9 * drivers/spi/spi-dw.c, which is:
10 * Copyright (c) 2009, Intel Corporation.
11 */
12
13 #define LOG_CATEGORY UCLASS_SPI
14 #include <common.h>
15 #include <clk.h>
16 #include <dm.h>
17 #include <dm/device_compat.h>
18 #include <errno.h>
19 #include <fdtdec.h>
20 #include <log.h>
21 #include <malloc.h>
22 #include <reset.h>
23 #include <spi.h>
24 #include <spi-mem.h>
25 #include <asm/io.h>
26 #include <asm-generic/gpio.h>
27 #include <linux/bitfield.h>
28 #include <linux/bitops.h>
29 #include <linux/compat.h>
30 #include <linux/iopoll.h>
31 #include <linux/sizes.h>
32
33 /* Register offsets */
34 #define DW_SPI_CTRLR0 0x00
35 #define DW_SPI_CTRLR1 0x04
36 #define DW_SPI_SSIENR 0x08
37 #define DW_SPI_MWCR 0x0c
38 #define DW_SPI_SER 0x10
39 #define DW_SPI_BAUDR 0x14
40 #define DW_SPI_TXFTLR 0x18
41 #define DW_SPI_RXFTLR 0x1c
42 #define DW_SPI_TXFLR 0x20
43 #define DW_SPI_RXFLR 0x24
44 #define DW_SPI_SR 0x28
45 #define DW_SPI_IMR 0x2c
46 #define DW_SPI_ISR 0x30
47 #define DW_SPI_RISR 0x34
48 #define DW_SPI_TXOICR 0x38
49 #define DW_SPI_RXOICR 0x3c
50 #define DW_SPI_RXUICR 0x40
51 #define DW_SPI_MSTICR 0x44
52 #define DW_SPI_ICR 0x48
53 #define DW_SPI_DMACR 0x4c
54 #define DW_SPI_DMATDLR 0x50
55 #define DW_SPI_DMARDLR 0x54
56 #define DW_SPI_IDR 0x58
57 #define DW_SPI_VERSION 0x5c
58 #define DW_SPI_DR 0x60
59
60 /* Bit fields in CTRLR0 */
61 /*
62 * Only present when SSI_MAX_XFER_SIZE=16. This is the default, and the only
63 * option before version 3.23a.
64 */
65 #define CTRLR0_DFS_MASK GENMASK(3, 0)
66
67 #define CTRLR0_FRF_MASK GENMASK(5, 4)
68 #define CTRLR0_FRF_SPI 0x0
69 #define CTRLR0_FRF_SSP 0x1
70 #define CTRLR0_FRF_MICROWIRE 0x2
71 #define CTRLR0_FRF_RESV 0x3
72
73 #define CTRLR0_MODE_MASK GENMASK(7, 6)
74 #define CTRLR0_MODE_SCPH 0x1
75 #define CTRLR0_MODE_SCPOL 0x2
76
77 #define CTRLR0_TMOD_MASK GENMASK(9, 8)
78 #define CTRLR0_TMOD_TR 0x0 /* xmit & recv */
79 #define CTRLR0_TMOD_TO 0x1 /* xmit only */
80 #define CTRLR0_TMOD_RO 0x2 /* recv only */
81 #define CTRLR0_TMOD_EPROMREAD 0x3 /* eeprom read mode */
82
83 #define CTRLR0_SLVOE_OFFSET 10
84 #define CTRLR0_SRL_OFFSET 11
85 #define CTRLR0_CFS_MASK GENMASK(15, 12)
86
87 /* Only present when SSI_MAX_XFER_SIZE=32 */
88 #define CTRLR0_DFS_32_MASK GENMASK(20, 16)
89
90 /* The next field is only present on versions after 4.00a */
91 #define CTRLR0_SPI_FRF_MASK GENMASK(22, 21)
92 #define CTRLR0_SPI_FRF_BYTE 0x0
93 #define CTRLR0_SPI_FRF_DUAL 0x1
94 #define CTRLR0_SPI_FRF_QUAD 0x2
95
96 /* Bit fields in CTRLR0 based on DWC_ssi_databook.pdf v1.01a */
97 #define DWC_SSI_CTRLR0_DFS_MASK GENMASK(4, 0)
98 #define DWC_SSI_CTRLR0_FRF_MASK GENMASK(7, 6)
99 #define DWC_SSI_CTRLR0_MODE_MASK GENMASK(9, 8)
100 #define DWC_SSI_CTRLR0_TMOD_MASK GENMASK(11, 10)
101 #define DWC_SSI_CTRLR0_SRL_OFFSET 13
102 #define DWC_SSI_CTRLR0_SPI_FRF_MASK GENMASK(23, 22)
103
104 /* Bit fields in SR, 7 bits */
105 #define SR_MASK GENMASK(6, 0) /* cover 7 bits */
106 #define SR_BUSY BIT(0)
107 #define SR_TF_NOT_FULL BIT(1)
108 #define SR_TF_EMPT BIT(2)
109 #define SR_RF_NOT_EMPT BIT(3)
110 #define SR_RF_FULL BIT(4)
111 #define SR_TX_ERR BIT(5)
112 #define SR_DCOL BIT(6)
113
114 #define RX_TIMEOUT 1000 /* timeout in ms */
115
116 struct dw_spi_plat {
117 s32 frequency; /* Default clock frequency, -1 for none */
118 void __iomem *regs;
119 };
120
121 struct dw_spi_priv {
122 struct clk clk;
123 struct reset_ctl_bulk resets;
124 struct gpio_desc cs_gpio; /* External chip-select gpio */
125
126 u32 (*update_cr0)(struct dw_spi_priv *priv);
127
128 void __iomem *regs;
129 unsigned long bus_clk_rate;
130 unsigned int freq; /* Default frequency */
131 unsigned int mode;
132
133 const void *tx;
134 const void *tx_end;
135 void *rx;
136 void *rx_end;
137 u32 fifo_len; /* depth of the FIFO buffer */
138 u32 max_xfer; /* Maximum transfer size (in bits) */
139
140 int bits_per_word;
141 int len;
142 u8 cs; /* chip select pin */
143 u8 tmode; /* TR/TO/RO/EEPROM */
144 u8 type; /* SPI/SSP/MicroWire */
145 };
146
dw_read(struct dw_spi_priv * priv,u32 offset)147 static inline u32 dw_read(struct dw_spi_priv *priv, u32 offset)
148 {
149 return __raw_readl(priv->regs + offset);
150 }
151
dw_write(struct dw_spi_priv * priv,u32 offset,u32 val)152 static inline void dw_write(struct dw_spi_priv *priv, u32 offset, u32 val)
153 {
154 __raw_writel(val, priv->regs + offset);
155 }
156
dw_spi_dw16_update_cr0(struct dw_spi_priv * priv)157 static u32 dw_spi_dw16_update_cr0(struct dw_spi_priv *priv)
158 {
159 return FIELD_PREP(CTRLR0_DFS_MASK, priv->bits_per_word - 1)
160 | FIELD_PREP(CTRLR0_FRF_MASK, priv->type)
161 | FIELD_PREP(CTRLR0_MODE_MASK, priv->mode)
162 | FIELD_PREP(CTRLR0_TMOD_MASK, priv->tmode);
163 }
164
dw_spi_dw32_update_cr0(struct dw_spi_priv * priv)165 static u32 dw_spi_dw32_update_cr0(struct dw_spi_priv *priv)
166 {
167 return FIELD_PREP(CTRLR0_DFS_32_MASK, priv->bits_per_word - 1)
168 | FIELD_PREP(CTRLR0_FRF_MASK, priv->type)
169 | FIELD_PREP(CTRLR0_MODE_MASK, priv->mode)
170 | FIELD_PREP(CTRLR0_TMOD_MASK, priv->tmode);
171 }
172
dw_spi_dwc_update_cr0(struct dw_spi_priv * priv)173 static u32 dw_spi_dwc_update_cr0(struct dw_spi_priv *priv)
174 {
175 return FIELD_PREP(DWC_SSI_CTRLR0_DFS_MASK, priv->bits_per_word - 1)
176 | FIELD_PREP(DWC_SSI_CTRLR0_FRF_MASK, priv->type)
177 | FIELD_PREP(DWC_SSI_CTRLR0_MODE_MASK, priv->mode)
178 | FIELD_PREP(DWC_SSI_CTRLR0_TMOD_MASK, priv->tmode);
179 }
180
dw_spi_apb_init(struct udevice * bus,struct dw_spi_priv * priv)181 static int dw_spi_apb_init(struct udevice *bus, struct dw_spi_priv *priv)
182 {
183 /* If we read zeros from DFS, then we need to use DFS_32 instead */
184 dw_write(priv, DW_SPI_SSIENR, 0);
185 dw_write(priv, DW_SPI_CTRLR0, 0xffffffff);
186 if (FIELD_GET(CTRLR0_DFS_MASK, dw_read(priv, DW_SPI_CTRLR0))) {
187 priv->max_xfer = 16;
188 priv->update_cr0 = dw_spi_dw16_update_cr0;
189 } else {
190 priv->max_xfer = 32;
191 priv->update_cr0 = dw_spi_dw32_update_cr0;
192 }
193
194 return 0;
195 }
196
dw_spi_dwc_init(struct udevice * bus,struct dw_spi_priv * priv)197 static int dw_spi_dwc_init(struct udevice *bus, struct dw_spi_priv *priv)
198 {
199 priv->max_xfer = 32;
200 priv->update_cr0 = dw_spi_dwc_update_cr0;
201 return 0;
202 }
203
request_gpio_cs(struct udevice * bus)204 static int request_gpio_cs(struct udevice *bus)
205 {
206 #if CONFIG_IS_ENABLED(DM_GPIO) && !defined(CONFIG_SPL_BUILD)
207 struct dw_spi_priv *priv = dev_get_priv(bus);
208 int ret;
209
210 /* External chip select gpio line is optional */
211 ret = gpio_request_by_name(bus, "cs-gpios", 0, &priv->cs_gpio,
212 GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
213 if (ret == -ENOENT)
214 return 0;
215
216 if (ret < 0) {
217 dev_err(bus, "Couldn't request gpio! (error %d)\n", ret);
218 return ret;
219 }
220
221 if (dm_gpio_is_valid(&priv->cs_gpio)) {
222 dm_gpio_set_dir_flags(&priv->cs_gpio,
223 GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
224 }
225
226 dev_dbg(bus, "Using external gpio for CS management\n");
227 #endif
228 return 0;
229 }
230
dw_spi_of_to_plat(struct udevice * bus)231 static int dw_spi_of_to_plat(struct udevice *bus)
232 {
233 struct dw_spi_plat *plat = dev_get_plat(bus);
234
235 plat->regs = dev_read_addr_ptr(bus);
236 if (!plat->regs)
237 return -EINVAL;
238
239 /* Use 500KHz as a suitable default */
240 plat->frequency = dev_read_u32_default(bus, "spi-max-frequency",
241 500000);
242
243 if (dev_read_bool(bus, "spi-slave"))
244 return -EINVAL;
245
246 dev_info(bus, "max-frequency=%d\n", plat->frequency);
247
248 return request_gpio_cs(bus);
249 }
250
251 /* Restart the controller, disable all interrupts, clean rx fifo */
spi_hw_init(struct udevice * bus,struct dw_spi_priv * priv)252 static void spi_hw_init(struct udevice *bus, struct dw_spi_priv *priv)
253 {
254 dw_write(priv, DW_SPI_SSIENR, 0);
255 dw_write(priv, DW_SPI_IMR, 0xff);
256 dw_write(priv, DW_SPI_SSIENR, 1);
257
258 /*
259 * Try to detect the FIFO depth if not set by interface driver,
260 * the depth could be from 2 to 256 from HW spec
261 */
262 if (!priv->fifo_len) {
263 u32 fifo;
264
265 for (fifo = 1; fifo < 256; fifo++) {
266 dw_write(priv, DW_SPI_TXFTLR, fifo);
267 if (fifo != dw_read(priv, DW_SPI_TXFTLR))
268 break;
269 }
270
271 priv->fifo_len = (fifo == 1) ? 0 : fifo;
272 dw_write(priv, DW_SPI_TXFTLR, 0);
273 }
274 dev_dbg(bus, "fifo_len=%d\n", priv->fifo_len);
275 }
276
277 /*
278 * We define dw_spi_get_clk function as 'weak' as some targets
279 * (like SOCFPGA_GEN5 and SOCFPGA_ARRIA10) don't use standard clock API
280 * and implement dw_spi_get_clk their own way in their clock manager.
281 */
dw_spi_get_clk(struct udevice * bus,ulong * rate)282 __weak int dw_spi_get_clk(struct udevice *bus, ulong *rate)
283 {
284 struct dw_spi_priv *priv = dev_get_priv(bus);
285 int ret;
286
287 ret = clk_get_by_index(bus, 0, &priv->clk);
288 if (ret)
289 return ret;
290
291 ret = clk_enable(&priv->clk);
292 if (ret && ret != -ENOSYS && ret != -ENOTSUPP)
293 return ret;
294
295 *rate = clk_get_rate(&priv->clk);
296 if (!*rate)
297 goto err_rate;
298
299 dev_dbg(bus, "Got clock via device tree: %lu Hz\n", *rate);
300
301 return 0;
302
303 err_rate:
304 clk_disable(&priv->clk);
305 clk_free(&priv->clk);
306
307 return -EINVAL;
308 }
309
dw_spi_reset(struct udevice * bus)310 static int dw_spi_reset(struct udevice *bus)
311 {
312 int ret;
313 struct dw_spi_priv *priv = dev_get_priv(bus);
314
315 ret = reset_get_bulk(bus, &priv->resets);
316 if (ret) {
317 /*
318 * Return 0 if error due to !CONFIG_DM_RESET and reset
319 * DT property is not present.
320 */
321 if (ret == -ENOENT || ret == -ENOTSUPP)
322 return 0;
323
324 dev_warn(bus, "Couldn't find/assert reset device (error %d)\n",
325 ret);
326 return ret;
327 }
328
329 ret = reset_deassert_bulk(&priv->resets);
330 if (ret) {
331 reset_release_bulk(&priv->resets);
332 dev_err(bus, "Failed to de-assert reset for SPI (error %d)\n",
333 ret);
334 return ret;
335 }
336
337 return 0;
338 }
339
340 typedef int (*dw_spi_init_t)(struct udevice *bus, struct dw_spi_priv *priv);
341
dw_spi_probe(struct udevice * bus)342 static int dw_spi_probe(struct udevice *bus)
343 {
344 dw_spi_init_t init = (dw_spi_init_t)dev_get_driver_data(bus);
345 struct dw_spi_plat *plat = dev_get_plat(bus);
346 struct dw_spi_priv *priv = dev_get_priv(bus);
347 int ret;
348 u32 version;
349
350 priv->regs = plat->regs;
351 priv->freq = plat->frequency;
352
353 ret = dw_spi_get_clk(bus, &priv->bus_clk_rate);
354 if (ret)
355 return ret;
356
357 ret = dw_spi_reset(bus);
358 if (ret)
359 return ret;
360
361 if (!init)
362 return -EINVAL;
363 ret = init(bus, priv);
364 if (ret)
365 return ret;
366
367 version = dw_read(priv, DW_SPI_VERSION);
368 dev_dbg(bus, "ssi_version_id=%c.%c%c%c ssi_max_xfer_size=%u\n",
369 version >> 24, version >> 16, version >> 8, version,
370 priv->max_xfer);
371
372 /* Currently only bits_per_word == 8 supported */
373 priv->bits_per_word = 8;
374
375 priv->tmode = 0; /* Tx & Rx */
376
377 /* Basic HW init */
378 spi_hw_init(bus, priv);
379
380 return 0;
381 }
382
383 /* Return the max entries we can fill into tx fifo */
tx_max(struct dw_spi_priv * priv)384 static inline u32 tx_max(struct dw_spi_priv *priv)
385 {
386 u32 tx_left, tx_room, rxtx_gap;
387
388 tx_left = (priv->tx_end - priv->tx) / (priv->bits_per_word >> 3);
389 tx_room = priv->fifo_len - dw_read(priv, DW_SPI_TXFLR);
390
391 /*
392 * Another concern is about the tx/rx mismatch, we
393 * thought about using (priv->fifo_len - rxflr - txflr) as
394 * one maximum value for tx, but it doesn't cover the
395 * data which is out of tx/rx fifo and inside the
396 * shift registers. So a control from sw point of
397 * view is taken.
398 */
399 rxtx_gap = ((priv->rx_end - priv->rx) - (priv->tx_end - priv->tx)) /
400 (priv->bits_per_word >> 3);
401
402 return min3(tx_left, tx_room, (u32)(priv->fifo_len - rxtx_gap));
403 }
404
405 /* Return the max entries we should read out of rx fifo */
rx_max(struct dw_spi_priv * priv)406 static inline u32 rx_max(struct dw_spi_priv *priv)
407 {
408 u32 rx_left = (priv->rx_end - priv->rx) / (priv->bits_per_word >> 3);
409
410 return min_t(u32, rx_left, dw_read(priv, DW_SPI_RXFLR));
411 }
412
dw_writer(struct dw_spi_priv * priv)413 static void dw_writer(struct dw_spi_priv *priv)
414 {
415 u32 max = tx_max(priv);
416 u32 txw = 0xFFFFFFFF;
417
418 while (max--) {
419 /* Set the tx word if the transfer's original "tx" is not null */
420 if (priv->tx_end - priv->len) {
421 if (priv->bits_per_word == 8)
422 txw = *(u8 *)(priv->tx);
423 else
424 txw = *(u16 *)(priv->tx);
425 }
426 dw_write(priv, DW_SPI_DR, txw);
427 log_content("tx=0x%02x\n", txw);
428 priv->tx += priv->bits_per_word >> 3;
429 }
430 }
431
dw_reader(struct dw_spi_priv * priv)432 static void dw_reader(struct dw_spi_priv *priv)
433 {
434 u32 max = rx_max(priv);
435 u16 rxw;
436
437 while (max--) {
438 rxw = dw_read(priv, DW_SPI_DR);
439 log_content("rx=0x%02x\n", rxw);
440
441 /* Care about rx if the transfer's original "rx" is not null */
442 if (priv->rx_end - priv->len) {
443 if (priv->bits_per_word == 8)
444 *(u8 *)(priv->rx) = rxw;
445 else
446 *(u16 *)(priv->rx) = rxw;
447 }
448 priv->rx += priv->bits_per_word >> 3;
449 }
450 }
451
poll_transfer(struct dw_spi_priv * priv)452 static int poll_transfer(struct dw_spi_priv *priv)
453 {
454 do {
455 dw_writer(priv);
456 dw_reader(priv);
457 } while (priv->rx_end > priv->rx);
458
459 return 0;
460 }
461
462 /*
463 * We define external_cs_manage function as 'weak' as some targets
464 * (like MSCC Ocelot) don't control the external CS pin using a GPIO
465 * controller. These SoCs use specific registers to control by
466 * software the SPI pins (and especially the CS).
467 */
external_cs_manage(struct udevice * dev,bool on)468 __weak void external_cs_manage(struct udevice *dev, bool on)
469 {
470 #if CONFIG_IS_ENABLED(DM_GPIO) && !defined(CONFIG_SPL_BUILD)
471 struct dw_spi_priv *priv = dev_get_priv(dev->parent);
472
473 if (!dm_gpio_is_valid(&priv->cs_gpio))
474 return;
475
476 dm_gpio_set_value(&priv->cs_gpio, on ? 1 : 0);
477 #endif
478 }
479
dw_spi_xfer(struct udevice * dev,unsigned int bitlen,const void * dout,void * din,unsigned long flags)480 static int dw_spi_xfer(struct udevice *dev, unsigned int bitlen,
481 const void *dout, void *din, unsigned long flags)
482 {
483 struct udevice *bus = dev->parent;
484 struct dw_spi_priv *priv = dev_get_priv(bus);
485 const u8 *tx = dout;
486 u8 *rx = din;
487 int ret = 0;
488 u32 cr0 = 0;
489 u32 val;
490 u32 cs;
491
492 /* spi core configured to do 8 bit transfers */
493 if (bitlen % 8) {
494 dev_err(dev, "Non byte aligned SPI transfer.\n");
495 return -1;
496 }
497
498 /* Start the transaction if necessary. */
499 if (flags & SPI_XFER_BEGIN)
500 external_cs_manage(dev, false);
501
502 if (rx && tx)
503 priv->tmode = CTRLR0_TMOD_TR;
504 else if (rx)
505 priv->tmode = CTRLR0_TMOD_RO;
506 else
507 /*
508 * In transmit only mode (CTRL0_TMOD_TO) input FIFO never gets
509 * any data which breaks our logic in poll_transfer() above.
510 */
511 priv->tmode = CTRLR0_TMOD_TR;
512
513 cr0 = priv->update_cr0(priv);
514
515 priv->len = bitlen >> 3;
516
517 priv->tx = (void *)tx;
518 priv->tx_end = priv->tx + priv->len;
519 priv->rx = rx;
520 priv->rx_end = priv->rx + priv->len;
521
522 /* Disable controller before writing control registers */
523 dw_write(priv, DW_SPI_SSIENR, 0);
524
525 dev_dbg(dev, "cr0=%08x rx=%p tx=%p len=%d [bytes]\n", cr0, rx, tx,
526 priv->len);
527 /* Reprogram cr0 only if changed */
528 if (dw_read(priv, DW_SPI_CTRLR0) != cr0)
529 dw_write(priv, DW_SPI_CTRLR0, cr0);
530
531 /*
532 * Configure the desired SS (slave select 0...3) in the controller
533 * The DW SPI controller will activate and deactivate this CS
534 * automatically. So no cs_activate() etc is needed in this driver.
535 */
536 cs = spi_chip_select(dev);
537 dw_write(priv, DW_SPI_SER, 1 << cs);
538
539 /* Enable controller after writing control registers */
540 dw_write(priv, DW_SPI_SSIENR, 1);
541
542 /* Start transfer in a polling loop */
543 ret = poll_transfer(priv);
544
545 /*
546 * Wait for current transmit operation to complete.
547 * Otherwise if some data still exists in Tx FIFO it can be
548 * silently flushed, i.e. dropped on disabling of the controller,
549 * which happens when writing 0 to DW_SPI_SSIENR which happens
550 * in the beginning of new transfer.
551 */
552 if (readl_poll_timeout(priv->regs + DW_SPI_SR, val,
553 (val & SR_TF_EMPT) && !(val & SR_BUSY),
554 RX_TIMEOUT * 1000)) {
555 ret = -ETIMEDOUT;
556 }
557
558 /* Stop the transaction if necessary */
559 if (flags & SPI_XFER_END)
560 external_cs_manage(dev, true);
561
562 return ret;
563 }
564
565 /*
566 * This function is necessary for reading SPI flash with the native CS
567 * c.f. https://lkml.org/lkml/2015/12/23/132
568 */
dw_spi_exec_op(struct spi_slave * slave,const struct spi_mem_op * op)569 static int dw_spi_exec_op(struct spi_slave *slave, const struct spi_mem_op *op)
570 {
571 bool read = op->data.dir == SPI_MEM_DATA_IN;
572 int pos, i, ret = 0;
573 struct udevice *bus = slave->dev->parent;
574 struct dw_spi_priv *priv = dev_get_priv(bus);
575 u8 op_len = sizeof(op->cmd.opcode) + op->addr.nbytes + op->dummy.nbytes;
576 u8 op_buf[op_len];
577 u32 cr0;
578
579 if (read)
580 priv->tmode = CTRLR0_TMOD_EPROMREAD;
581 else
582 priv->tmode = CTRLR0_TMOD_TO;
583
584 cr0 = priv->update_cr0(priv);
585 dev_dbg(bus, "cr0=%08x buf=%p len=%u [bytes]\n", cr0, op->data.buf.in,
586 op->data.nbytes);
587
588 dw_write(priv, DW_SPI_SSIENR, 0);
589 dw_write(priv, DW_SPI_CTRLR0, cr0);
590 if (read)
591 dw_write(priv, DW_SPI_CTRLR1, op->data.nbytes - 1);
592 dw_write(priv, DW_SPI_SSIENR, 1);
593
594 /* From spi_mem_exec_op */
595 pos = 0;
596 op_buf[pos++] = op->cmd.opcode;
597 if (op->addr.nbytes) {
598 for (i = 0; i < op->addr.nbytes; i++)
599 op_buf[pos + i] = op->addr.val >>
600 (8 * (op->addr.nbytes - i - 1));
601
602 pos += op->addr.nbytes;
603 }
604 if (op->dummy.nbytes)
605 memset(op_buf + pos, 0xff, op->dummy.nbytes);
606
607 external_cs_manage(slave->dev, false);
608
609 priv->tx = &op_buf;
610 priv->tx_end = priv->tx + op_len;
611 priv->rx = NULL;
612 priv->rx_end = NULL;
613 while (priv->tx != priv->tx_end)
614 dw_writer(priv);
615
616 /*
617 * XXX: The following are tight loops! Enabling debug messages may cause
618 * them to fail because we are not reading/writing the fifo fast enough.
619 */
620 if (read) {
621 priv->rx = op->data.buf.in;
622 priv->rx_end = priv->rx + op->data.nbytes;
623
624 dw_write(priv, DW_SPI_SER, 1 << spi_chip_select(slave->dev));
625 while (priv->rx != priv->rx_end)
626 dw_reader(priv);
627 } else {
628 u32 val;
629
630 priv->tx = op->data.buf.out;
631 priv->tx_end = priv->tx + op->data.nbytes;
632
633 /* Fill up the write fifo before starting the transfer */
634 dw_writer(priv);
635 dw_write(priv, DW_SPI_SER, 1 << spi_chip_select(slave->dev));
636 while (priv->tx != priv->tx_end)
637 dw_writer(priv);
638
639 if (readl_poll_timeout(priv->regs + DW_SPI_SR, val,
640 (val & SR_TF_EMPT) && !(val & SR_BUSY),
641 RX_TIMEOUT * 1000)) {
642 ret = -ETIMEDOUT;
643 }
644 }
645
646 dw_write(priv, DW_SPI_SER, 0);
647 external_cs_manage(slave->dev, true);
648
649 dev_dbg(bus, "%u bytes xfered\n", op->data.nbytes);
650 return ret;
651 }
652
653 /* The size of ctrl1 limits data transfers to 64K */
dw_spi_adjust_op_size(struct spi_slave * slave,struct spi_mem_op * op)654 static int dw_spi_adjust_op_size(struct spi_slave *slave, struct spi_mem_op *op)
655 {
656 op->data.nbytes = min(op->data.nbytes, (unsigned int)SZ_64K);
657
658 return 0;
659 }
660
661 static const struct spi_controller_mem_ops dw_spi_mem_ops = {
662 .exec_op = dw_spi_exec_op,
663 .adjust_op_size = dw_spi_adjust_op_size,
664 };
665
dw_spi_set_speed(struct udevice * bus,uint speed)666 static int dw_spi_set_speed(struct udevice *bus, uint speed)
667 {
668 struct dw_spi_plat *plat = dev_get_plat(bus);
669 struct dw_spi_priv *priv = dev_get_priv(bus);
670 u16 clk_div;
671
672 if (speed > plat->frequency)
673 speed = plat->frequency;
674
675 /* Disable controller before writing control registers */
676 dw_write(priv, DW_SPI_SSIENR, 0);
677
678 /* clk_div doesn't support odd number */
679 clk_div = priv->bus_clk_rate / speed;
680 clk_div = (clk_div + 1) & 0xfffe;
681 dw_write(priv, DW_SPI_BAUDR, clk_div);
682
683 /* Enable controller after writing control registers */
684 dw_write(priv, DW_SPI_SSIENR, 1);
685
686 priv->freq = speed;
687 dev_dbg(bus, "speed=%d clk_div=%d\n", priv->freq, clk_div);
688
689 return 0;
690 }
691
dw_spi_set_mode(struct udevice * bus,uint mode)692 static int dw_spi_set_mode(struct udevice *bus, uint mode)
693 {
694 struct dw_spi_priv *priv = dev_get_priv(bus);
695
696 /*
697 * Can't set mode yet. Since this depends on if rx, tx, or
698 * rx & tx is requested. So we have to defer this to the
699 * real transfer function.
700 */
701 priv->mode = mode;
702 dev_dbg(bus, "mode=%d\n", priv->mode);
703
704 return 0;
705 }
706
dw_spi_remove(struct udevice * bus)707 static int dw_spi_remove(struct udevice *bus)
708 {
709 struct dw_spi_priv *priv = dev_get_priv(bus);
710 int ret;
711
712 ret = reset_release_bulk(&priv->resets);
713 if (ret)
714 return ret;
715
716 #if CONFIG_IS_ENABLED(CLK)
717 ret = clk_disable(&priv->clk);
718 if (ret)
719 return ret;
720
721 ret = clk_free(&priv->clk);
722 if (ret)
723 return ret;
724 #endif
725 return 0;
726 }
727
728 static const struct dm_spi_ops dw_spi_ops = {
729 .xfer = dw_spi_xfer,
730 .mem_ops = &dw_spi_mem_ops,
731 .set_speed = dw_spi_set_speed,
732 .set_mode = dw_spi_set_mode,
733 /*
734 * cs_info is not needed, since we require all chip selects to be
735 * in the device tree explicitly
736 */
737 };
738
739 static const struct udevice_id dw_spi_ids[] = {
740 /* Generic compatible strings */
741
742 { .compatible = "snps,dw-apb-ssi", .data = (ulong)dw_spi_apb_init },
743 { .compatible = "snps,dw-apb-ssi-3.20a", .data = (ulong)dw_spi_apb_init },
744 { .compatible = "snps,dw-apb-ssi-3.22a", .data = (ulong)dw_spi_apb_init },
745 /* First version with SSI_MAX_XFER_SIZE */
746 { .compatible = "snps,dw-apb-ssi-3.23a", .data = (ulong)dw_spi_apb_init },
747 /* First version with Dual/Quad SPI; unused by this driver */
748 { .compatible = "snps,dw-apb-ssi-4.00a", .data = (ulong)dw_spi_apb_init },
749 { .compatible = "snps,dw-apb-ssi-4.01", .data = (ulong)dw_spi_apb_init },
750 { .compatible = "snps,dwc-ssi-1.01a", .data = (ulong)dw_spi_dwc_init },
751
752 /* Compatible strings for specific SoCs */
753
754 /*
755 * Both the Cyclone V and Arria V share a device tree and have the same
756 * version of this device. This compatible string is used for those
757 * devices, and is not used for sofpgas in general.
758 */
759 { .compatible = "altr,socfpga-spi", .data = (ulong)dw_spi_apb_init },
760 { .compatible = "altr,socfpga-arria10-spi", .data = (ulong)dw_spi_apb_init },
761 { .compatible = "canaan,kendryte-k210-spi", .data = (ulong)dw_spi_apb_init },
762 { .compatible = "canaan,kendryte-k210-ssi", .data = (ulong)dw_spi_dwc_init },
763 { .compatible = "intel,stratix10-spi", .data = (ulong)dw_spi_apb_init },
764 { .compatible = "intel,agilex-spi", .data = (ulong)dw_spi_apb_init },
765 { .compatible = "mscc,ocelot-spi", .data = (ulong)dw_spi_apb_init },
766 { .compatible = "mscc,jaguar2-spi", .data = (ulong)dw_spi_apb_init },
767 { .compatible = "snps,axs10x-spi", .data = (ulong)dw_spi_apb_init },
768 { .compatible = "snps,hsdk-spi", .data = (ulong)dw_spi_apb_init },
769 { }
770 };
771
772 U_BOOT_DRIVER(dw_spi) = {
773 .name = "dw_spi",
774 .id = UCLASS_SPI,
775 .of_match = dw_spi_ids,
776 .ops = &dw_spi_ops,
777 .of_to_plat = dw_spi_of_to_plat,
778 .plat_auto = sizeof(struct dw_spi_plat),
779 .priv_auto = sizeof(struct dw_spi_priv),
780 .probe = dw_spi_probe,
781 .remove = dw_spi_remove,
782 };
783