1 // SPDX-License-Identifier: GPL-2.0
2 /**
3 * core.c - DesignWare USB3 DRD Controller Core file
4 *
5 * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
6 *
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 *
10 * Taken from Linux Kernel v3.19-rc1 (drivers/usb/dwc3/core.c) and ported
11 * to uboot.
12 *
13 * commit cd72f890d2 : usb: dwc3: core: enable phy suspend quirk on non-FPGA
14 */
15
16 #include <common.h>
17 #include <cpu_func.h>
18 #include <malloc.h>
19 #include <dwc3-uboot.h>
20 #include <dm/device_compat.h>
21 #include <dm/devres.h>
22 #include <linux/bug.h>
23 #include <linux/delay.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/err.h>
26 #include <linux/ioport.h>
27 #include <dm.h>
28 #include <generic-phy.h>
29 #include <linux/usb/ch9.h>
30 #include <linux/usb/gadget.h>
31
32 #include "core.h"
33 #include "gadget.h"
34 #include "io.h"
35
36 #include "linux-compat.h"
37
38 static LIST_HEAD(dwc3_list);
39 /* -------------------------------------------------------------------------- */
40
dwc3_set_mode(struct dwc3 * dwc,u32 mode)41 static void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
42 {
43 u32 reg;
44
45 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
46 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
47 reg |= DWC3_GCTL_PRTCAPDIR(mode);
48 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
49 }
50
51 /**
52 * dwc3_core_soft_reset - Issues core soft reset and PHY reset
53 * @dwc: pointer to our context structure
54 */
dwc3_core_soft_reset(struct dwc3 * dwc)55 static int dwc3_core_soft_reset(struct dwc3 *dwc)
56 {
57 u32 reg;
58
59 /* Before Resetting PHY, put Core in Reset */
60 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
61 reg |= DWC3_GCTL_CORESOFTRESET;
62 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
63
64 /* Assert USB3 PHY reset */
65 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
66 reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST;
67 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
68
69 /* Assert USB2 PHY reset */
70 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
71 reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST;
72 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
73
74 mdelay(100);
75
76 /* Clear USB3 PHY reset */
77 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
78 reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST;
79 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
80
81 /* Clear USB2 PHY reset */
82 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
83 reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST;
84 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
85
86 mdelay(100);
87
88 /* After PHYs are stable we can take Core out of reset state */
89 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
90 reg &= ~DWC3_GCTL_CORESOFTRESET;
91 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
92
93 return 0;
94 }
95
96 /**
97 * dwc3_free_one_event_buffer - Frees one event buffer
98 * @dwc: Pointer to our controller context structure
99 * @evt: Pointer to event buffer to be freed
100 */
dwc3_free_one_event_buffer(struct dwc3 * dwc,struct dwc3_event_buffer * evt)101 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
102 struct dwc3_event_buffer *evt)
103 {
104 dma_free_coherent(evt->buf);
105 }
106
107 /**
108 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
109 * @dwc: Pointer to our controller context structure
110 * @length: size of the event buffer
111 *
112 * Returns a pointer to the allocated event buffer structure on success
113 * otherwise ERR_PTR(errno).
114 */
dwc3_alloc_one_event_buffer(struct dwc3 * dwc,unsigned length)115 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
116 unsigned length)
117 {
118 struct dwc3_event_buffer *evt;
119
120 evt = devm_kzalloc((struct udevice *)dwc->dev, sizeof(*evt),
121 GFP_KERNEL);
122 if (!evt)
123 return ERR_PTR(-ENOMEM);
124
125 evt->dwc = dwc;
126 evt->length = length;
127 evt->buf = dma_alloc_coherent(length,
128 (unsigned long *)&evt->dma);
129 if (!evt->buf)
130 return ERR_PTR(-ENOMEM);
131
132 dwc3_flush_cache((uintptr_t)evt->buf, evt->length);
133
134 return evt;
135 }
136
137 /**
138 * dwc3_free_event_buffers - frees all allocated event buffers
139 * @dwc: Pointer to our controller context structure
140 */
dwc3_free_event_buffers(struct dwc3 * dwc)141 static void dwc3_free_event_buffers(struct dwc3 *dwc)
142 {
143 struct dwc3_event_buffer *evt;
144 int i;
145
146 for (i = 0; i < dwc->num_event_buffers; i++) {
147 evt = dwc->ev_buffs[i];
148 if (evt)
149 dwc3_free_one_event_buffer(dwc, evt);
150 }
151 }
152
153 /**
154 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
155 * @dwc: pointer to our controller context structure
156 * @length: size of event buffer
157 *
158 * Returns 0 on success otherwise negative errno. In the error case, dwc
159 * may contain some buffers allocated but not all which were requested.
160 */
dwc3_alloc_event_buffers(struct dwc3 * dwc,unsigned length)161 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
162 {
163 int num;
164 int i;
165
166 num = DWC3_NUM_INT(dwc->hwparams.hwparams1);
167 dwc->num_event_buffers = num;
168
169 dwc->ev_buffs = memalign(CONFIG_SYS_CACHELINE_SIZE,
170 sizeof(*dwc->ev_buffs) * num);
171 if (!dwc->ev_buffs)
172 return -ENOMEM;
173
174 for (i = 0; i < num; i++) {
175 struct dwc3_event_buffer *evt;
176
177 evt = dwc3_alloc_one_event_buffer(dwc, length);
178 if (IS_ERR(evt)) {
179 dev_err(dwc->dev, "can't allocate event buffer\n");
180 return PTR_ERR(evt);
181 }
182 dwc->ev_buffs[i] = evt;
183 }
184
185 return 0;
186 }
187
188 /**
189 * dwc3_event_buffers_setup - setup our allocated event buffers
190 * @dwc: pointer to our controller context structure
191 *
192 * Returns 0 on success otherwise negative errno.
193 */
dwc3_event_buffers_setup(struct dwc3 * dwc)194 static int dwc3_event_buffers_setup(struct dwc3 *dwc)
195 {
196 struct dwc3_event_buffer *evt;
197 int n;
198
199 for (n = 0; n < dwc->num_event_buffers; n++) {
200 evt = dwc->ev_buffs[n];
201 dev_dbg(dwc->dev, "Event buf %p dma %08llx length %d\n",
202 evt->buf, (unsigned long long) evt->dma,
203 evt->length);
204
205 evt->lpos = 0;
206
207 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n),
208 lower_32_bits(evt->dma));
209 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n),
210 upper_32_bits(evt->dma));
211 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n),
212 DWC3_GEVNTSIZ_SIZE(evt->length));
213 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
214 }
215
216 return 0;
217 }
218
dwc3_event_buffers_cleanup(struct dwc3 * dwc)219 static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
220 {
221 struct dwc3_event_buffer *evt;
222 int n;
223
224 for (n = 0; n < dwc->num_event_buffers; n++) {
225 evt = dwc->ev_buffs[n];
226
227 evt->lpos = 0;
228
229 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0);
230 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0);
231 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), DWC3_GEVNTSIZ_INTMASK
232 | DWC3_GEVNTSIZ_SIZE(0));
233 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
234 }
235 }
236
dwc3_alloc_scratch_buffers(struct dwc3 * dwc)237 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
238 {
239 if (!dwc->has_hibernation)
240 return 0;
241
242 if (!dwc->nr_scratch)
243 return 0;
244
245 dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
246 DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
247 if (!dwc->scratchbuf)
248 return -ENOMEM;
249
250 return 0;
251 }
252
dwc3_setup_scratch_buffers(struct dwc3 * dwc)253 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
254 {
255 dma_addr_t scratch_addr;
256 u32 param;
257 int ret;
258
259 if (!dwc->has_hibernation)
260 return 0;
261
262 if (!dwc->nr_scratch)
263 return 0;
264
265 scratch_addr = dma_map_single(dwc->scratchbuf,
266 dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
267 DMA_BIDIRECTIONAL);
268 if (dma_mapping_error(dwc->dev, scratch_addr)) {
269 dev_err(dwc->dev, "failed to map scratch buffer\n");
270 ret = -EFAULT;
271 goto err0;
272 }
273
274 dwc->scratch_addr = scratch_addr;
275
276 param = lower_32_bits(scratch_addr);
277
278 ret = dwc3_send_gadget_generic_command(dwc,
279 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
280 if (ret < 0)
281 goto err1;
282
283 param = upper_32_bits(scratch_addr);
284
285 ret = dwc3_send_gadget_generic_command(dwc,
286 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
287 if (ret < 0)
288 goto err1;
289
290 return 0;
291
292 err1:
293 dma_unmap_single(scratch_addr, dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
294 DMA_BIDIRECTIONAL);
295
296 err0:
297 return ret;
298 }
299
dwc3_free_scratch_buffers(struct dwc3 * dwc)300 static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
301 {
302 if (!dwc->has_hibernation)
303 return;
304
305 if (!dwc->nr_scratch)
306 return;
307
308 dma_unmap_single(dwc->scratch_addr, dwc->nr_scratch *
309 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
310 kfree(dwc->scratchbuf);
311 }
312
dwc3_core_num_eps(struct dwc3 * dwc)313 static void dwc3_core_num_eps(struct dwc3 *dwc)
314 {
315 struct dwc3_hwparams *parms = &dwc->hwparams;
316
317 dwc->num_in_eps = DWC3_NUM_IN_EPS(parms);
318 dwc->num_out_eps = DWC3_NUM_EPS(parms) - dwc->num_in_eps;
319
320 dev_vdbg(dwc->dev, "found %d IN and %d OUT endpoints\n",
321 dwc->num_in_eps, dwc->num_out_eps);
322 }
323
dwc3_cache_hwparams(struct dwc3 * dwc)324 static void dwc3_cache_hwparams(struct dwc3 *dwc)
325 {
326 struct dwc3_hwparams *parms = &dwc->hwparams;
327
328 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
329 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
330 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
331 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
332 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
333 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
334 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
335 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
336 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
337 }
338
dwc3_hsphy_mode_setup(struct dwc3 * dwc)339 static void dwc3_hsphy_mode_setup(struct dwc3 *dwc)
340 {
341 enum usb_phy_interface hsphy_mode = dwc->hsphy_mode;
342 u32 reg;
343
344 /* Set dwc3 usb2 phy config */
345 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
346
347 switch (hsphy_mode) {
348 case USBPHY_INTERFACE_MODE_UTMI:
349 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
350 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
351 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
352 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
353 break;
354 case USBPHY_INTERFACE_MODE_UTMIW:
355 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
356 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
357 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
358 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
359 break;
360 default:
361 break;
362 }
363
364 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
365 }
366
367 /**
368 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
369 * @dwc: Pointer to our controller context structure
370 */
dwc3_phy_setup(struct dwc3 * dwc)371 static void dwc3_phy_setup(struct dwc3 *dwc)
372 {
373 u32 reg;
374
375 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
376
377 /*
378 * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
379 * to '0' during coreConsultant configuration. So default value
380 * will be '0' when the core is reset. Application needs to set it
381 * to '1' after the core initialization is completed.
382 */
383 if (dwc->revision > DWC3_REVISION_194A)
384 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
385
386 if (dwc->u2ss_inp3_quirk)
387 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
388
389 if (dwc->req_p1p2p3_quirk)
390 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
391
392 if (dwc->del_p1p2p3_quirk)
393 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
394
395 if (dwc->del_phy_power_chg_quirk)
396 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
397
398 if (dwc->lfps_filter_quirk)
399 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
400
401 if (dwc->rx_detect_poll_quirk)
402 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
403
404 if (dwc->tx_de_emphasis_quirk)
405 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
406
407 if (dwc->dis_u3_susphy_quirk)
408 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
409
410 if (dwc->dis_del_phy_power_chg_quirk)
411 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
412
413 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
414
415 dwc3_hsphy_mode_setup(dwc);
416
417 mdelay(100);
418
419 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
420
421 /*
422 * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
423 * '0' during coreConsultant configuration. So default value will
424 * be '0' when the core is reset. Application needs to set it to
425 * '1' after the core initialization is completed.
426 */
427 if (dwc->revision > DWC3_REVISION_194A)
428 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
429
430 if (dwc->dis_u2_susphy_quirk)
431 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
432
433 if (dwc->dis_enblslpm_quirk)
434 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
435
436 if (dwc->dis_u2_freeclk_exists_quirk)
437 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
438
439 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
440
441 mdelay(100);
442 }
443
444 /**
445 * dwc3_core_init - Low-level initialization of DWC3 Core
446 * @dwc: Pointer to our controller context structure
447 *
448 * Returns 0 on success otherwise negative errno.
449 */
dwc3_core_init(struct dwc3 * dwc)450 static int dwc3_core_init(struct dwc3 *dwc)
451 {
452 unsigned long timeout;
453 u32 hwparams4 = dwc->hwparams.hwparams4;
454 u32 reg;
455 int ret;
456
457 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
458 /* This should read as U3 followed by revision number */
459 if ((reg & DWC3_GSNPSID_MASK) != 0x55330000) {
460 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
461 ret = -ENODEV;
462 goto err0;
463 }
464 dwc->revision = reg;
465
466 /* Handle USB2.0-only core configuration */
467 if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
468 DWC3_GHWPARAMS3_SSPHY_IFC_DIS) {
469 if (dwc->maximum_speed == USB_SPEED_SUPER)
470 dwc->maximum_speed = USB_SPEED_HIGH;
471 }
472
473 /* issue device SoftReset too */
474 timeout = 5000;
475 dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST);
476 while (timeout--) {
477 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
478 if (!(reg & DWC3_DCTL_CSFTRST))
479 break;
480 };
481
482 if (!timeout) {
483 dev_err(dwc->dev, "Reset Timed Out\n");
484 ret = -ETIMEDOUT;
485 goto err0;
486 }
487
488 dwc3_phy_setup(dwc);
489
490 ret = dwc3_core_soft_reset(dwc);
491 if (ret)
492 goto err0;
493
494 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
495 reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
496
497 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
498 case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
499 /**
500 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
501 * issue which would cause xHCI compliance tests to fail.
502 *
503 * Because of that we cannot enable clock gating on such
504 * configurations.
505 *
506 * Refers to:
507 *
508 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
509 * SOF/ITP Mode Used
510 */
511 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
512 dwc->dr_mode == USB_DR_MODE_OTG) &&
513 (dwc->revision >= DWC3_REVISION_210A &&
514 dwc->revision <= DWC3_REVISION_250A))
515 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
516 else
517 reg &= ~DWC3_GCTL_DSBLCLKGTNG;
518 break;
519 case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
520 /* enable hibernation here */
521 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
522
523 /*
524 * REVISIT Enabling this bit so that host-mode hibernation
525 * will work. Device-mode hibernation is not yet implemented.
526 */
527 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
528 break;
529 default:
530 dev_dbg(dwc->dev, "No power optimization available\n");
531 }
532
533 /* check if current dwc3 is on simulation board */
534 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
535 dev_dbg(dwc->dev, "it is on FPGA board\n");
536 dwc->is_fpga = true;
537 }
538
539 if(dwc->disable_scramble_quirk && !dwc->is_fpga)
540 WARN(true,
541 "disable_scramble cannot be used on non-FPGA builds\n");
542
543 if (dwc->disable_scramble_quirk && dwc->is_fpga)
544 reg |= DWC3_GCTL_DISSCRAMBLE;
545 else
546 reg &= ~DWC3_GCTL_DISSCRAMBLE;
547
548 if (dwc->u2exit_lfps_quirk)
549 reg |= DWC3_GCTL_U2EXIT_LFPS;
550
551 /*
552 * WORKAROUND: DWC3 revisions <1.90a have a bug
553 * where the device can fail to connect at SuperSpeed
554 * and falls back to high-speed mode which causes
555 * the device to enter a Connect/Disconnect loop
556 */
557 if (dwc->revision < DWC3_REVISION_190A)
558 reg |= DWC3_GCTL_U2RSTECN;
559
560 dwc3_core_num_eps(dwc);
561
562 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
563
564 ret = dwc3_alloc_scratch_buffers(dwc);
565 if (ret)
566 goto err0;
567
568 ret = dwc3_setup_scratch_buffers(dwc);
569 if (ret)
570 goto err1;
571
572 return 0;
573
574 err1:
575 dwc3_free_scratch_buffers(dwc);
576
577 err0:
578 return ret;
579 }
580
dwc3_core_exit(struct dwc3 * dwc)581 static void dwc3_core_exit(struct dwc3 *dwc)
582 {
583 dwc3_free_scratch_buffers(dwc);
584 }
585
dwc3_core_init_mode(struct dwc3 * dwc)586 static int dwc3_core_init_mode(struct dwc3 *dwc)
587 {
588 int ret;
589
590 switch (dwc->dr_mode) {
591 case USB_DR_MODE_PERIPHERAL:
592 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
593 ret = dwc3_gadget_init(dwc);
594 if (ret) {
595 dev_err(dwc->dev, "failed to initialize gadget\n");
596 return ret;
597 }
598 break;
599 case USB_DR_MODE_HOST:
600 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
601 ret = dwc3_host_init(dwc);
602 if (ret) {
603 dev_err(dwc->dev, "failed to initialize host\n");
604 return ret;
605 }
606 break;
607 case USB_DR_MODE_OTG:
608 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG);
609 ret = dwc3_host_init(dwc);
610 if (ret) {
611 dev_err(dwc->dev, "failed to initialize host\n");
612 return ret;
613 }
614
615 ret = dwc3_gadget_init(dwc);
616 if (ret) {
617 dev_err(dwc->dev, "failed to initialize gadget\n");
618 return ret;
619 }
620 break;
621 default:
622 dev_err(dwc->dev,
623 "Unsupported mode of operation %d\n", dwc->dr_mode);
624 return -EINVAL;
625 }
626
627 return 0;
628 }
629
dwc3_gadget_run(struct dwc3 * dwc)630 static void dwc3_gadget_run(struct dwc3 *dwc)
631 {
632 dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_RUN_STOP);
633 mdelay(100);
634 }
635
dwc3_core_exit_mode(struct dwc3 * dwc)636 static void dwc3_core_exit_mode(struct dwc3 *dwc)
637 {
638 switch (dwc->dr_mode) {
639 case USB_DR_MODE_PERIPHERAL:
640 dwc3_gadget_exit(dwc);
641 break;
642 case USB_DR_MODE_HOST:
643 dwc3_host_exit(dwc);
644 break;
645 case USB_DR_MODE_OTG:
646 dwc3_host_exit(dwc);
647 dwc3_gadget_exit(dwc);
648 break;
649 default:
650 /* do nothing */
651 break;
652 }
653
654 /*
655 * switch back to peripheral mode
656 * This enables the phy to enter idle and then, if enabled, suspend.
657 */
658 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
659 dwc3_gadget_run(dwc);
660 }
661
662 #define DWC3_ALIGN_MASK (16 - 1)
663
664 /**
665 * dwc3_uboot_init - dwc3 core uboot initialization code
666 * @dwc3_dev: struct dwc3_device containing initialization data
667 *
668 * Entry point for dwc3 driver (equivalent to dwc3_probe in linux
669 * kernel driver). Pointer to dwc3_device should be passed containing
670 * base address and other initialization data. Returns '0' on success and
671 * a negative value on failure.
672 *
673 * Generally called from board_usb_init() implemented in board file.
674 */
dwc3_uboot_init(struct dwc3_device * dwc3_dev)675 int dwc3_uboot_init(struct dwc3_device *dwc3_dev)
676 {
677 struct dwc3 *dwc;
678 struct device *dev = NULL;
679 u8 lpm_nyet_threshold;
680 u8 tx_de_emphasis;
681 u8 hird_threshold;
682
683 int ret;
684
685 void *mem;
686
687 mem = devm_kzalloc((struct udevice *)dev,
688 sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
689 if (!mem)
690 return -ENOMEM;
691
692 dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1);
693 dwc->mem = mem;
694
695 dwc->regs = (void *)(uintptr_t)(dwc3_dev->base +
696 DWC3_GLOBALS_REGS_START);
697
698 /* default to highest possible threshold */
699 lpm_nyet_threshold = 0xff;
700
701 /* default to -3.5dB de-emphasis */
702 tx_de_emphasis = 1;
703
704 /*
705 * default to assert utmi_sleep_n and use maximum allowed HIRD
706 * threshold value of 0b1100
707 */
708 hird_threshold = 12;
709
710 dwc->maximum_speed = dwc3_dev->maximum_speed;
711 dwc->has_lpm_erratum = dwc3_dev->has_lpm_erratum;
712 if (dwc3_dev->lpm_nyet_threshold)
713 lpm_nyet_threshold = dwc3_dev->lpm_nyet_threshold;
714 dwc->is_utmi_l1_suspend = dwc3_dev->is_utmi_l1_suspend;
715 if (dwc3_dev->hird_threshold)
716 hird_threshold = dwc3_dev->hird_threshold;
717
718 dwc->needs_fifo_resize = dwc3_dev->tx_fifo_resize;
719 dwc->dr_mode = dwc3_dev->dr_mode;
720
721 dwc->disable_scramble_quirk = dwc3_dev->disable_scramble_quirk;
722 dwc->u2exit_lfps_quirk = dwc3_dev->u2exit_lfps_quirk;
723 dwc->u2ss_inp3_quirk = dwc3_dev->u2ss_inp3_quirk;
724 dwc->req_p1p2p3_quirk = dwc3_dev->req_p1p2p3_quirk;
725 dwc->del_p1p2p3_quirk = dwc3_dev->del_p1p2p3_quirk;
726 dwc->del_phy_power_chg_quirk = dwc3_dev->del_phy_power_chg_quirk;
727 dwc->lfps_filter_quirk = dwc3_dev->lfps_filter_quirk;
728 dwc->rx_detect_poll_quirk = dwc3_dev->rx_detect_poll_quirk;
729 dwc->dis_u3_susphy_quirk = dwc3_dev->dis_u3_susphy_quirk;
730 dwc->dis_u2_susphy_quirk = dwc3_dev->dis_u2_susphy_quirk;
731 dwc->dis_del_phy_power_chg_quirk = dwc3_dev->dis_del_phy_power_chg_quirk;
732 dwc->dis_tx_ipgap_linecheck_quirk = dwc3_dev->dis_tx_ipgap_linecheck_quirk;
733 dwc->dis_enblslpm_quirk = dwc3_dev->dis_enblslpm_quirk;
734 dwc->dis_u2_freeclk_exists_quirk = dwc3_dev->dis_u2_freeclk_exists_quirk;
735
736 dwc->tx_de_emphasis_quirk = dwc3_dev->tx_de_emphasis_quirk;
737 if (dwc3_dev->tx_de_emphasis)
738 tx_de_emphasis = dwc3_dev->tx_de_emphasis;
739
740 /* default to superspeed if no maximum_speed passed */
741 if (dwc->maximum_speed == USB_SPEED_UNKNOWN)
742 dwc->maximum_speed = USB_SPEED_SUPER;
743
744 dwc->lpm_nyet_threshold = lpm_nyet_threshold;
745 dwc->tx_de_emphasis = tx_de_emphasis;
746
747 dwc->hird_threshold = hird_threshold
748 | (dwc->is_utmi_l1_suspend << 4);
749
750 dwc->hsphy_mode = dwc3_dev->hsphy_mode;
751
752 dwc->index = dwc3_dev->index;
753
754 dwc3_cache_hwparams(dwc);
755
756 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
757 if (ret) {
758 dev_err(dwc->dev, "failed to allocate event buffers\n");
759 return -ENOMEM;
760 }
761
762 if (!IS_ENABLED(CONFIG_USB_DWC3_GADGET))
763 dwc->dr_mode = USB_DR_MODE_HOST;
764 else if (!IS_ENABLED(CONFIG_USB_HOST))
765 dwc->dr_mode = USB_DR_MODE_PERIPHERAL;
766
767 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
768 dwc->dr_mode = USB_DR_MODE_OTG;
769
770 ret = dwc3_core_init(dwc);
771 if (ret) {
772 dev_err(dwc->dev, "failed to initialize core\n");
773 goto err0;
774 }
775
776 ret = dwc3_event_buffers_setup(dwc);
777 if (ret) {
778 dev_err(dwc->dev, "failed to setup event buffers\n");
779 goto err1;
780 }
781
782 ret = dwc3_core_init_mode(dwc);
783 if (ret)
784 goto err2;
785
786 list_add_tail(&dwc->list, &dwc3_list);
787
788 return 0;
789
790 err2:
791 dwc3_event_buffers_cleanup(dwc);
792
793 err1:
794 dwc3_core_exit(dwc);
795
796 err0:
797 dwc3_free_event_buffers(dwc);
798
799 return ret;
800 }
801
802 /**
803 * dwc3_uboot_exit - dwc3 core uboot cleanup code
804 * @index: index of this controller
805 *
806 * Performs cleanup of memory allocated in dwc3_uboot_init and other misc
807 * cleanups (equivalent to dwc3_remove in linux). index of _this_ controller
808 * should be passed and should match with the index passed in
809 * dwc3_device during init.
810 *
811 * Generally called from board file.
812 */
dwc3_uboot_exit(int index)813 void dwc3_uboot_exit(int index)
814 {
815 struct dwc3 *dwc;
816
817 list_for_each_entry(dwc, &dwc3_list, list) {
818 if (dwc->index != index)
819 continue;
820
821 dwc3_core_exit_mode(dwc);
822 dwc3_event_buffers_cleanup(dwc);
823 dwc3_free_event_buffers(dwc);
824 dwc3_core_exit(dwc);
825 list_del(&dwc->list);
826 kfree(dwc->mem);
827 break;
828 }
829 }
830
831 /**
832 * dwc3_uboot_handle_interrupt - handle dwc3 core interrupt
833 * @index: index of this controller
834 *
835 * Invokes dwc3 gadget interrupts.
836 *
837 * Generally called from board file.
838 */
dwc3_uboot_handle_interrupt(int index)839 void dwc3_uboot_handle_interrupt(int index)
840 {
841 struct dwc3 *dwc = NULL;
842
843 list_for_each_entry(dwc, &dwc3_list, list) {
844 if (dwc->index != index)
845 continue;
846
847 dwc3_gadget_uboot_handle_interrupt(dwc);
848 break;
849 }
850 }
851
852 MODULE_ALIAS("platform:dwc3");
853 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
854 MODULE_LICENSE("GPL v2");
855 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");
856
857 #if CONFIG_IS_ENABLED(PHY) && CONFIG_IS_ENABLED(DM_USB)
dwc3_setup_phy(struct udevice * dev,struct phy_bulk * phys)858 int dwc3_setup_phy(struct udevice *dev, struct phy_bulk *phys)
859 {
860 int ret;
861
862 ret = generic_phy_get_bulk(dev, phys);
863 if (ret)
864 return ret;
865
866 ret = generic_phy_init_bulk(phys);
867 if (ret)
868 return ret;
869
870 ret = generic_phy_power_on_bulk(phys);
871 if (ret)
872 generic_phy_exit_bulk(phys);
873
874 return ret;
875 }
876
dwc3_shutdown_phy(struct udevice * dev,struct phy_bulk * phys)877 int dwc3_shutdown_phy(struct udevice *dev, struct phy_bulk *phys)
878 {
879 int ret;
880
881 ret = generic_phy_power_off_bulk(phys);
882 ret |= generic_phy_exit_bulk(phys);
883 return ret;
884 }
885 #endif
886
887 #if CONFIG_IS_ENABLED(DM_USB)
dwc3_of_parse(struct dwc3 * dwc)888 void dwc3_of_parse(struct dwc3 *dwc)
889 {
890 const u8 *tmp;
891 struct udevice *dev = dwc->dev;
892 u8 lpm_nyet_threshold;
893 u8 tx_de_emphasis;
894 u8 hird_threshold;
895
896 /* default to highest possible threshold */
897 lpm_nyet_threshold = 0xff;
898
899 /* default to -3.5dB de-emphasis */
900 tx_de_emphasis = 1;
901
902 /*
903 * default to assert utmi_sleep_n and use maximum allowed HIRD
904 * threshold value of 0b1100
905 */
906 hird_threshold = 12;
907
908 dwc->hsphy_mode = usb_get_phy_mode(dev_ofnode(dev));
909
910 dwc->has_lpm_erratum = dev_read_bool(dev,
911 "snps,has-lpm-erratum");
912 tmp = dev_read_u8_array_ptr(dev, "snps,lpm-nyet-threshold", 1);
913 if (tmp)
914 lpm_nyet_threshold = *tmp;
915
916 dwc->is_utmi_l1_suspend = dev_read_bool(dev,
917 "snps,is-utmi-l1-suspend");
918 tmp = dev_read_u8_array_ptr(dev, "snps,hird-threshold", 1);
919 if (tmp)
920 hird_threshold = *tmp;
921
922 dwc->disable_scramble_quirk = dev_read_bool(dev,
923 "snps,disable_scramble_quirk");
924 dwc->u2exit_lfps_quirk = dev_read_bool(dev,
925 "snps,u2exit_lfps_quirk");
926 dwc->u2ss_inp3_quirk = dev_read_bool(dev,
927 "snps,u2ss_inp3_quirk");
928 dwc->req_p1p2p3_quirk = dev_read_bool(dev,
929 "snps,req_p1p2p3_quirk");
930 dwc->del_p1p2p3_quirk = dev_read_bool(dev,
931 "snps,del_p1p2p3_quirk");
932 dwc->del_phy_power_chg_quirk = dev_read_bool(dev,
933 "snps,del_phy_power_chg_quirk");
934 dwc->lfps_filter_quirk = dev_read_bool(dev,
935 "snps,lfps_filter_quirk");
936 dwc->rx_detect_poll_quirk = dev_read_bool(dev,
937 "snps,rx_detect_poll_quirk");
938 dwc->dis_u3_susphy_quirk = dev_read_bool(dev,
939 "snps,dis_u3_susphy_quirk");
940 dwc->dis_u2_susphy_quirk = dev_read_bool(dev,
941 "snps,dis_u2_susphy_quirk");
942 dwc->dis_del_phy_power_chg_quirk = dev_read_bool(dev,
943 "snps,dis-del-phy-power-chg-quirk");
944 dwc->dis_tx_ipgap_linecheck_quirk = dev_read_bool(dev,
945 "snps,dis-tx-ipgap-linecheck-quirk");
946 dwc->dis_enblslpm_quirk = dev_read_bool(dev,
947 "snps,dis_enblslpm_quirk");
948 dwc->dis_u2_freeclk_exists_quirk = dev_read_bool(dev,
949 "snps,dis-u2-freeclk-exists-quirk");
950 dwc->tx_de_emphasis_quirk = dev_read_bool(dev,
951 "snps,tx_de_emphasis_quirk");
952 tmp = dev_read_u8_array_ptr(dev, "snps,tx_de_emphasis", 1);
953 if (tmp)
954 tx_de_emphasis = *tmp;
955
956 dwc->lpm_nyet_threshold = lpm_nyet_threshold;
957 dwc->tx_de_emphasis = tx_de_emphasis;
958
959 dwc->hird_threshold = hird_threshold
960 | (dwc->is_utmi_l1_suspend << 4);
961 }
962
dwc3_init(struct dwc3 * dwc)963 int dwc3_init(struct dwc3 *dwc)
964 {
965 int ret;
966 u32 reg;
967
968 dwc3_cache_hwparams(dwc);
969
970 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
971 if (ret) {
972 dev_err(dwc->dev, "failed to allocate event buffers\n");
973 return -ENOMEM;
974 }
975
976 ret = dwc3_core_init(dwc);
977 if (ret) {
978 dev_err(dwc->dev, "failed to initialize core\n");
979 goto core_fail;
980 }
981
982 ret = dwc3_event_buffers_setup(dwc);
983 if (ret) {
984 dev_err(dwc->dev, "failed to setup event buffers\n");
985 goto event_fail;
986 }
987
988 if (dwc->revision >= DWC3_REVISION_250A) {
989 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
990
991 /*
992 * Enable hardware control of sending remote wakeup
993 * in HS when the device is in the L1 state.
994 */
995 if (dwc->revision >= DWC3_REVISION_290A)
996 reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW;
997
998 if (dwc->dis_tx_ipgap_linecheck_quirk)
999 reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS;
1000
1001 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
1002 }
1003
1004 if (dwc->dr_mode == USB_DR_MODE_HOST ||
1005 dwc->dr_mode == USB_DR_MODE_OTG) {
1006 reg = dwc3_readl(dwc->regs, DWC3_GUCTL);
1007
1008 reg |= DWC3_GUCTL_HSTINAUTORETRY;
1009
1010 dwc3_writel(dwc->regs, DWC3_GUCTL, reg);
1011 }
1012
1013 ret = dwc3_core_init_mode(dwc);
1014 if (ret)
1015 goto mode_fail;
1016
1017 return 0;
1018
1019 mode_fail:
1020 dwc3_event_buffers_cleanup(dwc);
1021
1022 event_fail:
1023 dwc3_core_exit(dwc);
1024
1025 core_fail:
1026 dwc3_free_event_buffers(dwc);
1027
1028 return ret;
1029 }
1030
dwc3_remove(struct dwc3 * dwc)1031 void dwc3_remove(struct dwc3 *dwc)
1032 {
1033 dwc3_core_exit_mode(dwc);
1034 dwc3_event_buffers_cleanup(dwc);
1035 dwc3_free_event_buffers(dwc);
1036 dwc3_core_exit(dwc);
1037 kfree(dwc->mem);
1038 }
1039 #endif
1040