1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * (C) Copyright 2016 Rockchip Electronics Co., Ltd
4  */
5 
6 #ifndef __ASM_ARCH_CRU_RK3328_H_
7 #define __ASM_ARCH_CRU_RK3328_H_
8 
9 struct rk3328_clk_priv {
10 	struct rk3328_cru *cru;
11 	ulong rate;
12 };
13 
14 struct rk3328_cru {
15 	u32 apll_con[5];
16 	u32 reserved1[3];
17 	u32 dpll_con[5];
18 	u32 reserved2[3];
19 	u32 cpll_con[5];
20 	u32 reserved3[3];
21 	u32 gpll_con[5];
22 	u32 reserved4[3];
23 	u32 mode_con;
24 	u32 misc;
25 	u32 reserved5[2];
26 	u32 glb_cnt_th;
27 	u32 glb_rst_st;
28 	u32 glb_srst_snd_value;
29 	u32 glb_srst_fst_value;
30 	u32 npll_con[5];
31 	u32 reserved6[(0x100 - 0xb4) / 4];
32 	u32 clksel_con[53];
33 	u32 reserved7[(0x200 - 0x1d4) / 4];
34 	u32 clkgate_con[29];
35 	u32 reserved8[3];
36 	u32 ssgtbl[32];
37 	u32 softrst_con[12];
38 	u32 reserved9[(0x380 - 0x330) / 4];
39 	u32 sdmmc_con[2];
40 	u32 sdio_con[2];
41 	u32 emmc_con[2];
42 	u32 sdmmc_ext_con[2];
43 };
44 check_member(rk3328_cru, sdmmc_ext_con[1], 0x39c);
45 #define MHz		1000000
46 #define KHz		1000
47 #define OSC_HZ		(24 * MHz)
48 #define APLL_HZ		(600 * MHz)
49 #define GPLL_HZ		(576 * MHz)
50 #define CPLL_HZ		(594 * MHz)
51 
52 #define CLK_CORE_HZ	(600 * MHz)
53 #define ACLKM_CORE_HZ	(300 * MHz)
54 #define PCLK_DBG_HZ	(300 * MHz)
55 
56 #define PERIHP_ACLK_HZ	(144000 * KHz)
57 #define PERIHP_HCLK_HZ	(72000 * KHz)
58 #define PERIHP_PCLK_HZ	(72000 * KHz)
59 
60 #define PWM_CLOCK_HZ    (74 * MHz)
61 
62 enum apll_frequencies {
63 	APLL_816_MHZ,
64 	APLL_600_MHZ,
65 };
66 
67 void rk3328_configure_cpu(struct rk3328_cru *cru,
68 			  enum apll_frequencies apll_freq);
69 
70 #endif	/* __ASM_ARCH_CRU_RK3328_H_ */
71