1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2017 Rockchip Electronics Co., Ltd. 4 */ 5 #ifndef _ASM_ARCH_GRF_px30_H 6 #define _ASM_ARCH_GRF_px30_H 7 8 struct px30_grf { 9 unsigned int gpio1al_iomux; 10 unsigned int gpio1ah_iomux; 11 unsigned int gpio1bl_iomux; 12 unsigned int gpio1bh_iomux; 13 unsigned int gpio1cl_iomux; 14 unsigned int gpio1ch_iomux; 15 unsigned int gpio1dl_iomux; 16 unsigned int gpio1dh_iomux; 17 18 unsigned int gpio2al_iomux; 19 unsigned int gpio2ah_iomux; 20 unsigned int gpio2bl_iomux; 21 unsigned int gpio2bh_iomux; 22 unsigned int gpio2cl_iomux; 23 unsigned int gpio2ch_iomux; 24 unsigned int gpio2dl_iomux; 25 unsigned int gpio2dh_iomux; 26 27 unsigned int gpio3al_iomux; 28 unsigned int gpio3ah_iomux; 29 unsigned int gpio3bl_iomux; 30 unsigned int gpio3bh_iomux; 31 unsigned int gpio3cl_iomux; 32 unsigned int gpio3ch_iomux; 33 unsigned int gpio3dl_iomux; 34 unsigned int gpio3dh_iomux; 35 36 unsigned int gpio1a_p; 37 unsigned int gpio1b_p; 38 unsigned int gpio1c_p; 39 unsigned int gpio1d_p; 40 unsigned int gpio2a_p; 41 unsigned int gpio2b_p; 42 unsigned int gpio2c_p; 43 unsigned int gpio2d_p; 44 unsigned int gpio3a_p; 45 unsigned int gpio3b_p; 46 unsigned int gpio3c_p; 47 unsigned int gpio3d_p; 48 unsigned int gpio1a_sr; 49 unsigned int gpio1b_sr; 50 unsigned int gpio1c_sr; 51 unsigned int gpio1d_sr; 52 unsigned int gpio2a_sr; 53 unsigned int gpio2b_sr; 54 unsigned int gpio2c_sr; 55 unsigned int gpio2d_sr; 56 unsigned int gpio3a_sr; 57 unsigned int gpio3b_sr; 58 unsigned int gpio3c_sr; 59 unsigned int gpio3d_sr; 60 unsigned int gpio1a_smt; 61 unsigned int gpio1b_smt; 62 unsigned int gpio1c_smt; 63 unsigned int gpio1d_smt; 64 unsigned int gpio2a_smt; 65 unsigned int gpio2b_smt; 66 unsigned int gpio2c_smt; 67 unsigned int gpio2d_smt; 68 unsigned int gpio3a_smt; 69 unsigned int gpio3b_smt; 70 unsigned int gpio3c_smt; 71 unsigned int gpio3d_smt; 72 unsigned int gpio1a_e; 73 unsigned int gpio1b_e; 74 unsigned int gpio1c_e; 75 unsigned int gpio1d_e; 76 unsigned int gpio2a_e; 77 unsigned int gpio2b_e; 78 unsigned int gpio2c_e; 79 unsigned int gpio2d_e; 80 unsigned int gpio3a_e; 81 unsigned int gpio3b_e; 82 unsigned int gpio3c_e; 83 unsigned int gpio3d_e; 84 85 unsigned int reserved0[(0x180 - 0x11C) / 4 - 1]; 86 unsigned int io_vsel; 87 unsigned int iofunc_con0; 88 unsigned int reserved1[(0x400 - 0x184) / 4 - 1]; 89 unsigned int soc_con[6]; 90 unsigned int reserved2[(0x480 - 0x414) / 4 - 1]; 91 unsigned int soc_status0; 92 unsigned int reserved3[(0x500 - 0x480) / 4 - 1]; 93 unsigned int cpu_con[3]; 94 unsigned int reserved4[5]; 95 unsigned int cpu_status[2]; 96 unsigned int reserved5[2]; 97 unsigned int soc_noc_con[2]; 98 unsigned int reserved6[6]; 99 unsigned int ddr_bankhash[4]; 100 unsigned int reserved7[(0x700 - 0x55c) / 4 - 1]; 101 unsigned int host0_con[2]; 102 unsigned int reserved8[(0x880 - 0x704) / 4 - 1]; 103 unsigned int otg_con3; 104 unsigned int reserved9[3]; 105 unsigned int host0_status4; 106 unsigned int reserved10[(0x904 - 0x890) / 4 - 1]; 107 unsigned int mac_con1; 108 }; 109 110 check_member(px30_grf, mac_con1, 0x904); 111 112 struct px30_pmugrf { 113 unsigned int gpio0al_iomux; 114 unsigned int gpio0bl_iomux; 115 unsigned int gpio0cl_iomux; 116 unsigned int gpio0dl_iomux; 117 unsigned int gpio0a_p; 118 unsigned int gpio0b_p; 119 unsigned int gpio0c_p; 120 unsigned int gpio0d_p; 121 unsigned int gpio0a_e; 122 unsigned int gpio0b_e; 123 unsigned int gpio0c_e; 124 unsigned int gpio0d_e; 125 unsigned int gpio0l_sr; 126 unsigned int gpio0h_sr; 127 unsigned int gpio0l_smt; 128 unsigned int gpio0h_smt; 129 unsigned int reserved1[(0x100 - 0x3c) / 4 - 1]; 130 unsigned int soc_con[4]; 131 unsigned int reserved2[(0x180 - 0x10c) / 4 - 1]; 132 unsigned int pvtm_con[2]; 133 unsigned int reserved3[2]; 134 unsigned int pvtm_status[2]; 135 unsigned int reserved4[(0x200 - 0x194) / 4 - 1]; 136 unsigned int os_reg[12]; 137 unsigned int reset_function_status; 138 }; 139 140 check_member(px30_pmugrf, reset_function_status, 0x230); 141 142 #endif 143