1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * (C) Copyright 2017 Rockchip Electronics Co., Ltd
4  */
5 #ifndef _ASM_ARCH_GRF_RK3128_H
6 #define _ASM_ARCH_GRF_RK3128_H
7 
8 struct rk3128_grf {
9 	unsigned int reserved[0x2a];
10 	unsigned int gpio0a_iomux;
11 	unsigned int gpio0b_iomux;
12 	unsigned int gpio0c_iomux;
13 	unsigned int gpio0d_iomux;
14 	unsigned int gpio1a_iomux;
15 	unsigned int gpio1b_iomux;
16 	unsigned int gpio1c_iomux;
17 	unsigned int gpio1d_iomux;
18 	unsigned int gpio2a_iomux;
19 	unsigned int gpio2b_iomux;
20 	unsigned int gpio2c_iomux;
21 	unsigned int gpio2d_iomux;
22 	unsigned int gpio3a_iomux;
23 	unsigned int gpio3b_iomux;
24 	unsigned int gpio3c_iomux;
25 	unsigned int gpio3d_iomux;
26 	unsigned int gpio2c_iomux2;
27 	unsigned int grf_cif_iomux;
28 	unsigned int grf_cif_iomux1;
29 	unsigned int reserved1[(0x118 - 0xf0) / 4 - 1];
30 	unsigned int gpio0l_pull;
31 	unsigned int gpio0h_pull;
32 	unsigned int gpio1l_pull;
33 	unsigned int gpio1h_pull;
34 	unsigned int gpio2l_pull;
35 	unsigned int gpio2h_pull;
36 	unsigned int gpio3l_pull;
37 	unsigned int gpio3h_pull;
38 	unsigned int reserved2;
39 	unsigned int soc_con0;
40 	unsigned int soc_con1;
41 	unsigned int soc_con2;
42 	unsigned int soc_status0;
43 	unsigned int reserved3[6];
44 	unsigned int mac_con0;
45 	unsigned int mac_con1;
46 	unsigned int reserved4[4];
47 	unsigned int uoc0_con0;
48 	unsigned int reserved5;
49 	unsigned int uoc1_con1;
50 	unsigned int uoc1_con2;
51 	unsigned int uoc1_con3;
52 	unsigned int uoc1_con4;
53 	unsigned int uoc1_con5;
54 	unsigned int reserved6;
55 	unsigned int ddrc_stat;
56 	unsigned int reserved9;
57 	unsigned int soc_status1;
58 	unsigned int cpu_con0;
59 	unsigned int cpu_con1;
60 	unsigned int cpu_con2;
61 	unsigned int cpu_con3;
62 	unsigned int reserved10;
63 	unsigned int reserved11;
64 	unsigned int cpu_status0;
65 	unsigned int cpu_status1;
66 	unsigned int os_reg[8];
67 	unsigned int reserved12[(0x280 - 0x1e4) / 4 - 1];
68 	unsigned int usbphy0_con[8];
69 	unsigned int usbphy1_con[8];
70 	unsigned int uoc_status0;
71 	unsigned int reserved13[(0x300 - 0x2c0) / 4 - 1];
72 	unsigned int chip_tag;
73 	unsigned int sdmmc_det_cnt;
74 };
75 check_member(rk3128_grf, sdmmc_det_cnt, 0x304);
76 
77 struct rk3128_pmu {
78 	unsigned int wakeup_cfg;
79 	unsigned int pwrdn_con;
80 	unsigned int pwrdn_st;
81 	unsigned int idle_req;
82 	unsigned int idle_st;
83 	unsigned int pwrmode_con;
84 	unsigned int pwr_state;
85 	unsigned int osc_cnt;
86 	unsigned int core_pwrdwn_cnt;
87 	unsigned int core_pwrup_cnt;
88 	unsigned int sft_con;
89 	unsigned int ddr_sref_st;
90 	unsigned int int_con;
91 	unsigned int int_st;
92 	unsigned int sys_reg[4];
93 };
94 check_member(rk3128_pmu, int_st, 0x34);
95 
96 /* GRF_GPIO0A_IOMUX */
97 enum {
98 	GPIO0A7_SHIFT		= 14,
99 	GPIO0A7_MASK		= 3 << GPIO0A7_SHIFT,
100 	GPIO0A7_GPIO		= 0,
101 	GPIO0A7_I2C3_SDA,
102 
103 	GPIO0A6_SHIFT		= 12,
104 	GPIO0A6_MASK		= 3 << GPIO0A6_SHIFT,
105 	GPIO0A6_GPIO		= 0,
106 	GPIO0A6_I2C3_SCL,
107 
108 	GPIO0A3_SHIFT		= 6,
109 	GPIO0A3_MASK		= 3 << GPIO0A3_SHIFT,
110 	GPIO0A3_GPIO		= 0,
111 	GPIO0A3_I2C1_SDA,
112 
113 	GPIO0A2_SHIFT		= 4,
114 	GPIO0A2_MASK		= 1 << GPIO0A2_SHIFT,
115 	GPIO0A2_GPIO		= 0,
116 	GPIO0A2_I2C1_SCL,
117 
118 	GPIO0A1_SHIFT		= 2,
119 	GPIO0A1_MASK		= 1 << GPIO0A1_SHIFT,
120 	GPIO0A1_GPIO		= 0,
121 	GPIO0A1_I2C0_SDA,
122 
123 	GPIO0A0_SHIFT		= 0,
124 	GPIO0A0_MASK		= 1 << GPIO0A0_SHIFT,
125 	GPIO0A0_GPIO		= 0,
126 	GPIO0A0_I2C0_SCL,
127 };
128 
129 /* GRF_GPIO0B_IOMUX */
130 enum {
131 	GPIO0B6_SHIFT		= 12,
132 	GPIO0B6_MASK		= 3 << GPIO0B6_SHIFT,
133 	GPIO0B6_GPIO		= 0,
134 	GPIO0B6_I2S_SDI,
135 	GPIO0B6_SPI_CSN0,
136 
137 	GPIO0B5_SHIFT		= 10,
138 	GPIO0B5_MASK		= 3 << GPIO0B5_SHIFT,
139 	GPIO0B5_GPIO		= 0,
140 	GPIO0B5_I2S_SDO,
141 	GPIO0B5_SPI_RXD,
142 
143 	GPIO0B4_SHIFT		= 8,
144 	GPIO0B4_MASK		= 1 << GPIO0B4_SHIFT,
145 	GPIO0B4_GPIO		= 0,
146 	GPIO0B4_I2S_LRCKTX,
147 
148 	GPIO0B3_SHIFT		= 6,
149 	GPIO0B3_MASK		= 3 << GPIO0B3_SHIFT,
150 	GPIO0B3_GPIO		= 0,
151 	GPIO0B3_I2S_LRCKRX,
152 	GPIO0B3_SPI_TXD,
153 
154 	GPIO0B1_SHIFT		= 2,
155 	GPIO0B1_MASK		= 3,
156 	GPIO0B1_GPIO		= 0,
157 	GPIO0B1_I2S_SCLK,
158 	GPIO0B1_SPI_CLK,
159 
160 	GPIO0B0_SHIFT		= 0,
161 	GPIO0B0_MASK		= 3,
162 	GPIO0B0_GPIO		= 0,
163 	GPIO0B0_I2S1_MCLK,
164 };
165 
166 /* GRF_GPIO0D_IOMUX */
167 enum {
168 	GPIO0D4_SHIFT		= 8,
169 	GPIO0D4_MASK		= 1 << GPIO0D4_SHIFT,
170 	GPIO0D4_GPIO		= 0,
171 	GPIO0D4_PWM2,
172 
173 	GPIO0D3_SHIFT		= 6,
174 	GPIO0D3_MASK		= 1 << GPIO0D3_SHIFT,
175 	GPIO0D3_GPIO		= 0,
176 	GPIO0D3_PWM1,
177 
178 	GPIO0D2_SHIFT		= 4,
179 	GPIO0D2_MASK		= 1 << GPIO0D2_SHIFT,
180 	GPIO0D2_GPIO		= 0,
181 	GPIO0D2_PWM0,
182 
183 	GPIO0D1_SHIFT		= 2,
184 	GPIO0D1_MASK		= 1 << GPIO0D1_SHIFT,
185 	GPIO0D1_GPIO		= 0,
186 	GPIO0D1_UART2_CTSN,
187 
188 	GPIO0D0_SHIFT		= 0,
189 	GPIO0D0_MASK		= 3 << GPIO0D0_SHIFT,
190 	GPIO0D0_GPIO		= 0,
191 	GPIO0D0_UART2_RTSN,
192 	GPIO0D0_PMIC_SLEEP,
193 };
194 
195 /* GRF_GPIO1A_IOMUX */
196 enum {
197 	GPIO1A5_SHIFT		= 10,
198 	GPIO1A5_MASK		= 3 << GPIO1A5_SHIFT,
199 	GPIO1A5_GPIO		= 0,
200 	GPIO1A5_I2S_SDI,
201 	GPIO1A5_SDMMC_DATA3,
202 
203 	GPIO1A4_SHIFT		= 8,
204 	GPIO1A4_MASK		= 3 << GPIO1A4_SHIFT,
205 	GPIO1A4_GPIO		= 0,
206 	GPIO1A4_I2S_SD0,
207 	GPIO1A4_SDMMC_DATA2,
208 
209 	GPIO1A3_SHIFT		= 6,
210 	GPIO1A3_MASK		= 1 << GPIO1A3_SHIFT,
211 	GPIO1A3_GPIO		= 0,
212 	GPIO1A3_I2S_LRCKTX,
213 
214 	GPIO1A2_SHIFT		= 4,
215 	GPIO1A2_MASK		= 3 << GPIO1A2_SHIFT,
216 	GPIO1A2_GPIO		= 0,
217 	GPIO1A2_I2S_LRCKRX,
218 	GPIO1A2_SDMMC_DATA1,
219 
220 	GPIO1A1_SHIFT		= 2,
221 	GPIO1A1_MASK		= 3 << GPIO1A1_SHIFT,
222 	GPIO1A1_GPIO		= 0,
223 	GPIO1A1_I2S_SCLK,
224 	GPIO1A1_SDMMC_DATA0,
225 	GPIO1A1_PMIC_SLEEP,
226 
227 	GPIO1A0_SHIFT		= 0,
228 	GPIO1A0_MASK		= 3,
229 	GPIO1A0_GPIO		= 0,
230 	GPIO1A0_I2S_MCLK,
231 	GPIO1A0_SDMMC_CLKOUT,
232 	GPIO1A0_XIN32K,
233 
234 };
235 
236 /* GRF_GPIO1B_IOMUX */
237 enum {
238 	GPIO1B7_SHIFT		= 14,
239 	GPIO1B7_MASK		= 1 << GPIO1B7_SHIFT,
240 	GPIO1B7_GPIO		= 0,
241 	GPIO1B7_MMC0_CMD,
242 
243 	GPIO1B6_SHIFT		= 12,
244 	GPIO1B6_MASK		= 1 << GPIO1B6_SHIFT,
245 	GPIO1B6_GPIO		= 0,
246 	GPIO1B6_MMC_PWREN,
247 
248 	GPIO1B2_SHIFT		= 4,
249 	GPIO1B2_MASK		= 3 << GPIO1B2_SHIFT,
250 	GPIO1B2_GPIO		= 0,
251 	GPIO1B2_SPI_RXD,
252 	GPIO1B2_UART1_SIN,
253 
254 	GPIO1B1_SHIFT		= 2,
255 	GPIO1B1_MASK		= 3 << GPIO1B1_SHIFT,
256 	GPIO1B1_GPIO		= 0,
257 	GPIO1B1_SPI_TXD,
258 	GPIO1B1_UART1_SOUT,
259 
260 	GPIO1B0_SHIFT		= 0,
261 	GPIO1B0_MASK		= 3 << GPIO1B0_SHIFT,
262 	GPIO1B0_GPIO		= 0,
263 	GPIO1B0_SPI_CLK,
264 	GPIO1B0_UART1_CTSN
265 };
266 
267 /* GRF_GPIO1C_IOMUX */
268 enum {
269 	GPIO1C6_SHIFT		= 12,
270 	GPIO1C6_MASK		= 3 << GPIO1C6_SHIFT,
271 	GPIO1C6_GPIO		= 0,
272 	GPIO1C6_NAND_CS2,
273 	GPIO1C6_EMMC_CMD,
274 
275 	GPIO1C5_SHIFT		= 10,
276 	GPIO1C5_MASK		= 3 << GPIO1C5_SHIFT,
277 	GPIO1C5_GPIO		= 0,
278 	GPIO1C5_MMC0_D3,
279 	GPIO1C5_JTAG_TMS,
280 
281 	GPIO1C4_SHIFT		= 8,
282 	GPIO1C4_MASK		= 3 << GPIO1C4_SHIFT,
283 	GPIO1C4_GPIO		= 0,
284 	GPIO1C4_MMC0_D2,
285 	GPIO1C4_JTAG_TCK,
286 
287 	GPIO1C3_SHIFT		= 6,
288 	GPIO1C3_MASK		= 3 << GPIO1C3_SHIFT,
289 	GPIO1C3_GPIO		= 0,
290 	GPIO1C3_MMC0_D1,
291 	GPIO1C3_UART2_RX,
292 
293 	GPIO1C2_SHIFT		= 4,
294 	GPIO1C2_MASK		= 3 << GPIO1C2_SHIFT,
295 	GPIO1C2_GPIO		= 0,
296 	GPIO1C2_MMC0_D0,
297 	GPIO1C2_UART2_TX,
298 
299 	GPIO1C1_SHIFT		= 2,
300 	GPIO1C1_MASK		= 1 << GPIO1C1_SHIFT,
301 	GPIO1C1_GPIO		= 0,
302 	GPIO1C1_MMC0_DETN,
303 
304 	GPIO1C0_SHIFT		= 0,
305 	GPIO1C0_MASK		= 1 << GPIO1C0_SHIFT,
306 	GPIO1C0_GPIO		= 0,
307 	GPIO1C0_MMC0_CLKOUT,
308 };
309 
310 /* GRF_GPIO1D_IOMUX */
311 enum {
312 	GPIO1D7_SHIFT		= 14,
313 	GPIO1D7_MASK		= 3 << GPIO1D7_SHIFT,
314 	GPIO1D7_GPIO		= 0,
315 	GPIO1D7_NAND_D7,
316 	GPIO1D7_EMMC_D7,
317 	GPIO1D7_SPI_CSN1,
318 
319 	GPIO1D6_SHIFT		= 12,
320 	GPIO1D6_MASK		= 3 << GPIO1D6_SHIFT,
321 	GPIO1D6_GPIO		= 0,
322 	GPIO1D6_NAND_D6,
323 	GPIO1D6_EMMC_D6,
324 	GPIO1D6_SPI_CSN0,
325 
326 	GPIO1D5_SHIFT		= 10,
327 	GPIO1D5_MASK		= 3 << GPIO1D5_SHIFT,
328 	GPIO1D5_GPIO		= 0,
329 	GPIO1D5_NAND_D5,
330 	GPIO1D5_EMMC_D5,
331 	GPIO1D5_SPI_TXD1,
332 
333 	GPIO1D4_SHIFT		= 8,
334 	GPIO1D4_MASK		= 3 << GPIO1D4_SHIFT,
335 	GPIO1D4_GPIO		= 0,
336 	GPIO1D4_NAND_D4,
337 	GPIO1D4_EMMC_D4,
338 	GPIO1D4_SPI_RXD1,
339 
340 	GPIO1D3_SHIFT		= 6,
341 	GPIO1D3_MASK		= 3 << GPIO1D3_SHIFT,
342 	GPIO1D3_GPIO		= 0,
343 	GPIO1D3_NAND_D3,
344 	GPIO1D3_EMMC_D3,
345 	GPIO1D3_SFC_SIO3,
346 
347 	GPIO1D2_SHIFT		= 4,
348 	GPIO1D2_MASK		= 3 << GPIO1D2_SHIFT,
349 	GPIO1D2_GPIO		= 0,
350 	GPIO1D2_NAND_D2,
351 	GPIO1D2_EMMC_D2,
352 	GPIO1D2_SFC_SIO2,
353 
354 	GPIO1D1_SHIFT		= 2,
355 	GPIO1D1_MASK		= 3 << GPIO1D1_SHIFT,
356 	GPIO1D1_GPIO		= 0,
357 	GPIO1D1_NAND_D1,
358 	GPIO1D1_EMMC_D1,
359 	GPIO1D1_SFC_SIO1,
360 
361 	GPIO1D0_SHIFT		= 0,
362 	GPIO1D0_MASK		= 3 << GPIO1D0_SHIFT,
363 	GPIO1D0_GPIO		= 0,
364 	GPIO1D0_NAND_D0,
365 	GPIO1D0_EMMC_D0,
366 	GPIO1D0_SFC_SIO0,
367 };
368 
369 /* GRF_GPIO2A_IOMUX */
370 enum {
371 	GPIO2A7_SHIFT		= 14,
372 	GPIO2A7_MASK		= 3 << GPIO2A7_SHIFT,
373 	GPIO2A7_GPIO		= 0,
374 	GPIO2A7_NAND_DQS,
375 	GPIO2A7_EMMC_CLKOUT,
376 
377 	GPIO2A6_SHIFT		= 12,
378 	GPIO2A6_MASK		= 1 << GPIO2A6_SHIFT,
379 	GPIO2A6_GPIO		= 0,
380 	GPIO2A6_NAND_CS0,
381 
382 	GPIO2A5_SHIFT		= 10,
383 	GPIO2A5_MASK		= 3 << GPIO2A5_SHIFT,
384 	GPIO2A5_GPIO		= 0,
385 	GPIO2A5_NAND_WP,
386 	GPIO2A5_EMMC_PWREN,
387 
388 	GPIO2A4_SHIFT		= 8,
389 	GPIO2A4_MASK		= 3 << GPIO2A4_SHIFT,
390 	GPIO2A4_GPIO		= 0,
391 	GPIO2A4_NAND_RDY,
392 	GPIO2A4_EMMC_CMD,
393 	GPIO2A3_SFC_CLK,
394 
395 	GPIO2A3_SHIFT		= 6,
396 	GPIO2A3_MASK		= 3 << GPIO2A3_SHIFT,
397 	GPIO2A3_GPIO		= 0,
398 	GPIO2A3_NAND_RDN,
399 	GPIO2A4_SFC_CSN1,
400 
401 	GPIO2A2_SHIFT		= 4,
402 	GPIO2A2_MASK		= 3 << GPIO2A2_SHIFT,
403 	GPIO2A2_GPIO		= 0,
404 	GPIO2A2_NAND_WRN,
405 	GPIO2A4_SFC_CSN0,
406 
407 	GPIO2A1_SHIFT		= 2,
408 	GPIO2A1_MASK		= 3 << GPIO2A1_SHIFT,
409 	GPIO2A1_GPIO		= 0,
410 	GPIO2A1_NAND_CLE,
411 	GPIO2A1_EMMC_CLKOUT,
412 
413 	GPIO2A0_SHIFT		= 0,
414 	GPIO2A0_MASK		= 3 << GPIO2A0_SHIFT,
415 	GPIO2A0_GPIO		= 0,
416 	GPIO2A0_NAND_ALE,
417 	GPIO2A0_SPI_CLK,
418 };
419 
420 /* GRF_GPIO2B_IOMUX */
421 enum {
422 	GPIO2B7_SHIFT		= 14,
423 	GPIO2B7_MASK		= 3 << GPIO2B7_SHIFT,
424 	GPIO2B7_GPIO		= 0,
425 	GPIO2B7_LCDC0_D13,
426 	GPIO2B7_EBC_SDCE5,
427 	GPIO2B7_GMAC_RXER,
428 
429 	GPIO2B6_SHIFT		= 12,
430 	GPIO2B6_MASK		= 3 << GPIO2B6_SHIFT,
431 	GPIO2B6_GPIO		= 0,
432 	GPIO2B6_LCDC0_D12,
433 	GPIO2B6_EBC_SDCE4,
434 	GPIO2B6_GMAC_CLK,
435 
436 	GPIO2B5_SHIFT		= 10,
437 	GPIO2B5_MASK		= 3 << GPIO2B5_SHIFT,
438 	GPIO2B5_GPIO		= 0,
439 	GPIO2B5_LCDC0_D11,
440 	GPIO2B5_EBC_SDCE3,
441 	GPIO2B5_GMAC_TXEN,
442 
443 	GPIO2B4_SHIFT		= 8,
444 	GPIO2B4_MASK		= 3 << GPIO2B4_SHIFT,
445 	GPIO2B4_GPIO		= 0,
446 	GPIO2B4_LCDC0_D10,
447 	GPIO2B4_EBC_SDCE2,
448 	GPIO2B4_GMAC_MDIO,
449 
450 	GPIO2B3_SHIFT		= 6,
451 	GPIO2B3_MASK		= 3 << GPIO2B3_SHIFT,
452 	GPIO2B3_GPIO		= 0,
453 	GPIO2B3_LCDC0_DEN,
454 	GPIO2B3_EBC_GDCLK,
455 	GPIO2B3_GMAC_RXCLK,
456 
457 	GPIO2B2_SHIFT		= 4,
458 	GPIO2B2_MASK		= 3 << GPIO2B2_SHIFT,
459 	GPIO2B2_GPIO		= 0,
460 	GPIO2B2_LCDC0_VSYNC,
461 	GPIO2B2_EBC_SDOE,
462 	GPIO2B2_GMAC_CRS,
463 
464 	GPIO2B1_SHIFT		= 2,
465 	GPIO2B1_MASK		= 3 << GPIO2B1_SHIFT,
466 	GPIO2B1_GPIO		= 0,
467 	GPIO2B1_LCDC0_HSYNC,
468 	GPIO2B1_EBC_SDLE,
469 	GPIO2B1_GMAC_TXCLK,
470 
471 	GPIO2B0_SHIFT		= 0,
472 	GPIO2B0_MASK		= 3 << GPIO2B0_SHIFT,
473 	GPIO2B0_GPIO		= 0,
474 	GPIO2B0_LCDC0_DCLK,
475 	GPIO2B0_EBC_SDCLK,
476 	GPIO2B0_GMAC_RXDV,
477 };
478 
479 /* GRF_GPIO2C_IOMUX */
480 enum {
481 	GPIO2C3_SHIFT		= 6,
482 	GPIO2C3_MASK		= 3 << GPIO2C3_SHIFT,
483 	GPIO2C3_GPIO		= 0,
484 	GPIO2C3_LCDC0_D17,
485 	GPIO2C3_EBC_GDPWR0,
486 	GPIO2C3_GMAC_TXD0,
487 
488 	GPIO2C2_SHIFT		= 4,
489 	GPIO2C2_MASK		= 3 << GPIO2C2_SHIFT,
490 	GPIO2C2_GPIO		= 0,
491 	GPIO2C2_LCDC0_D16,
492 	GPIO2C2_EBC_GDSP,
493 	GPIO2C2_GMAC_TXD1,
494 
495 	GPIO2C1_SHIFT		= 2,
496 	GPIO2C1_MASK		= 3 << GPIO2C1_SHIFT,
497 	GPIO2C1_GPIO		= 0,
498 	GPIO2C1_LCDC0_D15,
499 	GPIO2C1_EBC_GDOE,
500 	GPIO2C1_GMAC_RXD0,
501 
502 	GPIO2C0_SHIFT		= 0,
503 	GPIO2C0_MASK		= 3 << GPIO2C0_SHIFT,
504 	GPIO2C0_GPIO		= 0,
505 	GPIO2C0_LCDC0_D14,
506 	GPIO2C0_EBC_VCOM,
507 	GPIO2C0_GMAC_RXD1,
508 };
509 
510 /* GRF_GPIO2D_IOMUX */
511 enum {
512 	GPIO2D6_SHIFT		= 12,
513 	GPIO2D6_MASK		= 3 << GPIO2D6_SHIFT,
514 	GPIO2D6_GPIO		= 0,
515 	GPIO2D6_LCDC0_D22,
516 	GPIO2D6_GMAC_COL	= 4,
517 
518 	GPIO2D1_SHIFT		= 2,
519 	GPIO2D1_MASK		= 3 << GPIO2D1_SHIFT,
520 	GPIO2D1_GPIO		= 0,
521 	GPIO2D1_GMAC_MDC	= 3,
522 };
523 
524 /* GRF_GPIO2C_IOMUX2 */
525 enum {
526 	GPIO2C7_SHIFT		= 12,
527 	GPIO2C7_MASK		= 7 << GPIO2C7_SHIFT,
528 	GPIO2C7_GPIO		= 0,
529 	GPIO2C7_GMAC_TXD3	= 4,
530 
531 	GPIO2C6_SHIFT		= 12,
532 	GPIO2C6_MASK		= 7 << GPIO2C6_SHIFT,
533 	GPIO2C6_GPIO		= 0,
534 	GPIO2C6_GMAC_TXD2	= 4,
535 
536 	GPIO2C5_SHIFT		= 4,
537 	GPIO2C5_MASK		= 7 << GPIO2C5_SHIFT,
538 	GPIO2C5_GPIO		= 0,
539 	GPIO2C5_I2C2_SCL	= 3,
540 	GPIO2C5_GMAC_RXD2,
541 
542 	GPIO2C4_SHIFT		= 0,
543 	GPIO2C4_MASK		= 7 << GPIO2C4_SHIFT,
544 	GPIO2C4_GPIO		= 0,
545 	GPIO2C4_I2C2_SDA	= 3,
546 	GPIO2C4_GMAC_RXD2,
547 };
548 #endif
549