1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * Copyright (c) 2015 Google, Inc
4  *
5  * Copyright 2014 Rockchip Inc.
6  */
7 
8 #ifndef _ASM_ARCH_RK3288_SDRAM_H__
9 #define _ASM_ARCH_RK3288_SDRAM_H__
10 
11 struct rk3288_sdram_channel {
12 	/*
13 	 * bit width in address, eg:
14 	 * 8 banks using 3 bit to address,
15 	 * 2 cs using 1 bit to address.
16 	 */
17 	u8 rank;
18 	u8 col;
19 	u8 bk;
20 	u8 bw;
21 	u8 dbw;
22 	u8 row_3_4;
23 	u8 cs0_row;
24 	u8 cs1_row;
25 #if CONFIG_IS_ENABLED(OF_PLATDATA)
26 	/*
27 	 * For of-platdata, which would otherwise convert this into two
28 	 * byte-swapped integers. With a size of 9 bytes, this struct will
29 	 * appear in of-platdata as a byte array.
30 	 *
31 	 * If OF_PLATDATA enabled, need to add a dummy byte in dts.(i.e 0xff)
32 	 */
33 	u8 dummy;
34 #endif
35 };
36 
37 struct rk3288_sdram_pctl_timing {
38 	u32 togcnt1u;
39 	u32 tinit;
40 	u32 trsth;
41 	u32 togcnt100n;
42 	u32 trefi;
43 	u32 tmrd;
44 	u32 trfc;
45 	u32 trp;
46 	u32 trtw;
47 	u32 tal;
48 	u32 tcl;
49 	u32 tcwl;
50 	u32 tras;
51 	u32 trc;
52 	u32 trcd;
53 	u32 trrd;
54 	u32 trtp;
55 	u32 twr;
56 	u32 twtr;
57 	u32 texsr;
58 	u32 txp;
59 	u32 txpdll;
60 	u32 tzqcs;
61 	u32 tzqcsi;
62 	u32 tdqs;
63 	u32 tcksre;
64 	u32 tcksrx;
65 	u32 tcke;
66 	u32 tmod;
67 	u32 trstl;
68 	u32 tzqcl;
69 	u32 tmrr;
70 	u32 tckesr;
71 	u32 tdpd;
72 };
73 check_member(rk3288_sdram_pctl_timing, tdpd, 0x144 - 0xc0);
74 
75 struct rk3288_sdram_phy_timing {
76 	u32 dtpr0;
77 	u32 dtpr1;
78 	u32 dtpr2;
79 	u32 mr[4];
80 };
81 
82 struct rk3288_base_params {
83 	u32 noc_timing;
84 	u32 noc_activate;
85 	u32 ddrconfig;
86 	u32 ddr_freq;
87 	u32 dramtype;
88 	/*
89 	 * DDR Stride is address mapping for DRAM space
90 	 * Stride	Ch 0 range	Ch1 range	Total
91 	 * 0x00		0-256MB		256MB-512MB	512MB
92 	 * 0x05		0-1GB		0-1GB		1GB
93 	 * 0x09		0-2GB		0-2GB		2GB
94 	 * 0x0d		0-4GB		0-4GB		4GB
95 	 * 0x17		N/A		0-4GB		4GB
96 	 * 0x1a		0-4GB		4GB-8GB		8GB
97 	 */
98 	u32 stride;
99 	u32 odt;
100 };
101 
102 #endif
103