1 #ifndef __ASM_ARM_SYSTEM_H
2 #define __ASM_ARM_SYSTEM_H
3
4 #include <linux/compiler.h>
5 #include <asm/barriers.h>
6
7 #ifdef CONFIG_ARM64
8
9 /*
10 * SCTLR_EL1/SCTLR_EL2/SCTLR_EL3 bits definitions
11 */
12 #define CR_M (1 << 0) /* MMU enable */
13 #define CR_A (1 << 1) /* Alignment abort enable */
14 #define CR_C (1 << 2) /* Dcache enable */
15 #define CR_SA (1 << 3) /* Stack Alignment Check Enable */
16 #define CR_I (1 << 12) /* Icache enable */
17 #define CR_WXN (1 << 19) /* Write Permision Imply XN */
18 #define CR_EE (1 << 25) /* Exception (Big) Endian */
19
20 #define ES_TO_AARCH64 1
21 #define ES_TO_AARCH32 0
22
23 /*
24 * SCR_EL3 bits definitions
25 */
26 #define SCR_EL3_RW_AARCH64 (1 << 10) /* Next lower level is AArch64 */
27 #define SCR_EL3_RW_AARCH32 (0 << 10) /* Lower lowers level are AArch32 */
28 #define SCR_EL3_HCE_EN (1 << 8) /* Hypervisor Call enable */
29 #define SCR_EL3_SMD_DIS (1 << 7) /* Secure Monitor Call disable */
30 #define SCR_EL3_RES1 (3 << 4) /* Reserved, RES1 */
31 #define SCR_EL3_EA_EN (1 << 3) /* External aborts taken to EL3 */
32 #define SCR_EL3_NS_EN (1 << 0) /* EL0 and EL1 in Non-scure state */
33
34 /*
35 * SPSR_EL3/SPSR_EL2 bits definitions
36 */
37 #define SPSR_EL_END_LE (0 << 9) /* Exception Little-endian */
38 #define SPSR_EL_DEBUG_MASK (1 << 9) /* Debug exception masked */
39 #define SPSR_EL_ASYN_MASK (1 << 8) /* Asynchronous data abort masked */
40 #define SPSR_EL_SERR_MASK (1 << 8) /* System Error exception masked */
41 #define SPSR_EL_IRQ_MASK (1 << 7) /* IRQ exception masked */
42 #define SPSR_EL_FIQ_MASK (1 << 6) /* FIQ exception masked */
43 #define SPSR_EL_T_A32 (0 << 5) /* AArch32 instruction set A32 */
44 #define SPSR_EL_M_AARCH64 (0 << 4) /* Exception taken from AArch64 */
45 #define SPSR_EL_M_AARCH32 (1 << 4) /* Exception taken from AArch32 */
46 #define SPSR_EL_M_SVC (0x3) /* Exception taken from SVC mode */
47 #define SPSR_EL_M_HYP (0xa) /* Exception taken from HYP mode */
48 #define SPSR_EL_M_EL1H (5) /* Exception taken from EL1h mode */
49 #define SPSR_EL_M_EL2H (9) /* Exception taken from EL2h mode */
50
51 /*
52 * CPTR_EL2 bits definitions
53 */
54 #define CPTR_EL2_RES1 (3 << 12 | 0x3ff) /* Reserved, RES1 */
55
56 /*
57 * SCTLR_EL2 bits definitions
58 */
59 #define SCTLR_EL2_RES1 (3 << 28 | 3 << 22 | 1 << 18 | 1 << 16 |\
60 1 << 11 | 3 << 4) /* Reserved, RES1 */
61 #define SCTLR_EL2_EE_LE (0 << 25) /* Exception Little-endian */
62 #define SCTLR_EL2_WXN_DIS (0 << 19) /* Write permission is not XN */
63 #define SCTLR_EL2_ICACHE_DIS (0 << 12) /* Instruction cache disabled */
64 #define SCTLR_EL2_SA_DIS (0 << 3) /* Stack Alignment Check disabled */
65 #define SCTLR_EL2_DCACHE_DIS (0 << 2) /* Data cache disabled */
66 #define SCTLR_EL2_ALIGN_DIS (0 << 1) /* Alignment check disabled */
67 #define SCTLR_EL2_MMU_DIS (0) /* MMU disabled */
68
69 /*
70 * CNTHCTL_EL2 bits definitions
71 */
72 #define CNTHCTL_EL2_EL1PCEN_EN (1 << 1) /* Physical timer regs accessible */
73 #define CNTHCTL_EL2_EL1PCTEN_EN (1 << 0) /* Physical counter accessible */
74
75 /*
76 * HCR_EL2 bits definitions
77 */
78 #define HCR_EL2_RW_AARCH64 (1 << 31) /* EL1 is AArch64 */
79 #define HCR_EL2_RW_AARCH32 (0 << 31) /* Lower levels are AArch32 */
80 #define HCR_EL2_HCD_DIS (1 << 29) /* Hypervisor Call disabled */
81
82 /*
83 * CPACR_EL1 bits definitions
84 */
85 #define CPACR_EL1_FPEN_EN (3 << 20) /* SIMD and FP instruction enabled */
86
87 /*
88 * SCTLR_EL1 bits definitions
89 */
90 #define SCTLR_EL1_RES1 (3 << 28 | 3 << 22 | 1 << 20 |\
91 1 << 11) /* Reserved, RES1 */
92 #define SCTLR_EL1_UCI_DIS (0 << 26) /* Cache instruction disabled */
93 #define SCTLR_EL1_EE_LE (0 << 25) /* Exception Little-endian */
94 #define SCTLR_EL1_WXN_DIS (0 << 19) /* Write permission is not XN */
95 #define SCTLR_EL1_NTWE_DIS (0 << 18) /* WFE instruction disabled */
96 #define SCTLR_EL1_NTWI_DIS (0 << 16) /* WFI instruction disabled */
97 #define SCTLR_EL1_UCT_DIS (0 << 15) /* CTR_EL0 access disabled */
98 #define SCTLR_EL1_DZE_DIS (0 << 14) /* DC ZVA instruction disabled */
99 #define SCTLR_EL1_ICACHE_DIS (0 << 12) /* Instruction cache disabled */
100 #define SCTLR_EL1_UMA_DIS (0 << 9) /* User Mask Access disabled */
101 #define SCTLR_EL1_SED_EN (0 << 8) /* SETEND instruction enabled */
102 #define SCTLR_EL1_ITD_EN (0 << 7) /* IT instruction enabled */
103 #define SCTLR_EL1_CP15BEN_DIS (0 << 5) /* CP15 barrier operation disabled */
104 #define SCTLR_EL1_SA0_DIS (0 << 4) /* Stack Alignment EL0 disabled */
105 #define SCTLR_EL1_SA_DIS (0 << 3) /* Stack Alignment EL1 disabled */
106 #define SCTLR_EL1_DCACHE_DIS (0 << 2) /* Data cache disabled */
107 #define SCTLR_EL1_ALIGN_DIS (0 << 1) /* Alignment check disabled */
108 #define SCTLR_EL1_MMU_DIS (0) /* MMU disabled */
109
110 #ifndef __ASSEMBLY__
111
112 struct pt_regs;
113
114 u64 get_page_table_size(void);
115 #define PGTABLE_SIZE get_page_table_size()
116
117 /* 2MB granularity */
118 #define MMU_SECTION_SHIFT 21
119 #define MMU_SECTION_SIZE (1 << MMU_SECTION_SHIFT)
120
121 /* These constants need to be synced to the MT_ types in asm/armv8/mmu.h */
122 enum dcache_option {
123 DCACHE_OFF = 0 << 2,
124 DCACHE_WRITETHROUGH = 3 << 2,
125 DCACHE_WRITEBACK = 4 << 2,
126 DCACHE_WRITEALLOC = 4 << 2,
127 };
128
129 #define wfi() \
130 ({asm volatile( \
131 "wfi" : : : "memory"); \
132 })
133
current_el(void)134 static inline unsigned int current_el(void)
135 {
136 unsigned long el;
137
138 asm volatile("mrs %0, CurrentEL" : "=r" (el) : : "cc");
139 return 3 & (el >> 2);
140 }
141
get_sctlr(void)142 static inline unsigned int get_sctlr(void)
143 {
144 unsigned int el;
145 unsigned long val;
146
147 el = current_el();
148 if (el == 1)
149 asm volatile("mrs %0, sctlr_el1" : "=r" (val) : : "cc");
150 else if (el == 2)
151 asm volatile("mrs %0, sctlr_el2" : "=r" (val) : : "cc");
152 else
153 asm volatile("mrs %0, sctlr_el3" : "=r" (val) : : "cc");
154
155 return val;
156 }
157
set_sctlr(unsigned long val)158 static inline void set_sctlr(unsigned long val)
159 {
160 unsigned int el;
161
162 el = current_el();
163 if (el == 1)
164 asm volatile("msr sctlr_el1, %0" : : "r" (val) : "cc");
165 else if (el == 2)
166 asm volatile("msr sctlr_el2, %0" : : "r" (val) : "cc");
167 else
168 asm volatile("msr sctlr_el3, %0" : : "r" (val) : "cc");
169
170 asm volatile("isb");
171 }
172
read_mpidr(void)173 static inline unsigned long read_mpidr(void)
174 {
175 unsigned long val;
176
177 asm volatile("mrs %0, mpidr_el1" : "=r" (val));
178
179 return val;
180 }
181
182 #define BSP_COREID 0
183
184 void __asm_flush_dcache_all(void);
185 void __asm_invalidate_dcache_all(void);
186 void __asm_flush_dcache_range(u64 start, u64 end);
187
188 /**
189 * __asm_invalidate_dcache_range() - Invalidate a range of virtual addresses
190 *
191 * This performance an invalidate from @start to @end - 1. Both addresses
192 * should be cache-aligned, otherwise this function will align the start
193 * address and may continue past the end address.
194 *
195 * Data in the address range is evicted from the cache and is not written back
196 * to memory.
197 *
198 * @start: Start address to invalidate
199 * @end: End address to invalidate up to (exclusive)
200 */
201 void __asm_invalidate_dcache_range(u64 start, u64 end);
202 void __asm_invalidate_tlb_all(void);
203 void __asm_invalidate_icache_all(void);
204 int __asm_invalidate_l3_dcache(void);
205 int __asm_flush_l3_dcache(void);
206 int __asm_invalidate_l3_icache(void);
207 void __asm_switch_ttbr(u64 new_ttbr);
208
209 /*
210 * armv8_switch_to_el2() - switch from EL3 to EL2 for ARMv8
211 *
212 * @args: For loading 64-bit OS, fdt address.
213 * For loading 32-bit OS, zero.
214 * @mach_nr: For loading 64-bit OS, zero.
215 * For loading 32-bit OS, machine nr
216 * @fdt_addr: For loading 64-bit OS, zero.
217 * For loading 32-bit OS, fdt address.
218 * @arg4: Input argument.
219 * @entry_point: kernel entry point
220 * @es_flag: execution state flag, ES_TO_AARCH64 or ES_TO_AARCH32
221 */
222 void __noreturn armv8_switch_to_el2(u64 args, u64 mach_nr, u64 fdt_addr,
223 u64 arg4, u64 entry_point, u64 es_flag);
224 /*
225 * armv8_switch_to_el1() - switch from EL2 to EL1 for ARMv8
226 *
227 * @args: For loading 64-bit OS, fdt address.
228 * For loading 32-bit OS, zero.
229 * @mach_nr: For loading 64-bit OS, zero.
230 * For loading 32-bit OS, machine nr
231 * @fdt_addr: For loading 64-bit OS, zero.
232 * For loading 32-bit OS, fdt address.
233 * @arg4: Input argument.
234 * @entry_point: kernel entry point
235 * @es_flag: execution state flag, ES_TO_AARCH64 or ES_TO_AARCH32
236 */
237 void armv8_switch_to_el1(u64 args, u64 mach_nr, u64 fdt_addr,
238 u64 arg4, u64 entry_point, u64 es_flag);
239 void armv8_el2_to_aarch32(u64 args, u64 mach_nr, u64 fdt_addr,
240 u64 arg4, u64 entry_point);
241 void gic_init(void);
242 void gic_send_sgi(unsigned long sgino);
243 void wait_for_wakeup(void);
244 void protect_secure_region(void);
245 void smp_kick_all_cpus(void);
246
247 void flush_l3_cache(void);
248 void mmu_change_region_attr(phys_addr_t start, size_t size, u64 attrs);
249
250 /*
251 * smc_call() - issue a secure monitor call
252 *
253 * Issue a secure monitor call in accordance with ARM "SMC Calling convention",
254 * DEN0028A
255 *
256 * @args: input and output arguments
257 */
258 void smc_call(struct pt_regs *args);
259
260 void __noreturn psci_system_reset(void);
261 void __noreturn psci_system_reset2(u32 reset_level, u32 cookie);
262 void __noreturn psci_system_off(void);
263
264 #ifdef CONFIG_ARMV8_PSCI
265 extern char __secure_start[];
266 extern char __secure_end[];
267 extern char __secure_stack_start[];
268 extern char __secure_stack_end[];
269
270 void armv8_setup_psci(void);
271 void psci_setup_vectors(void);
272 void psci_arch_init(void);
273 #endif
274
275 #endif /* __ASSEMBLY__ */
276
277 #else /* CONFIG_ARM64 */
278
279 #ifdef __KERNEL__
280
281 #define CPU_ARCH_UNKNOWN 0
282 #define CPU_ARCH_ARMv3 1
283 #define CPU_ARCH_ARMv4 2
284 #define CPU_ARCH_ARMv4T 3
285 #define CPU_ARCH_ARMv5 4
286 #define CPU_ARCH_ARMv5T 5
287 #define CPU_ARCH_ARMv5TE 6
288 #define CPU_ARCH_ARMv5TEJ 7
289 #define CPU_ARCH_ARMv6 8
290 #define CPU_ARCH_ARMv7 9
291
292 /*
293 * CR1 bits (CP#15 CR1)
294 */
295 #define CR_M (1 << 0) /* MMU enable */
296 #define CR_A (1 << 1) /* Alignment abort enable */
297 #define CR_C (1 << 2) /* Dcache enable */
298 #define CR_W (1 << 3) /* Write buffer enable */
299 #define CR_P (1 << 4) /* 32-bit exception handler */
300 #define CR_D (1 << 5) /* 32-bit data address range */
301 #define CR_L (1 << 6) /* Implementation defined */
302 #define CR_B (1 << 7) /* Big endian */
303 #define CR_S (1 << 8) /* System MMU protection */
304 #define CR_R (1 << 9) /* ROM MMU protection */
305 #define CR_F (1 << 10) /* Implementation defined */
306 #define CR_Z (1 << 11) /* Implementation defined */
307 #define CR_I (1 << 12) /* Icache enable */
308 #define CR_V (1 << 13) /* Vectors relocated to 0xffff0000 */
309 #define CR_RR (1 << 14) /* Round Robin cache replacement */
310 #define CR_L4 (1 << 15) /* LDR pc can set T bit */
311 #define CR_DT (1 << 16)
312 #define CR_IT (1 << 18)
313 #define CR_ST (1 << 19)
314 #define CR_FI (1 << 21) /* Fast interrupt (lower latency mode) */
315 #define CR_U (1 << 22) /* Unaligned access operation */
316 #define CR_XP (1 << 23) /* Extended page tables */
317 #define CR_VE (1 << 24) /* Vectored interrupts */
318 #define CR_EE (1 << 25) /* Exception (Big) Endian */
319 #define CR_TRE (1 << 28) /* TEX remap enable */
320 #define CR_AFE (1 << 29) /* Access flag enable */
321 #define CR_TE (1 << 30) /* Thumb exception enable */
322
323 #if defined(CONFIG_ARMV7_LPAE) && !defined(PGTABLE_SIZE)
324 #define PGTABLE_SIZE (4096 * 5)
325 #elif !defined(PGTABLE_SIZE)
326 #define PGTABLE_SIZE (4096 * 4)
327 #endif
328
329 /*
330 * This is used to ensure the compiler did actually allocate the register we
331 * asked it for some inline assembly sequences. Apparently we can't trust
332 * the compiler from one version to another so a bit of paranoia won't hurt.
333 * This string is meant to be concatenated with the inline asm string and
334 * will cause compilation to stop on mismatch.
335 * (for details, see gcc PR 15089)
336 */
337 #define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t"
338
339 #ifndef __ASSEMBLY__
340
341 #ifdef CONFIG_ARMV7_LPAE
342 void switch_to_hypervisor_ret(void);
343 #endif
344
345 #define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
346
347 #ifdef __ARM_ARCH_7A__
348 #define wfi() __asm__ __volatile__ ("wfi" : : : "memory")
349 #else
350 #define wfi()
351 #endif
352
get_cpsr(void)353 static inline unsigned long get_cpsr(void)
354 {
355 unsigned long cpsr;
356
357 asm volatile("mrs %0, cpsr" : "=r"(cpsr): );
358 return cpsr;
359 }
360
is_hyp(void)361 static inline int is_hyp(void)
362 {
363 #ifdef CONFIG_ARMV7_LPAE
364 /* HYP mode requires LPAE ... */
365 return ((get_cpsr() & 0x1f) == 0x1a);
366 #else
367 /* ... so without LPAE support we can optimize all hyp code away */
368 return 0;
369 #endif
370 }
371
get_cr(void)372 static inline unsigned int get_cr(void)
373 {
374 unsigned int val;
375
376 if (is_hyp())
377 asm volatile("mrc p15, 4, %0, c1, c0, 0 @ get CR" : "=r" (val)
378 :
379 : "cc");
380 else
381 asm volatile("mrc p15, 0, %0, c1, c0, 0 @ get CR" : "=r" (val)
382 :
383 : "cc");
384 return val;
385 }
386
set_cr(unsigned int val)387 static inline void set_cr(unsigned int val)
388 {
389 if (is_hyp())
390 asm volatile("mcr p15, 4, %0, c1, c0, 0 @ set CR" :
391 : "r" (val)
392 : "cc");
393 else
394 asm volatile("mcr p15, 0, %0, c1, c0, 0 @ set CR" :
395 : "r" (val)
396 : "cc");
397 isb();
398 }
399
400 #ifdef CONFIG_ARMV7_LPAE
401 /* Long-Descriptor Translation Table Level 1/2 Bits */
402 #define TTB_SECT_XN_MASK (1ULL << 54)
403 #define TTB_SECT_NG_MASK (1 << 11)
404 #define TTB_SECT_AF (1 << 10)
405 #define TTB_SECT_SH_MASK (3 << 8)
406 #define TTB_SECT_NS_MASK (1 << 5)
407 #define TTB_SECT_AP (1 << 6)
408 /* Note: TTB AP bits are set elsewhere */
409 #define TTB_SECT_MAIR(x) ((x & 0x7) << 2) /* Index into MAIR */
410 #define TTB_SECT (1 << 0)
411 #define TTB_PAGETABLE (3 << 0)
412
413 /* TTBCR flags */
414 #define TTBCR_EAE (1 << 31)
415 #define TTBCR_T0SZ(x) ((x) << 0)
416 #define TTBCR_T1SZ(x) ((x) << 16)
417 #define TTBCR_USING_TTBR0 (TTBCR_T0SZ(0) | TTBCR_T1SZ(0))
418 #define TTBCR_IRGN0_NC (0 << 8)
419 #define TTBCR_IRGN0_WBWA (1 << 8)
420 #define TTBCR_IRGN0_WT (2 << 8)
421 #define TTBCR_IRGN0_WBNWA (3 << 8)
422 #define TTBCR_IRGN0_MASK (3 << 8)
423 #define TTBCR_ORGN0_NC (0 << 10)
424 #define TTBCR_ORGN0_WBWA (1 << 10)
425 #define TTBCR_ORGN0_WT (2 << 10)
426 #define TTBCR_ORGN0_WBNWA (3 << 10)
427 #define TTBCR_ORGN0_MASK (3 << 10)
428 #define TTBCR_SHARED_NON (0 << 12)
429 #define TTBCR_SHARED_OUTER (2 << 12)
430 #define TTBCR_SHARED_INNER (3 << 12)
431 #define TTBCR_EPD0 (0 << 7)
432
433 /*
434 * VMSAv8-32 Long-descriptor format memory region attributes
435 * (ARM Architecture Reference Manual section G5.7.4 [DDI0487E.a])
436 *
437 * MAIR0[ 7: 0] 0x00 Device-nGnRnE (aka Strongly-Ordered)
438 * MAIR0[15: 8] 0xaa Outer/Inner Write-Through, Read-Allocate No Write-Allocate
439 * MAIR0[23:16] 0xee Outer/Inner Write-Back, Read-Allocate No Write-Allocate
440 * MAIR0[31:24] 0xff Outer/Inner Write-Back, Read-Allocate Write-Allocate
441 */
442 #define MEMORY_ATTRIBUTES ((0x00 << (0 * 8)) | (0xaa << (1 * 8)) | \
443 (0xee << (2 * 8)) | (0xff << (3 * 8)))
444
445 /* options available for data cache on each page */
446 enum dcache_option {
447 DCACHE_OFF = TTB_SECT | TTB_SECT_MAIR(0) | TTB_SECT_XN_MASK,
448 DCACHE_WRITETHROUGH = TTB_SECT | TTB_SECT_MAIR(1),
449 DCACHE_WRITEBACK = TTB_SECT | TTB_SECT_MAIR(2),
450 DCACHE_WRITEALLOC = TTB_SECT | TTB_SECT_MAIR(3),
451 };
452 #elif defined(CONFIG_CPU_V7A)
453 /* Short-Descriptor Translation Table Level 1 Bits */
454 #define TTB_SECT_NS_MASK (1 << 19)
455 #define TTB_SECT_NG_MASK (1 << 17)
456 #define TTB_SECT_S_MASK (1 << 16)
457 /* Note: TTB AP bits are set elsewhere */
458 #define TTB_SECT_AP (3 << 10)
459 #define TTB_SECT_TEX(x) ((x & 0x7) << 12)
460 #define TTB_SECT_DOMAIN(x) ((x & 0xf) << 5)
461 #define TTB_SECT_XN_MASK (1 << 4)
462 #define TTB_SECT_C_MASK (1 << 3)
463 #define TTB_SECT_B_MASK (1 << 2)
464 #define TTB_SECT (2 << 0)
465
466 /*
467 * Short-descriptor format memory region attributes, without TEX remap
468 * (ARM Architecture Reference Manual section G5.7.2 [DDI0487E.a])
469 *
470 * TEX[0] C B
471 * 0 0 0 Device-nGnRnE (aka Strongly-Ordered)
472 * 0 1 0 Outer/Inner Write-Through, Read-Allocate No Write-Allocate
473 * 0 1 1 Outer/Inner Write-Back, Read-Allocate No Write-Allocate
474 * 1 1 1 Outer/Inner Write-Back, Read-Allocate Write-Allocate
475 */
476 enum dcache_option {
477 DCACHE_OFF = TTB_SECT_DOMAIN(0) | TTB_SECT_XN_MASK | TTB_SECT,
478 DCACHE_WRITETHROUGH = TTB_SECT_DOMAIN(0) | TTB_SECT | TTB_SECT_C_MASK,
479 DCACHE_WRITEBACK = DCACHE_WRITETHROUGH | TTB_SECT_B_MASK,
480 DCACHE_WRITEALLOC = DCACHE_WRITEBACK | TTB_SECT_TEX(1),
481 };
482 #else
483 #define TTB_SECT_AP (3 << 10)
484 /* options available for data cache on each page */
485 enum dcache_option {
486 DCACHE_OFF = 0x12,
487 DCACHE_WRITETHROUGH = 0x1a,
488 DCACHE_WRITEBACK = 0x1e,
489 DCACHE_WRITEALLOC = 0x16,
490 };
491 #endif
492
493 #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
494 #define DCACHE_DEFAULT_OPTION DCACHE_WRITETHROUGH
495 #elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
496 #define DCACHE_DEFAULT_OPTION DCACHE_WRITEALLOC
497 #elif defined(CONFIG_SYS_ARM_CACHE_WRITEBACK)
498 #define DCACHE_DEFAULT_OPTION DCACHE_WRITEBACK
499 #endif
500
501 /* Size of an MMU section */
502 enum {
503 #ifdef CONFIG_ARMV7_LPAE
504 MMU_SECTION_SHIFT = 21, /* 2MB */
505 #else
506 MMU_SECTION_SHIFT = 20, /* 1MB */
507 #endif
508 MMU_SECTION_SIZE = 1 << MMU_SECTION_SHIFT,
509 };
510
511 #ifdef CONFIG_CPU_V7A
512 /* TTBR0 bits */
513 #define TTBR0_BASE_ADDR_MASK 0xFFFFC000
514 #define TTBR0_RGN_NC (0 << 3)
515 #define TTBR0_RGN_WBWA (1 << 3)
516 #define TTBR0_RGN_WT (2 << 3)
517 #define TTBR0_RGN_WB (3 << 3)
518 /* TTBR0[6] is IRGN[0] and TTBR[0] is IRGN[1] */
519 #define TTBR0_IRGN_NC (0 << 0 | 0 << 6)
520 #define TTBR0_IRGN_WBWA (0 << 0 | 1 << 6)
521 #define TTBR0_IRGN_WT (1 << 0 | 0 << 6)
522 #define TTBR0_IRGN_WB (1 << 0 | 1 << 6)
523 #endif
524
525 /**
526 * mmu_page_table_flush() - register an update to page tables
527 *
528 * Register an update to the page tables, and flush the TLB
529 *
530 * @start: start address of update in page table
531 * @stop: stop address of update in page table
532 */
533 void mmu_page_table_flush(unsigned long start, unsigned long stop);
534
535 #ifdef CONFIG_ARMV7_PSCI
536 void psci_arch_cpu_entry(void);
537 void psci_arch_init(void);
538 u32 psci_version(void);
539 s32 psci_features(u32 function_id, u32 psci_fid);
540 s32 psci_cpu_off(void);
541 s32 psci_cpu_on(u32 function_id, u32 target_cpu, u32 pc,
542 u32 context_id);
543 s32 psci_affinity_info(u32 function_id, u32 target_affinity,
544 u32 lowest_affinity_level);
545 u32 psci_migrate_info_type(void);
546 void psci_system_off(void);
547 void psci_system_reset(void);
548 s32 psci_features(u32 function_id, u32 psci_fid);
549 #endif
550
551 #endif /* __ASSEMBLY__ */
552
553 #define arch_align_stack(x) (x)
554
555 #endif /* __KERNEL__ */
556
557 #endif /* CONFIG_ARM64 */
558
559 #ifndef __ASSEMBLY__
560 /**
561 * save_boot_params() - Save boot parameters before starting reset sequence
562 *
563 * If you provide this function it will be called immediately U-Boot starts,
564 * both for SPL and U-Boot proper.
565 *
566 * All registers are unchanged from U-Boot entry. No registers need be
567 * preserved.
568 *
569 * This is not a normal C function. There is no stack. Return by branching to
570 * save_boot_params_ret.
571 *
572 * void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3);
573 */
574
575 /**
576 * save_boot_params_ret() - Return from save_boot_params()
577 *
578 * If you provide save_boot_params(), then you should jump back to this
579 * function when done. Try to preserve all registers.
580 *
581 * If your implementation of save_boot_params() is in C then it is acceptable
582 * to simply call save_boot_params_ret() at the end of your function. Since
583 * there is no link register set up, you cannot just exit the function. U-Boot
584 * will return to the (initialised) value of lr, and likely crash/hang.
585 *
586 * If your implementation of save_boot_params() is in assembler then you
587 * should use 'b' or 'bx' to return to save_boot_params_ret.
588 */
589 void save_boot_params_ret(void);
590
591 /**
592 * mmu_set_region_dcache_behaviour_phys() - set virt/phys mapping
593 *
594 * Change the virt/phys mapping and cache settings for a region.
595 *
596 * @virt: virtual start address of memory region to change
597 * @phys: physical address for the memory region to set
598 * @size: size of memory region to change
599 * @option: dcache option to select
600 */
601 void mmu_set_region_dcache_behaviour_phys(phys_addr_t virt, phys_addr_t phys,
602 size_t size, enum dcache_option option);
603
604 /**
605 * mmu_set_region_dcache_behaviour() - set cache settings
606 *
607 * Change the cache settings for a region.
608 *
609 * @start: start address of memory region to change
610 * @size: size of memory region to change
611 * @option: dcache option to select
612 */
613 void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
614 enum dcache_option option);
615
616 #ifdef CONFIG_SYS_NONCACHED_MEMORY
617 /**
618 * noncached_init() - Initialize non-cached memory region
619 *
620 * Initialize non-cached memory area. This memory region will be typically
621 * located right below the malloc() area and mapped uncached in the MMU.
622 *
623 * It is called during the generic post-relocation init sequence.
624 *
625 * Return: 0 if OK
626 */
627 int noncached_init(void);
628
629 phys_addr_t noncached_alloc(size_t size, size_t align);
630 #endif /* CONFIG_SYS_NONCACHED_MEMORY */
631
632 #endif /* __ASSEMBLY__ */
633
634 #endif
635