1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2008-2010 Freescale Semiconductor, Inc.
4 */
5
6 #include <common.h>
7 #include <cpu_func.h>
8 #include <asm/global_data.h>
9 #include <asm/processor.h>
10 #include <asm/mmu.h>
11 #include <ioports.h>
12 #include <lmb.h>
13 #include <asm/io.h>
14 #include <asm/mp.h>
15
16 DECLARE_GLOBAL_DATA_PTR;
17
cpu_reset(u32 nr)18 int cpu_reset(u32 nr)
19 {
20 /* dummy function so common/cmd_mp.c will build
21 * should be implemented in the future, when cpu_release()
22 * is supported. Be aware there may be a similiar bug
23 * as exists on MPC85xx w/its PIC having a timing window
24 * associated to resetting the core */
25 return 1;
26 }
27
cpu_status(u32 nr)28 int cpu_status(u32 nr)
29 {
30 /* dummy function so common/cmd_mp.c will build */
31 return 0;
32 }
33
cpu_disable(u32 nr)34 int cpu_disable(u32 nr)
35 {
36 volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
37 volatile ccsr_gur_t *gur = &immap->im_gur;
38
39 switch (nr) {
40 case 0:
41 setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_CPU0);
42 break;
43 case 1:
44 setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_CPU1);
45 break;
46 default:
47 printf("Invalid cpu number for disable %d\n", nr);
48 return 1;
49 }
50
51 return 0;
52 }
53
is_core_disabled(int nr)54 int is_core_disabled(int nr) {
55 immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
56 ccsr_gur_t *gur = &immap->im_gur;
57 u32 devdisr = in_be32(&gur->devdisr);
58
59 switch (nr) {
60 case 0:
61 return (devdisr & MPC86xx_DEVDISR_CPU0);
62 case 1:
63 return (devdisr & MPC86xx_DEVDISR_CPU1);
64 default:
65 printf("Invalid cpu number for disable %d\n", nr);
66 }
67
68 return 0;
69 }
70
cpu_release(u32 nr,int argc,char * const argv[])71 int cpu_release(u32 nr, int argc, char *const argv[])
72 {
73 /* dummy function so common/cmd_mp.c will build
74 * should be implemented in the future */
75 return 1;
76 }
77
determine_mp_bootpg(unsigned int * pagesize)78 u32 determine_mp_bootpg(unsigned int *pagesize)
79 {
80 if (pagesize)
81 *pagesize = 4096;
82
83 /* if we have 4G or more of memory, put the boot page at 4Gb-1M */
84 if ((u64)gd->ram_size > 0xfffff000)
85 return (0xfff00000);
86
87 return (gd->ram_size - (1024 * 1024));
88 }
89
cpu_mp_lmb_reserve(struct lmb * lmb)90 void cpu_mp_lmb_reserve(struct lmb *lmb)
91 {
92 u32 bootpg = determine_mp_bootpg(NULL);
93
94 /* tell u-boot we stole a page */
95 lmb_reserve(lmb, bootpg, 4096);
96 }
97
98 /*
99 * Copy the code for other cpus to execute into an
100 * aligned location accessible via BPTR
101 */
setup_mp(void)102 void setup_mp(void)
103 {
104 extern ulong __secondary_start_page;
105 ulong fixup = (ulong)&__secondary_start_page;
106 u32 bootpg = determine_mp_bootpg(NULL);
107 u32 bootpg_va;
108
109 if (bootpg >= CONFIG_SYS_MAX_DDR_BAT_SIZE) {
110 /* We're not covered by the DDR mapping, set up BAT */
111 write_bat(DBAT7, CONFIG_SYS_SCRATCH_VA | BATU_BL_128K |
112 BATU_VS | BATU_VP,
113 bootpg | BATL_PP_RW | BATL_MEMCOHERENCE);
114 bootpg_va = CONFIG_SYS_SCRATCH_VA;
115 } else {
116 bootpg_va = bootpg;
117 }
118
119 memcpy((void *)bootpg_va, (void *)fixup, 4096);
120 flush_cache(bootpg_va, 4096);
121
122 /* remove the temporary BAT mapping */
123 if (bootpg >= CONFIG_SYS_MAX_DDR_BAT_SIZE)
124 write_bat(DBAT7, 0, 0);
125
126 /* If the physical location of bootpg is not at fff00000, set BPTR */
127 if (bootpg != 0xfff00000)
128 out_be32((uint *)(CONFIG_SYS_CCSRBAR + 0x20), 0x80000000 |
129 (bootpg >> 12));
130 }
131