1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * board.c
4  *
5  * Board functions for B&R BRSMARC1 Board
6  *
7  * Copyright (C) 2017 Hannes Schmelzer <oe5hpm@oevsv.at>
8  * B&R Industrial Automation GmbH - http://www.br-automation.com
9  *
10  */
11 #include <common.h>
12 #include <errno.h>
13 #include <init.h>
14 #include <spl.h>
15 #include <asm/arch/cpu.h>
16 #include <asm/arch/hardware.h>
17 #include <asm/arch/omap.h>
18 #include <asm/arch/ddr_defs.h>
19 #include <asm/arch/clock.h>
20 #include <asm/arch/sys_proto.h>
21 #include <asm/arch/mem.h>
22 #include <asm/global_data.h>
23 #include <asm/io.h>
24 #include <asm/gpio.h>
25 #include <asm/emif.h>
26 #include <power/tps65217.h>
27 #include "../common/bur_common.h"
28 #include "../common/br_resetc.h"
29 
30 /* -------------------------------------------------------------------------*/
31 /* -- defines for used GPIO Hardware -- */
32 #define PER_RESET		(2 * 32 + 0)
33 
34 DECLARE_GLOBAL_DATA_PTR;
35 
36 #if defined(CONFIG_SPL_BUILD)
37 static const struct ddr_data ddr3_data = {
38 	.datardsratio0 = MT41K256M16HA125E_RD_DQS,
39 	.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
40 	.datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
41 	.datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
42 };
43 
44 static const struct cmd_control ddr3_cmd_ctrl_data = {
45 	.cmd0csratio = MT41K256M16HA125E_RATIO,
46 	.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
47 
48 	.cmd1csratio = MT41K256M16HA125E_RATIO,
49 	.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
50 
51 	.cmd2csratio = MT41K256M16HA125E_RATIO,
52 	.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
53 };
54 
55 static struct emif_regs ddr3_emif_reg_data = {
56 	.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
57 	.ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
58 	.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
59 	.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
60 	.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
61 	.zq_config = MT41K256M16HA125E_ZQ_CFG,
62 	.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
63 };
64 
65 static const struct ctrl_ioregs ddr3_ioregs = {
66 	.cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
67 	.cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
68 	.cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
69 	.dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
70 	.dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
71 };
72 
73 #define OSC	(V_OSCK / 1000000)
74 const struct dpll_params dpll_ddr3 = { 400, OSC - 1, 1, -1, -1, -1, -1};
75 
am33xx_spl_board_init(void)76 void am33xx_spl_board_init(void)
77 {
78 	struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
79 	struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;
80 
81 	int rc;
82 	/*
83 	 * enable additional clocks of modules which are accessed later from
84 	 * VxWorks OS
85 	 */
86 	u32 *const clk_domains[] = { 0 };
87 	u32 *const clk_modules_specific[] = {
88 		&cmwkup->wkup_adctscctrl,
89 		&cmper->spi1clkctrl,
90 		&cmper->dcan0clkctrl,
91 		&cmper->dcan1clkctrl,
92 		&cmper->timer4clkctrl,
93 		&cmper->timer5clkctrl,
94 		&cmper->lcdclkctrl,
95 		&cmper->lcdcclkstctrl,
96 		0
97 	};
98 	do_enable_clocks(clk_domains, clk_modules_specific, 1);
99 
100 	/* setup I2C */
101 	enable_i2c_pin_mux();
102 
103 	/* peripheral reset */
104 	rc = gpio_request(PER_RESET, "PER_RESET");
105 	if (rc != 0)
106 		printf("cannot request PER_RESET GPIO!\n");
107 
108 	rc = gpio_direction_output(PER_RESET, 0);
109 	if (rc != 0)
110 		printf("cannot set PER_RESET GPIO!\n");
111 
112 	/* setup pmic */
113 	pmicsetup(0, 0);
114 }
115 
get_dpll_ddr_params(void)116 const struct dpll_params *get_dpll_ddr_params(void)
117 {
118 	return &dpll_ddr3;
119 }
120 
sdram_init(void)121 void sdram_init(void)
122 {
123 	config_ddr(400, &ddr3_ioregs,
124 		   &ddr3_data,
125 		   &ddr3_cmd_ctrl_data,
126 		   &ddr3_emif_reg_data, 0);
127 }
128 #endif /* CONFIG_SPL_BUILD */
129 #if !defined(CONFIG_SPL_BUILD)
130 
131 /* decision if backlight is switched on or not on powerup */
board_backlightstate(void)132 int board_backlightstate(void)
133 {
134 	u8 bklmask, rstcause;
135 	int rc = 0;
136 
137 	rc |= br_resetc_regget(RSTCTRL_SCRATCHREG1, &bklmask);
138 	rc |= br_resetc_regget(RSTCTRL_ERSTCAUSE, &rstcause);
139 
140 	if (rc != 0) {
141 		printf("%s: read rstctrl failed!\n", __func__);
142 		return 1;
143 	}
144 
145 	if ((rstcause & bklmask) != 0)
146 		return 0;
147 
148 	return 1;
149 }
150 
151 /* Basic board specific setup. run quite after relocation */
board_init(void)152 int board_init(void)
153 {
154 	if (power_tps65217_init(0))
155 		printf("WARN: cannot setup PMIC 0x24 @ bus #0, not found!.\n");
156 
157 	return 0;
158 }
159 
160 #if defined(CONFIG_BOARD_LATE_INIT)
161 
board_late_init(void)162 int board_late_init(void)
163 {
164 	br_resetc_bmode();
165 
166 	return 0;
167 }
168 
169 #endif /* CONFIG_BOARD_LATE_INIT */
170 #endif /* !CONFIG_SPL_BUILD */
171