1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
4 */
5
6 /*
7 * PCI Configuration space access support for MPC83xx PCI Bridge
8 */
9 #include <init.h>
10 #include <asm/mmu.h>
11 #include <asm/io.h>
12 #include <common.h>
13 #include <mpc83xx.h>
14 #include <pci.h>
15 #include <i2c.h>
16 #include <asm/fsl_i2c.h>
17 #include <linux/delay.h>
18 #include "../common/pq-mds-pib.h"
19
20 static struct pci_region pci1_regions[] = {
21 {
22 bus_start: CONFIG_SYS_PCI1_MEM_BASE,
23 phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
24 size: CONFIG_SYS_PCI1_MEM_SIZE,
25 flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
26 },
27 {
28 bus_start: CONFIG_SYS_PCI1_IO_BASE,
29 phys_start: CONFIG_SYS_PCI1_IO_PHYS,
30 size: CONFIG_SYS_PCI1_IO_SIZE,
31 flags: PCI_REGION_IO
32 },
33 {
34 bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
35 phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
36 size: CONFIG_SYS_PCI1_MMIO_SIZE,
37 flags: PCI_REGION_MEM
38 },
39 };
40
41 #ifdef CONFIG_MPC83XX_PCI2
42 static struct pci_region pci2_regions[] = {
43 {
44 bus_start: CONFIG_SYS_PCI2_MEM_BASE,
45 phys_start: CONFIG_SYS_PCI2_MEM_PHYS,
46 size: CONFIG_SYS_PCI2_MEM_SIZE,
47 flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
48 },
49 {
50 bus_start: CONFIG_SYS_PCI2_IO_BASE,
51 phys_start: CONFIG_SYS_PCI2_IO_PHYS,
52 size: CONFIG_SYS_PCI2_IO_SIZE,
53 flags: PCI_REGION_IO
54 },
55 {
56 bus_start: CONFIG_SYS_PCI2_MMIO_BASE,
57 phys_start: CONFIG_SYS_PCI2_MMIO_PHYS,
58 size: CONFIG_SYS_PCI2_MMIO_SIZE,
59 flags: PCI_REGION_MEM
60 },
61 };
62 #endif
63
pci_init_board(void)64 void pci_init_board(void)
65 #ifdef CONFIG_PCISLAVE
66 {
67 volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
68 volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
69 volatile pcictrl83xx_t *pci_ctrl = &immr->pci_ctrl[0];
70 struct pci_region *reg[] = { pci1_regions };
71
72 /* Configure PCI Local Access Windows */
73 pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
74 pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
75
76 pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
77 pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
78
79 mpc83xx_pci_init(1, reg);
80
81 /*
82 * Configure PCI Inbound Translation Windows
83 */
84 pci_ctrl[0].pitar0 = 0x0;
85 pci_ctrl[0].pibar0 = 0x0;
86 pci_ctrl[0].piwar0 = PIWAR_EN | PIWAR_RTT_SNOOP |
87 PIWAR_WTT_SNOOP | PIWAR_IWS_4K;
88
89 pci_ctrl[0].pitar1 = 0x0;
90 pci_ctrl[0].pibar1 = 0x0;
91 pci_ctrl[0].piebar1 = 0x0;
92 pci_ctrl[0].piwar1 &= ~PIWAR_EN;
93
94 pci_ctrl[0].pitar2 = 0x0;
95 pci_ctrl[0].pibar2 = 0x0;
96 pci_ctrl[0].piebar2 = 0x0;
97 pci_ctrl[0].piwar2 &= ~PIWAR_EN;
98
99 /* Unlock the configuration bit */
100 mpc83xx_pcislave_unlock(0);
101 printf("PCI: Agent mode enabled\n");
102 }
103 #else
104 {
105 volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
106 volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
107 volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
108 #ifndef CONFIG_MPC83XX_PCI2
109 struct pci_region *reg[] = { pci1_regions };
110 #else
111 struct pci_region *reg[] = { pci1_regions, pci2_regions };
112 #endif
113
114 /* initialize the PCA9555PW IO expander on the PIB board */
115 pib_init();
116
117 #if defined(CONFIG_PCI_66M)
118 clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2;
119 printf("PCI clock is 66MHz\n");
120 #elif defined(CONFIG_PCI_33M)
121 clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2 |
122 OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 | OCCR_PCICR;
123 printf("PCI clock is 33MHz\n");
124 #else
125 clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2;
126 printf("PCI clock is 66MHz\n");
127 #endif
128 udelay(2000);
129
130 /* Configure PCI Local Access Windows */
131 pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
132 pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M;
133
134 pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
135 pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_1M;
136
137 udelay(2000);
138
139 #ifndef CONFIG_MPC83XX_PCI2
140 mpc83xx_pci_init(1, reg);
141 #else
142 mpc83xx_pci_init(2, reg);
143 #endif
144 }
145 #endif /* CONFIG_PCISLAVE */
146