1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3 * Copyright (c) 2021 BayLibre, SAS
4 * Author: Neil Armstrong <narmstrong@baylibre.com>
5 *
6 * Copyright (c) 2021 Rockchip, Inc.
7 *
8 * Copyright (C) 2018 Texas Instruments, Inc
9 */
10
11 #ifndef PCIE_DW_COMMON_H
12 #define PCIE_DW_COMMON_H
13
14 #define DEFAULT_DBI_ATU_OFFSET (0x3 << 20)
15
16 /* PCI DBICS registers */
17 #define PCIE_LINK_STATUS_REG 0x80
18 #define PCIE_LINK_STATUS_SPEED_OFF 16
19 #define PCIE_LINK_STATUS_SPEED_MASK (0xf << PCIE_LINK_STATUS_SPEED_OFF)
20 #define PCIE_LINK_STATUS_WIDTH_OFF 20
21 #define PCIE_LINK_STATUS_WIDTH_MASK (0xf << PCIE_LINK_STATUS_WIDTH_OFF)
22
23 /*
24 * iATU Unroll-specific register definitions
25 * From 4.80 core version the address translation will be made by unroll.
26 * The registers are offset from atu_base
27 */
28 #define PCIE_ATU_UNR_REGION_CTRL1 0x00
29 #define PCIE_ATU_UNR_REGION_CTRL2 0x04
30 #define PCIE_ATU_UNR_LOWER_BASE 0x08
31 #define PCIE_ATU_UNR_UPPER_BASE 0x0c
32 #define PCIE_ATU_UNR_LIMIT 0x10
33 #define PCIE_ATU_UNR_LOWER_TARGET 0x14
34 #define PCIE_ATU_UNR_UPPER_TARGET 0x18
35
36 #define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
37 #define PCIE_ATU_REGION_INDEX0 (0x0 << 0)
38 #define PCIE_ATU_TYPE_MEM (0x0 << 0)
39 #define PCIE_ATU_TYPE_IO (0x2 << 0)
40 #define PCIE_ATU_TYPE_CFG0 (0x4 << 0)
41 #define PCIE_ATU_TYPE_CFG1 (0x5 << 0)
42 #define PCIE_ATU_ENABLE (0x1 << 31)
43 #define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30)
44 #define PCIE_ATU_BUS(x) (((x) & 0xff) << 24)
45 #define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19)
46 #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
47
48 /* Register address builder */
49 #define PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(region) ((region) << 9)
50
51 /* Parameters for the waiting for iATU enabled routine */
52 #define LINK_WAIT_MAX_IATU_RETRIES 5
53 #define LINK_WAIT_IATU_US 10000
54
55 /* PCI DBICS registers */
56 #define PCIE_LINK_STATUS_REG 0x80
57 #define PCIE_LINK_STATUS_SPEED_OFF 16
58 #define PCIE_LINK_STATUS_SPEED_MASK (0xf << PCIE_LINK_STATUS_SPEED_OFF)
59 #define PCIE_LINK_STATUS_WIDTH_OFF 20
60 #define PCIE_LINK_STATUS_WIDTH_MASK (0xf << PCIE_LINK_STATUS_WIDTH_OFF)
61
62 #define PCIE_LINK_CAPABILITY 0x7c
63 #define PCIE_LINK_CTL_2 0xa0
64 #define TARGET_LINK_SPEED_MASK 0xf
65 #define LINK_SPEED_GEN_1 0x1
66 #define LINK_SPEED_GEN_2 0x2
67 #define LINK_SPEED_GEN_3 0x3
68
69 /* Synopsys-specific PCIe configuration registers */
70 #define PCIE_PORT_LINK_CONTROL 0x710
71 #define PORT_LINK_DLL_LINK_EN BIT(5)
72 #define PORT_LINK_FAST_LINK_MODE BIT(7)
73 #define PORT_LINK_MODE_MASK GENMASK(21, 16)
74 #define PORT_LINK_MODE(n) FIELD_PREP(PORT_LINK_MODE_MASK, n)
75 #define PORT_LINK_MODE_1_LANES PORT_LINK_MODE(0x1)
76 #define PORT_LINK_MODE_2_LANES PORT_LINK_MODE(0x3)
77 #define PORT_LINK_MODE_4_LANES PORT_LINK_MODE(0x7)
78 #define PORT_LINK_MODE_8_LANES PORT_LINK_MODE(0xf)
79
80 #define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
81 #define PORT_LOGIC_N_FTS_MASK GENMASK(7, 0)
82 #define PORT_LOGIC_SPEED_CHANGE BIT(17)
83 #define PORT_LOGIC_LINK_WIDTH_MASK GENMASK(12, 8)
84 #define PORT_LOGIC_LINK_WIDTH(n) FIELD_PREP(PORT_LOGIC_LINK_WIDTH_MASK, n)
85 #define PORT_LOGIC_LINK_WIDTH_1_LANES PORT_LOGIC_LINK_WIDTH(0x1)
86 #define PORT_LOGIC_LINK_WIDTH_2_LANES PORT_LOGIC_LINK_WIDTH(0x2)
87 #define PORT_LOGIC_LINK_WIDTH_4_LANES PORT_LOGIC_LINK_WIDTH(0x4)
88 #define PORT_LOGIC_LINK_WIDTH_8_LANES PORT_LOGIC_LINK_WIDTH(0x8)
89
90 #define PCIE_MISC_CONTROL_1_OFF 0x8bc
91 #define PCIE_DBI_RO_WR_EN BIT(0)
92
93 /* Parameters for the waiting for iATU enabled routine */
94 #define LINK_WAIT_MAX_IATU_RETRIES 5
95 #define LINK_WAIT_IATU 10000
96
97 /**
98 * struct pcie_dw - DW PCIe controller state
99 *
100 * @dbi_base: The base address of dbi register space
101 * @cfg_base: The base address of configuration space
102 * @atu_base: The base address of ATU space
103 * @cfg_size: The size of the configuration space which is needed
104 * as it gets written into the PCIE_ATU_LIMIT register
105 * @first_busno: This driver supports multiple PCIe controllers.
106 * first_busno stores the bus number of the PCIe root-port
107 * number which may vary depending on the PCIe setup
108 * (PEX switches etc).
109 * @io: The IO space for EP's BAR
110 * @mem: The memory space for EP's BAR
111 * @prefetch: The prefetch space for EP's BAR
112 */
113 struct pcie_dw {
114 struct udevice *dev;
115 void __iomem *dbi_base;
116 void __iomem *cfg_base;
117 void __iomem *atu_base;
118 fdt_size_t cfg_size;
119
120 int first_busno;
121
122 /* IO, MEM & PREFETCH PCI regions */
123 struct pci_region io;
124 struct pci_region mem;
125 struct pci_region prefetch;
126 };
127
128 int pcie_dw_get_link_speed(struct pcie_dw *pci);
129
130 int pcie_dw_get_link_width(struct pcie_dw *pci);
131
132 int pcie_dw_prog_outbound_atu_unroll(struct pcie_dw *pci, int index, int type, u64 cpu_addr,
133 u64 pci_addr, u32 size);
134
135 int pcie_dw_read_config(const struct udevice *bus, pci_dev_t bdf, uint offset, ulong *valuep,
136 enum pci_size_t size);
137
138 int pcie_dw_write_config(struct udevice *bus, pci_dev_t bdf, uint offset, ulong value,
139 enum pci_size_t size);
140
dw_pcie_dbi_write_enable(struct pcie_dw * pci,bool en)141 static inline void dw_pcie_dbi_write_enable(struct pcie_dw *pci, bool en)
142 {
143 u32 val;
144
145 val = readl(pci->dbi_base + PCIE_MISC_CONTROL_1_OFF);
146 if (en)
147 val |= PCIE_DBI_RO_WR_EN;
148 else
149 val &= ~PCIE_DBI_RO_WR_EN;
150 writel(val, pci->dbi_base + PCIE_MISC_CONTROL_1_OFF);
151 }
152
153 void pcie_dw_setup_host(struct pcie_dw *pci);
154
155 #endif
156