1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2015-2021 NXP 4 * Copyright 2014 Freescale Semiconductor, Inc. 5 * 6 */ 7 #ifndef __FSL_STREAM_ID_H 8 #define __FSL_STREAM_ID_H 9 10 /* 11 * Stream IDs on NXP Chassis-3 (for example ls2080a, ls1088a, ls2088a) 12 * devices are not hardwired and are programmed by sw. There are a limited 13 * number of stream IDs available, and the partitioning of them is scenario 14 * dependent. This header defines the partitioning between legacy, 15 * PCI, and DPAA2 devices. 16 * 17 * This partitioning can be customized in this file depending 18 * on the specific hardware config: 19 * 20 * -non-PCI legacy, platform devices (USB, SD/MMC, SATA, DMA) 21 * -all legacy devices get a unique stream ID assigned and programmed in 22 * their AMQR registers by u-boot 23 * 24 * -PCIe 25 * -there is a range of stream IDs set aside for PCI in this 26 * file. U-boot will scan the PCI bus and for each device discovered: 27 * -allocate a streamID 28 * -set a PEXn LUT table entry mapping 'requester ID' to 'stream ID' 29 * -set a msi-map entry in the PEXn controller node in the 30 * device tree (see Documentation/devicetree/bindings/pci/pci-msi.txt 31 * for more info on the msi-map definition) 32 * -set a iommu-map entry in the PEXn controller node in the 33 * device tree (see Documentation/devicetree/bindings/pci/pci-iommu.txt 34 * for more info on the iommu-map definition) 35 * 36 * -DPAA2 37 * -u-boot will allocate a range of stream IDs to be used by the Management 38 * Complex for containers and will set these values in the MC DPC image. 39 * -u-boot will fixup the iommu-map property in the fsl-mc node in the 40 * device tree (see Documentation/devicetree/bindings/misc/fsl,qoriq-mc.txt 41 * for more info on the msi-map definition) 42 * -the MC is responsible for allocating and setting up 'isolation context 43 * IDs (ICIDs) based on the allocated stream IDs for all DPAA2 devices. 44 * 45 * - ECAM (integrated PCI) 46 * - U-Boot applies the value here to HW and does DT fix-up for both 47 * 'iommu-map' and 'msi-map' 48 * 49 * On Chasis-3 SoCs stream IDs are programmed in AMQ registers (32-bits) for 50 * each of the different bus masters. The relationship between 51 * the AMQ registers and stream IDs is defined in the table below: 52 * AMQ bit streamID bit 53 * --------------------------- 54 * PL[18] 9 // privilege bit 55 * BMT[17] 8 // bypass translation 56 * VA[16] 7 // reserved 57 * [15] - // unused 58 * ICID[14:7] - // unused 59 * ICID[6:0] 6-0 // isolation context id 60 * ---------------------------- 61 * 62 */ 63 64 #define AMQ_PL_MASK (0x1 << 18) /* priviledge bit */ 65 #define AMQ_BMT_MASK (0x1 << 17) /* bypass bit */ 66 67 #define FSL_INVALID_STREAM_ID 0 68 69 #define FSL_BYPASS_AMQ (AMQ_PL_MASK | AMQ_BMT_MASK) 70 71 /* legacy devices */ 72 #define FSL_USB1_STREAM_ID 1 73 #define FSL_USB2_STREAM_ID 2 74 #define FSL_SDMMC_STREAM_ID 3 75 #define FSL_SATA1_STREAM_ID 4 76 77 #if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A) || \ 78 defined(CONFIG_ARCH_LX2162A) 79 #define FSL_SATA2_STREAM_ID 5 80 #endif 81 82 #if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A) || \ 83 defined(CONFIG_ARCH_LX2162A) 84 #define FSL_DMA_STREAM_ID 6 85 #elif defined(CONFIG_ARCH_LS1088A) || defined(CONFIG_ARCH_LS1028A) 86 #define FSL_DMA_STREAM_ID 5 87 #endif 88 89 /* PCI - programmed in PEXn_LUT */ 90 #define FSL_PEX_STREAM_ID_START 7 91 92 #if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1028A) 93 #define FSL_PEX_STREAM_ID_END 22 94 #elif defined(CONFIG_ARCH_LS1088A) 95 #define FSL_PEX_STREAM_ID_END 18 96 #elif defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A) 97 #define FSL_PEX_STREAM_ID_END (0x100) 98 #endif 99 100 101 /* DPAA2 - set in MC DPC and alloced by MC */ 102 #define FSL_DPAA2_STREAM_ID_START 23 103 #define FSL_DPAA2_STREAM_ID_END 63 104 105 /* PCI IEPs, this overlaps DPAA2 but these two are exclusive at least for now */ 106 #define FSL_ECAM_STREAM_ID_START 41 107 #define FSL_ECAM_STREAM_ID_END 63 108 109 #define FSL_SEC_STREAM_ID 64 110 #define FSL_SEC_JR1_STREAM_ID 65 111 #define FSL_SEC_JR2_STREAM_ID 66 112 #define FSL_SEC_JR3_STREAM_ID 67 113 #define FSL_SEC_JR4_STREAM_ID 68 114 115 #define FSL_SDMMC2_STREAM_ID 69 116 117 /* 118 * Erratum A-050382 workaround 119 * 120 * Description: 121 * The eDMA ICID programmed in the eDMA_AMQR register in DCFG is not 122 * correctly forwarded to the SMMU. 123 * Workaround: 124 * Program eDMA ICID in the eDMA_AMQR register in DCFG to 40. 125 */ 126 #ifdef CONFIG_SYS_FSL_ERRATUM_A050382 127 #define FSL_EDMA_STREAM_ID 40 128 #else 129 #define FSL_EDMA_STREAM_ID 70 130 #endif 131 132 #define FSL_GPU_STREAM_ID 71 133 #define FSL_DISPLAY_STREAM_ID 72 134 #define FSL_SATA3_STREAM_ID 73 135 #define FSL_SATA4_STREAM_ID 74 136 137 #endif 138