1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2018 Armadeus Systems
4 */
5
6 #include <init.h>
7 #include <asm/arch/clock.h>
8 #include <asm/arch/crm_regs.h>
9 #include <asm/arch/imx-regs.h>
10 #include <asm/arch/sys_proto.h>
11 #include <asm/global_data.h>
12 #include <asm/io.h>
13 #include <common.h>
14 #include <env.h>
15
16 DECLARE_GLOBAL_DATA_PTR;
17
18 #ifdef CONFIG_FEC_MXC
19 #include <miiphy.h>
20
board_phy_config(struct phy_device * phydev)21 int board_phy_config(struct phy_device *phydev)
22 {
23 phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
24
25 if (phydev->drv->config)
26 phydev->drv->config(phydev);
27
28 return 0;
29 }
30
setup_fec(void)31 static int setup_fec(void)
32 {
33 struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
34
35 /* Use 50M anatop loopback REF_CLK1 for ENET1,
36 * clear gpr1[13], set gpr1[17] */
37 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
38 IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
39
40 return enable_fec_anatop_clock(0, ENET_50MHZ);
41 }
42 #endif /* CONFIG_FEC_MXC */
43
board_init(void)44 int board_init(void)
45 {
46 /* Address of boot parameters */
47 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
48
49 #ifdef CONFIG_FEC_MXC
50 setup_fec();
51 #endif
52
53 return 0;
54 }
55
opos6ul_board_late_init(void)56 int __weak opos6ul_board_late_init(void)
57 {
58 return 0;
59 }
60
board_late_init(void)61 int board_late_init(void)
62 {
63 struct src *psrc = (struct src *)SRC_BASE_ADDR;
64 unsigned reg = readl(&psrc->sbmr2);
65
66 /* In bootstrap don't use the env vars */
67 if (((reg & 0x3000000) >> 24) == 0x1) {
68 env_set_default(NULL, 0);
69 env_set("preboot", "");
70 }
71
72 return opos6ul_board_late_init();
73 }
74
dram_init(void)75 int dram_init(void)
76 {
77 gd->ram_size = imx_ddr_size();
78
79 return 0;
80 }
81
82 #ifdef CONFIG_SPL_BUILD
83 #include <asm/arch/mx6-ddr.h>
84 #include <linux/libfdt.h>
85 #include <spl.h>
86
87 static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
88 .grp_addds = 0x00000030,
89 .grp_ddrmode_ctl = 0x00020000,
90 .grp_b0ds = 0x00000030,
91 .grp_ctlds = 0x00000030,
92 .grp_b1ds = 0x00000030,
93 .grp_ddrpke = 0x00000000,
94 .grp_ddrmode = 0x00020000,
95 .grp_ddr_type = 0x000c0000,
96 };
97
98 static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
99 .dram_dqm0 = 0x00000030,
100 .dram_dqm1 = 0x00000030,
101 .dram_ras = 0x00000030,
102 .dram_cas = 0x00000030,
103 .dram_odt0 = 0x00000030,
104 .dram_odt1 = 0x00000030,
105 .dram_sdba2 = 0x00000000,
106 .dram_sdclk_0 = 0x00000008,
107 .dram_sdqs0 = 0x00000038,
108 .dram_sdqs1 = 0x00000030,
109 .dram_reset = 0x00000030,
110 };
111
112 static struct mx6_mmdc_calibration mx6_mmcd_calib = {
113 .p0_mpwldectrl0 = 0x00070007,
114 .p0_mpdgctrl0 = 0x41490145,
115 .p0_mprddlctl = 0x40404546,
116 .p0_mpwrdlctl = 0x4040524D,
117 };
118
119 struct mx6_ddr_sysinfo ddr_sysinfo = {
120 .dsize = 0,
121 .cs_density = 20,
122 .ncs = 1,
123 .cs1_mirror = 0,
124 .rtt_wr = 2,
125 .rtt_nom = 1, /* RTT_Nom = RZQ/2 */
126 .walat = 1, /* Write additional latency */
127 .ralat = 5, /* Read additional latency */
128 .mif3_mode = 3, /* Command prediction working mode */
129 .bi_on = 1, /* Bank interleaving enabled */
130 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
131 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
132 .ddr_type = DDR_TYPE_DDR3,
133 .refsel = 1, /* Refresh cycles at 32KHz */
134 .refr = 7, /* 8 refreshes commands per refresh cycle */
135 };
136
137 static struct mx6_ddr3_cfg mem_ddr = {
138 .mem_speed = 800,
139 .density = 2,
140 .width = 16,
141 .banks = 8,
142 .rowaddr = 14,
143 .coladdr = 10,
144 .pagesz = 2,
145 .trcd = 1500,
146 .trcmin = 5250,
147 .trasmin = 3750,
148 };
149
board_boot_order(u32 * spl_boot_list)150 void board_boot_order(u32 *spl_boot_list)
151 {
152 unsigned int bmode = readl(&src_base->sbmr2);
153
154 if (((bmode >> 24) & 0x03) == 0x01) /* Serial Downloader */
155 spl_boot_list[0] = BOOT_DEVICE_UART;
156 else
157 spl_boot_list[0] = spl_boot_device();
158 }
159
ccgr_init(void)160 static void ccgr_init(void)
161 {
162 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
163
164 writel(0xFFFFFFFF, &ccm->CCGR0);
165 writel(0xFFFFFFFF, &ccm->CCGR1);
166 writel(0xFFFFFFFF, &ccm->CCGR2);
167 writel(0xFFFFFFFF, &ccm->CCGR3);
168 writel(0xFFFFFFFF, &ccm->CCGR4);
169 writel(0xFFFFFFFF, &ccm->CCGR5);
170 writel(0xFFFFFFFF, &ccm->CCGR6);
171 writel(0xFFFFFFFF, &ccm->CCGR7);
172 }
173
spl_dram_init(void)174 static void spl_dram_init(void)
175 {
176 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
177 struct fuse_bank *bank = &ocotp->bank[4];
178 struct fuse_bank4_regs *fuse =
179 (struct fuse_bank4_regs *)bank->fuse_regs;
180 int reg = readl(&fuse->gp1);
181
182 /* 512MB of RAM */
183 if (reg & 0x1) {
184 mem_ddr.density = 4;
185 mem_ddr.rowaddr = 15;
186 mem_ddr.trcd = 1375;
187 mem_ddr.trcmin = 4875;
188 mem_ddr.trasmin = 3500;
189 }
190
191 mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
192 mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
193 }
194
spl_board_init(void)195 void spl_board_init(void)
196 {
197 preloader_console_init();
198 }
199
board_init_f(ulong dummy)200 void board_init_f(ulong dummy)
201 {
202 ccgr_init();
203
204 /* setup AIPS and disable watchdog */
205 arch_cpu_init();
206
207 /* setup GP timer */
208 timer_init();
209
210 /* DDR initialization */
211 spl_dram_init();
212 }
213 #endif /* CONFIG_SPL_BUILD */
214