1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (c) 2013 Xilinx Inc. 4 */ 5 6 #ifndef _ASM_ARCH_HARDWARE_H 7 #define _ASM_ARCH_HARDWARE_H 8 9 #define ZYNQ_SYS_CTRL_BASEADDR 0xF8000000 10 #define ZYNQ_DEV_CFG_APB_BASEADDR 0xF8007000 11 #define ZYNQ_SCU_BASEADDR 0xF8F00000 12 #define ZYNQ_DDRC_BASEADDR 0xF8006000 13 #define ZYNQ_EFUSE_BASEADDR 0xF800D000 14 #define ZYNQ_OCM_BASEADDR 0xFFFC0000 15 16 /* Bootmode setting values */ 17 #define ZYNQ_BM_MASK 0x7 18 #define ZYNQ_BM_QSPI 0x1 19 #define ZYNQ_BM_NOR 0x2 20 #define ZYNQ_BM_NAND 0x4 21 #define ZYNQ_BM_SD 0x5 22 #define ZYNQ_BM_JTAG 0x0 23 24 /* Reflect slcr offsets */ 25 struct slcr_regs { 26 u32 scl; /* 0x0 */ 27 u32 slcr_lock; /* 0x4 */ 28 u32 slcr_unlock; /* 0x8 */ 29 u32 reserved0_1[61]; 30 u32 arm_pll_ctrl; /* 0x100 */ 31 u32 ddr_pll_ctrl; /* 0x104 */ 32 u32 io_pll_ctrl; /* 0x108 */ 33 u32 reserved0_2[5]; 34 u32 arm_clk_ctrl; /* 0x120 */ 35 u32 ddr_clk_ctrl; /* 0x124 */ 36 u32 dci_clk_ctrl; /* 0x128 */ 37 u32 aper_clk_ctrl; /* 0x12c */ 38 u32 reserved0_3[2]; 39 u32 gem0_rclk_ctrl; /* 0x138 */ 40 u32 gem1_rclk_ctrl; /* 0x13c */ 41 u32 gem0_clk_ctrl; /* 0x140 */ 42 u32 gem1_clk_ctrl; /* 0x144 */ 43 u32 smc_clk_ctrl; /* 0x148 */ 44 u32 lqspi_clk_ctrl; /* 0x14c */ 45 u32 sdio_clk_ctrl; /* 0x150 */ 46 u32 uart_clk_ctrl; /* 0x154 */ 47 u32 spi_clk_ctrl; /* 0x158 */ 48 u32 can_clk_ctrl; /* 0x15c */ 49 u32 can_mioclk_ctrl; /* 0x160 */ 50 u32 dbg_clk_ctrl; /* 0x164 */ 51 u32 pcap_clk_ctrl; /* 0x168 */ 52 u32 reserved0_4[1]; 53 u32 fpga0_clk_ctrl; /* 0x170 */ 54 u32 reserved0_5[3]; 55 u32 fpga1_clk_ctrl; /* 0x180 */ 56 u32 reserved0_6[3]; 57 u32 fpga2_clk_ctrl; /* 0x190 */ 58 u32 reserved0_7[3]; 59 u32 fpga3_clk_ctrl; /* 0x1a0 */ 60 u32 reserved0_8[8]; 61 u32 clk_621_true; /* 0x1c4 */ 62 u32 reserved1[14]; 63 u32 pss_rst_ctrl; /* 0x200 */ 64 u32 reserved2[15]; 65 u32 fpga_rst_ctrl; /* 0x240 */ 66 u32 reserved3[5]; 67 u32 reboot_status; /* 0x258 */ 68 u32 boot_mode; /* 0x25c */ 69 u32 reserved4[116]; 70 u32 trust_zone; /* 0x430 */ /* FIXME */ 71 u32 reserved5_1[63]; 72 u32 pss_idcode; /* 0x530 */ 73 u32 reserved5_2[51]; 74 u32 ddr_urgent; /* 0x600 */ 75 u32 reserved6[6]; 76 u32 ddr_urgent_sel; /* 0x61c */ 77 u32 reserved7[56]; 78 u32 mio_pin[54]; /* 0x700 - 0x7D4 */ 79 u32 reserved8[74]; 80 u32 lvl_shftr_en; /* 0x900 */ 81 u32 reserved9[3]; 82 u32 ocm_cfg; /* 0x910 */ 83 }; 84 85 #define slcr_base ((struct slcr_regs *)ZYNQ_SYS_CTRL_BASEADDR) 86 87 struct devcfg_regs { 88 u32 ctrl; /* 0x0 */ 89 u32 lock; /* 0x4 */ 90 u32 cfg; /* 0x8 */ 91 u32 int_sts; /* 0xc */ 92 u32 int_mask; /* 0x10 */ 93 u32 status; /* 0x14 */ 94 u32 dma_src_addr; /* 0x18 */ 95 u32 dma_dst_addr; /* 0x1c */ 96 u32 dma_src_len; /* 0x20 */ 97 u32 dma_dst_len; /* 0x24 */ 98 u32 rom_shadow; /* 0x28 */ 99 u32 reserved1[2]; 100 u32 unlock; /* 0x34 */ 101 u32 reserved2[18]; 102 u32 mctrl; /* 0x80 */ 103 u32 reserved3; 104 u32 write_count; /* 0x88 */ 105 u32 read_count; /* 0x8c */ 106 }; 107 108 #define devcfg_base ((struct devcfg_regs *)ZYNQ_DEV_CFG_APB_BASEADDR) 109 110 struct scu_regs { 111 u32 reserved1[16]; 112 u32 filter_start; /* 0x40 */ 113 u32 filter_end; /* 0x44 */ 114 }; 115 116 #define scu_base ((struct scu_regs *)ZYNQ_SCU_BASEADDR) 117 118 struct ddrc_regs { 119 u32 ddrc_ctrl; /* 0x0 */ 120 u32 reserved[60]; 121 u32 ecc_scrub; /* 0xF4 */ 122 }; 123 #define ddrc_base ((struct ddrc_regs *)ZYNQ_DDRC_BASEADDR) 124 125 struct efuse_reg { 126 u32 reserved1[4]; 127 u32 status; 128 u32 reserved2[3]; 129 }; 130 131 #define efuse_base ((struct efuse_reg *)ZYNQ_EFUSE_BASEADDR) 132 133 #endif /* _ASM_ARCH_HARDWARE_H */ 134