1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * PCI autoconfiguration library
4 *
5 * Author: Matt Porter <mporter@mvista.com>
6 *
7 * Copyright 2000 MontaVista Software Inc.
8 */
9
10 #include <common.h>
11 #include <dm.h>
12 #include <errno.h>
13 #include <log.h>
14 #include <pci.h>
15
16 /* the user can define CONFIG_SYS_PCI_CACHE_LINE_SIZE to avoid problems */
17 #ifndef CONFIG_SYS_PCI_CACHE_LINE_SIZE
18 #define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8
19 #endif
20
dm_pciauto_setup_device(struct udevice * dev,int bars_num,struct pci_region * mem,struct pci_region * prefetch,struct pci_region * io)21 static void dm_pciauto_setup_device(struct udevice *dev, int bars_num,
22 struct pci_region *mem,
23 struct pci_region *prefetch,
24 struct pci_region *io)
25 {
26 u32 bar_response;
27 pci_size_t bar_size;
28 u16 cmdstat = 0;
29 int bar, bar_nr = 0;
30 u8 header_type;
31 int rom_addr;
32 pci_addr_t bar_value;
33 struct pci_region *bar_res = NULL;
34 int found_mem64 = 0;
35 u16 class;
36
37 dm_pci_read_config16(dev, PCI_COMMAND, &cmdstat);
38 cmdstat = (cmdstat & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) |
39 PCI_COMMAND_MASTER;
40
41 for (bar = PCI_BASE_ADDRESS_0;
42 bar < PCI_BASE_ADDRESS_0 + (bars_num * 4); bar += 4) {
43 int ret = 0;
44
45 /* Tickle the BAR and get the response */
46 dm_pci_write_config32(dev, bar, 0xffffffff);
47 dm_pci_read_config32(dev, bar, &bar_response);
48
49 /* If BAR is not implemented (or invalid) go to the next BAR */
50 if (!bar_response || bar_response == 0xffffffff)
51 continue;
52
53 found_mem64 = 0;
54
55 /* Check the BAR type and set our address mask */
56 if (bar_response & PCI_BASE_ADDRESS_SPACE) {
57 bar_size = bar_response & PCI_BASE_ADDRESS_IO_MASK;
58 bar_size &= ~(bar_size - 1);
59
60 bar_res = io;
61
62 debug("PCI Autoconfig: BAR %d, I/O, size=0x%llx, ",
63 bar_nr, (unsigned long long)bar_size);
64 } else {
65 if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
66 PCI_BASE_ADDRESS_MEM_TYPE_64) {
67 u32 bar_response_upper;
68 u64 bar64;
69
70 dm_pci_write_config32(dev, bar + 4, 0xffffffff);
71 dm_pci_read_config32(dev, bar + 4,
72 &bar_response_upper);
73
74 bar64 = ((u64)bar_response_upper << 32) |
75 bar_response;
76
77 bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK)
78 + 1;
79 found_mem64 = 1;
80 } else {
81 bar_size = (u32)(~(bar_response &
82 PCI_BASE_ADDRESS_MEM_MASK) + 1);
83 }
84
85 if (prefetch &&
86 (bar_response & PCI_BASE_ADDRESS_MEM_PREFETCH))
87 bar_res = prefetch;
88 else
89 bar_res = mem;
90
91 debug("PCI Autoconfig: BAR %d, %s%s, size=0x%llx, ",
92 bar_nr, bar_res == prefetch ? "Prf" : "Mem",
93 found_mem64 ? "64" : "",
94 (unsigned long long)bar_size);
95 }
96
97 ret = pciauto_region_allocate(bar_res, bar_size,
98 &bar_value, found_mem64);
99 if (ret)
100 printf("PCI: Failed autoconfig bar %x\n", bar);
101
102 if (!ret) {
103 /* Write it out and update our limit */
104 dm_pci_write_config32(dev, bar, (u32)bar_value);
105
106 if (found_mem64) {
107 bar += 4;
108 #ifdef CONFIG_SYS_PCI_64BIT
109 dm_pci_write_config32(dev, bar,
110 (u32)(bar_value >> 32));
111 #else
112 /*
113 * If we are a 64-bit decoder then increment to
114 * the upper 32 bits of the bar and force it to
115 * locate in the lower 4GB of memory.
116 */
117 dm_pci_write_config32(dev, bar, 0x00000000);
118 #endif
119 }
120 }
121
122 cmdstat |= (bar_response & PCI_BASE_ADDRESS_SPACE) ?
123 PCI_COMMAND_IO : PCI_COMMAND_MEMORY;
124
125 debug("\n");
126
127 bar_nr++;
128 }
129
130 /* Configure the expansion ROM address */
131 dm_pci_read_config8(dev, PCI_HEADER_TYPE, &header_type);
132 header_type &= 0x7f;
133 if (header_type != PCI_HEADER_TYPE_CARDBUS) {
134 rom_addr = (header_type == PCI_HEADER_TYPE_NORMAL) ?
135 PCI_ROM_ADDRESS : PCI_ROM_ADDRESS1;
136 dm_pci_write_config32(dev, rom_addr, 0xfffffffe);
137 dm_pci_read_config32(dev, rom_addr, &bar_response);
138 if (bar_response) {
139 bar_size = -(bar_response & ~1);
140 debug("PCI Autoconfig: ROM, size=%#x, ",
141 (unsigned int)bar_size);
142 if (pciauto_region_allocate(mem, bar_size, &bar_value,
143 false) == 0) {
144 dm_pci_write_config32(dev, rom_addr, bar_value);
145 }
146 cmdstat |= PCI_COMMAND_MEMORY;
147 debug("\n");
148 }
149 }
150
151 /* PCI_COMMAND_IO must be set for VGA device */
152 dm_pci_read_config16(dev, PCI_CLASS_DEVICE, &class);
153 if (class == PCI_CLASS_DISPLAY_VGA)
154 cmdstat |= PCI_COMMAND_IO;
155
156 dm_pci_write_config16(dev, PCI_COMMAND, cmdstat);
157 dm_pci_write_config8(dev, PCI_CACHE_LINE_SIZE,
158 CONFIG_SYS_PCI_CACHE_LINE_SIZE);
159 dm_pci_write_config8(dev, PCI_LATENCY_TIMER, 0x80);
160 }
161
dm_pciauto_prescan_setup_bridge(struct udevice * dev,int sub_bus)162 void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus)
163 {
164 struct pci_region *pci_mem;
165 struct pci_region *pci_prefetch;
166 struct pci_region *pci_io;
167 u16 cmdstat, prefechable_64;
168 struct udevice *ctlr = pci_get_controller(dev);
169 struct pci_controller *ctlr_hose = dev_get_uclass_priv(ctlr);
170
171 pci_mem = ctlr_hose->pci_mem;
172 pci_prefetch = ctlr_hose->pci_prefetch;
173 pci_io = ctlr_hose->pci_io;
174
175 dm_pci_read_config16(dev, PCI_COMMAND, &cmdstat);
176 dm_pci_read_config16(dev, PCI_PREF_MEMORY_BASE, &prefechable_64);
177 prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
178
179 /* Configure bus number registers */
180 dm_pci_write_config8(dev, PCI_PRIMARY_BUS,
181 PCI_BUS(dm_pci_get_bdf(dev)) - dev_seq(ctlr));
182 dm_pci_write_config8(dev, PCI_SECONDARY_BUS, sub_bus - dev_seq(ctlr));
183 dm_pci_write_config8(dev, PCI_SUBORDINATE_BUS, 0xff);
184
185 if (pci_mem) {
186 /* Round memory allocator to 1MB boundary */
187 pciauto_region_align(pci_mem, 0x100000);
188
189 /*
190 * Set up memory and I/O filter limits, assume 32-bit
191 * I/O space
192 */
193 dm_pci_write_config16(dev, PCI_MEMORY_BASE,
194 (pci_mem->bus_lower & 0xfff00000) >> 16);
195
196 cmdstat |= PCI_COMMAND_MEMORY;
197 }
198
199 if (pci_prefetch) {
200 /* Round memory allocator to 1MB boundary */
201 pciauto_region_align(pci_prefetch, 0x100000);
202
203 /*
204 * Set up memory and I/O filter limits, assume 32-bit
205 * I/O space
206 */
207 dm_pci_write_config16(dev, PCI_PREF_MEMORY_BASE,
208 (pci_prefetch->bus_lower & 0xfff00000) >> 16);
209 if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
210 #ifdef CONFIG_SYS_PCI_64BIT
211 dm_pci_write_config32(dev, PCI_PREF_BASE_UPPER32,
212 pci_prefetch->bus_lower >> 32);
213 #else
214 dm_pci_write_config32(dev, PCI_PREF_BASE_UPPER32, 0x0);
215 #endif
216
217 cmdstat |= PCI_COMMAND_MEMORY;
218 } else {
219 /* We don't support prefetchable memory for now, so disable */
220 dm_pci_write_config16(dev, PCI_PREF_MEMORY_BASE, 0x1000);
221 dm_pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT, 0x0);
222 if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) {
223 dm_pci_write_config16(dev, PCI_PREF_BASE_UPPER32, 0x0);
224 dm_pci_write_config16(dev, PCI_PREF_LIMIT_UPPER32, 0x0);
225 }
226 }
227
228 if (pci_io) {
229 /* Round I/O allocator to 4KB boundary */
230 pciauto_region_align(pci_io, 0x1000);
231
232 dm_pci_write_config8(dev, PCI_IO_BASE,
233 (pci_io->bus_lower & 0x0000f000) >> 8);
234 dm_pci_write_config16(dev, PCI_IO_BASE_UPPER16,
235 (pci_io->bus_lower & 0xffff0000) >> 16);
236
237 cmdstat |= PCI_COMMAND_IO;
238 }
239
240 /* Enable memory and I/O accesses, enable bus master */
241 dm_pci_write_config16(dev, PCI_COMMAND, cmdstat | PCI_COMMAND_MASTER);
242 }
243
dm_pciauto_postscan_setup_bridge(struct udevice * dev,int sub_bus)244 void dm_pciauto_postscan_setup_bridge(struct udevice *dev, int sub_bus)
245 {
246 struct pci_region *pci_mem;
247 struct pci_region *pci_prefetch;
248 struct pci_region *pci_io;
249 struct udevice *ctlr = pci_get_controller(dev);
250 struct pci_controller *ctlr_hose = dev_get_uclass_priv(ctlr);
251
252 pci_mem = ctlr_hose->pci_mem;
253 pci_prefetch = ctlr_hose->pci_prefetch;
254 pci_io = ctlr_hose->pci_io;
255
256 /* Configure bus number registers */
257 dm_pci_write_config8(dev, PCI_SUBORDINATE_BUS, sub_bus - dev_seq(ctlr));
258
259 if (pci_mem) {
260 /* Round memory allocator to 1MB boundary */
261 pciauto_region_align(pci_mem, 0x100000);
262
263 dm_pci_write_config16(dev, PCI_MEMORY_LIMIT,
264 (pci_mem->bus_lower - 1) >> 16);
265 }
266
267 if (pci_prefetch) {
268 u16 prefechable_64;
269
270 dm_pci_read_config16(dev, PCI_PREF_MEMORY_LIMIT,
271 &prefechable_64);
272 prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
273
274 /* Round memory allocator to 1MB boundary */
275 pciauto_region_align(pci_prefetch, 0x100000);
276
277 dm_pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT,
278 (pci_prefetch->bus_lower - 1) >> 16);
279 if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
280 #ifdef CONFIG_SYS_PCI_64BIT
281 dm_pci_write_config32(dev, PCI_PREF_LIMIT_UPPER32,
282 (pci_prefetch->bus_lower - 1) >> 32);
283 #else
284 dm_pci_write_config32(dev, PCI_PREF_LIMIT_UPPER32, 0x0);
285 #endif
286 }
287
288 if (pci_io) {
289 /* Round I/O allocator to 4KB boundary */
290 pciauto_region_align(pci_io, 0x1000);
291
292 dm_pci_write_config8(dev, PCI_IO_LIMIT,
293 ((pci_io->bus_lower - 1) & 0x0000f000) >> 8);
294 dm_pci_write_config16(dev, PCI_IO_LIMIT_UPPER16,
295 ((pci_io->bus_lower - 1) & 0xffff0000) >> 16);
296 }
297 }
298
299 /*
300 * HJF: Changed this to return int. I think this is required
301 * to get the correct result when scanning bridges
302 */
dm_pciauto_config_device(struct udevice * dev)303 int dm_pciauto_config_device(struct udevice *dev)
304 {
305 struct pci_region *pci_mem;
306 struct pci_region *pci_prefetch;
307 struct pci_region *pci_io;
308 unsigned int sub_bus = PCI_BUS(dm_pci_get_bdf(dev));
309 unsigned short class;
310 struct udevice *ctlr = pci_get_controller(dev);
311 struct pci_controller *ctlr_hose = dev_get_uclass_priv(ctlr);
312 int ret;
313
314 pci_mem = ctlr_hose->pci_mem;
315 pci_prefetch = ctlr_hose->pci_prefetch;
316 pci_io = ctlr_hose->pci_io;
317
318 dm_pci_read_config16(dev, PCI_CLASS_DEVICE, &class);
319
320 switch (class) {
321 case PCI_CLASS_BRIDGE_PCI:
322 debug("PCI Autoconfig: Found P2P bridge, device %d\n",
323 PCI_DEV(dm_pci_get_bdf(dev)));
324
325 dm_pciauto_setup_device(dev, 2, pci_mem, pci_prefetch, pci_io);
326
327 ret = dm_pci_hose_probe_bus(dev);
328 if (ret < 0)
329 return log_msg_ret("probe", ret);
330 sub_bus = ret;
331 break;
332
333 case PCI_CLASS_BRIDGE_CARDBUS:
334 /*
335 * just do a minimal setup of the bridge,
336 * let the OS take care of the rest
337 */
338 dm_pciauto_setup_device(dev, 0, pci_mem, pci_prefetch, pci_io);
339
340 debug("PCI Autoconfig: Found P2CardBus bridge, device %d\n",
341 PCI_DEV(dm_pci_get_bdf(dev)));
342
343 break;
344
345 #if defined(CONFIG_PCIAUTO_SKIP_HOST_BRIDGE)
346 case PCI_CLASS_BRIDGE_OTHER:
347 debug("PCI Autoconfig: Skipping bridge device %d\n",
348 PCI_DEV(dm_pci_get_bdf(dev)));
349 break;
350 #endif
351 #if defined(CONFIG_ARCH_MPC834X) && !defined(CONFIG_TARGET_VME8349) && \
352 !defined(CONFIG_TARGET_CADDY2)
353 case PCI_CLASS_BRIDGE_OTHER:
354 /*
355 * The host/PCI bridge 1 seems broken in 8349 - it presents
356 * itself as 'PCI_CLASS_BRIDGE_OTHER' and appears as an _agent_
357 * device claiming resources io/mem/irq.. we only allow for
358 * the PIMMR window to be allocated (BAR0 - 1MB size)
359 */
360 debug("PCI Autoconfig: Broken bridge found, only minimal config\n");
361 dm_pciauto_setup_device(dev, 0, hose->pci_mem,
362 hose->pci_prefetch, hose->pci_io);
363 break;
364 #endif
365
366 case PCI_CLASS_PROCESSOR_POWERPC: /* an agent or end-point */
367 debug("PCI AutoConfig: Found PowerPC device\n");
368 /* fall through */
369
370 default:
371 dm_pciauto_setup_device(dev, 6, pci_mem, pci_prefetch, pci_io);
372 break;
373 }
374
375 return sub_bus;
376 }
377