1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * (C) Copyright 2013-2015
4  * NVIDIA Corporation <www.nvidia.com>
5  */
6 
7 #ifndef _TEGRA210_AHB_H_
8 #define _TEGRA210_AHB_H_
9 
10 struct ahb_ctlr {
11 	u32 reserved0;			/* 00h */
12 	u32 arbitration_disable;	/* _ARBITRATION_DISABLE_0,	04h */
13 	u32 arbitration_priority_ctrl;	/* _ARBITRATION_PRIORITY_CTRL_0,08h */
14 	u32 arbitration_usr_protect;	/* _ARBITRATION_USR_PROTECT_0,	0ch */
15 	u32 gizmo_ahb_mem;		/* _GIZMO_AHB_MEM_0,		10h */
16 	u32 gizmo_apb_dma;		/* _GIZMO_APB_DMA_0,		14h */
17 	u32 reserved6[2];		/* 18h, 1ch */
18 	u32 gizmo_usb;			/* _GIZMO_USB_0,		20h */
19 	u32 gizmo_ahb_xbar_bridge;	/* _GIZMO_AHB_XBAR_BRIDGE_0,	24h */
20 	u32 gizmo_cpu_ahb_bridge;	/* _GIZMO_CPU_AHB_BRIDGE_0,	28h */
21 	u32 gizmo_cop_ahb_bridge;	/* _GIZMO_COP_AHB_BRIDGE_0,	2ch */
22 	u32 gizmo_xbar_apb_ctlr;	/* _GIZMO_XBAR_APB_CTLR_0,	30h */
23 	u32 gizmo_vcp_ahb_bridge;	/* _GIZMO_VCP_AHB_BRIDGE_0,	34h */
24 	u32 reserved13[2];		/* 38h, 3ch */
25 	u32 gizmo_nand;			/* _GIZMO_NAND_0,		40h */
26 	u32 reserved15;			/* 44h */
27 	u32 gizmo_sdmmc4;		/* _GIZMO_SDMMC4_0,		48h */
28 	u32 reserved17;			/* 4ch */
29 	u32 gizmo_se;			/* _GIZMO_SE_0,			50h */
30 	u32 gizmo_tzram;		/* _GIZMO_TZRAM_0,		54h */
31 	u32 reserved20[3];		/* 58h, 5ch, 60h */
32 	u32 gizmo_bsev;			/* _GIZMO_BSEV_0,		64h */
33 	u32 reserved22[3];		/* 68h, 6ch, 70h */
34 	u32 gizmo_bsea;			/* _GIZMO_BSEA_0,		74h */
35 	u32 gizmo_nor;			/* _GIZMO_NOR_0,		78h */
36 	u32 gizmo_usb2;			/* _GIZMO_USB2_0,		7ch */
37 	u32 gizmo_usb3;			/* _GIZMO_USB3_0,		80h */
38 	u32 gizmo_sdmmc1;		/* _GIZMO_SDMMC1_0,		84h */
39 	u32 gizmo_sdmmc2;		/* _GIZMO_SDMMC2_0,		88h */
40 	u32 gizmo_sdmmc3;		/* _GIZMO_SDMMC3_0,		8ch */
41 	u32 reserved30[13];		/* 90h ~ c0h */
42 	u32 ahb_wrq_empty;		/* _AHB_WRQ_EMPTY_0,		c4h */
43 	u32 reserved32[5];		/* c8h ~ d8h */
44 	u32 ahb_mem_prefetch_cfg_x;	/* _AHB_MEM_PREFETCH_CFG_X_0,	dch */
45 	u32 arbitration_xbar_ctrl;	/* _ARBITRATION_XBAR_CTRL_0,	e0h */
46 	u32 ahb_mem_prefetch_cfg3;	/* _AHB_MEM_PREFETCH_CFG3_0,	e4h */
47 	u32 ahb_mem_prefetch_cfg4;	/* _AHB_MEM_PREFETCH_CFG3_0,	e8h */
48 	u32 avp_ppcs_rd_coh_status;	/* _AVP_PPCS_RD_COH_STATUS_0,	ech */
49 	u32 ahb_mem_prefetch_cfg1;	/* _AHB_MEM_PREFETCH_CFG1_0,	f0h */
50 	u32 ahb_mem_prefetch_cfg2;	/* _AHB_MEM_PREFETCH_CFG2_0,	f4h */
51 	u32 ahbslvmem_status;		/* _AHBSLVMEM_STATUS_0, f8h */
52 	/* _ARBITRATION_AHB_MEM_WRQUE_MST_ID_0, fch */
53 	u32 arbitration_ahb_mem_wrque_mst_id;
54 	u32 arbitration_cpu_abort_addr;	/* _ARBITRATION_CPU_ABORT_ADDR_0,100h */
55 	u32 arbitration_cpu_abort_info;	/* _ARBITRATION_CPU_ABORT_INFO_0,104h */
56 	u32 arbitration_cop_abort_addr;	/* _ARBITRATION_COP_ABORT_ADDR_0,108h */
57 	u32 arbitration_cop_abort_info;	/* _ARBITRATION_COP_ABORT_INFO_0,10ch */
58 	u32 reserved46[4];		/* 110h ~ 11ch */
59 	u32 avpc_mccif_fifoctrl;	/* _AVPC_MCCIF_FIFOCTRL_0,	120h */
60 	u32 timeout_wcoal_avpc;		/* _TIMEOUT_WCOAL_AVPC_0,	124h */
61 	u32 mpcorelp_mccif_fifoctrl;	/* _MPCORELP_MCCIF_FIFOCTRL_0,	128h */
62 	u32 mpcore_mccif_fifoctrl;	/* _MPCORE_MCCIF_FIFOCTRL_0,	12ch */
63 	u32 axicif_fastsync_ctrl;	/* AXICIF_FASTSYNC_CTRL_0,	130h */
64 	u32 axicif_fastsync_statistics;	/* _AXICIF_FASTSYNC_STATISTICS_0,134h */
65 	/* _AXICIF_FASTSYNC0_CPUCLK_TO_MCCLK_0,	138h */
66 	u32 axicif_fastsync0_cpuclk_to_mcclk;
67 	/* _AXICIF_FASTSYNC1_CPUCLK_TO_MCCLK_0, 13ch */
68 	u32 axicif_fastsync1_cpuclk_to_mcclk;
69 	/* _AXICIF_FASTSYNC2_CPUCLK_TO_MCCLK_0, 140h */
70 	u32 axicif_fastsync2_cpuclk_to_mcclk;
71 	/* _AXICIF_FASTSYNC0_MCCLK_TO_CPUCLK_0, 144h */
72 	u32 axicif_fastsync0_mcclk_to_cpuclk;
73 	/* _AXICIF_FASTSYNC1_MCCLK_TO_CPUCLK_0, 148h */
74 	u32 axicif_fastsync1_mcclk_to_cpuclk;
75 	/* _AXICIF_FASTSYNC2_MCCLK_TO_CPUCLK_0, 14ch */
76 	u32 axicif_fastsync2_mcclk_to_cpuclk;
77 };
78 
79 #define PPSB_STOPCLK_ENABLE	(1 << 2)
80 
81 #define GIZ_ENABLE_SPLIT	(1 << 0)
82 #define GIZ_ENB_FAST_REARB	(1 << 2)
83 #define GIZ_DONT_SPLIT_AHB_WR	(1 << 7)
84 
85 #define GIZ_USB_IMMEDIATE	(1 << 18)
86 
87 /* AHB_ARBITRATION_XBAR_CTRL_0 0xe0 */
88 #define ARBITRATION_XBAR_CTRL_PPSB_ENABLE	(1 << 2)
89 
90 #endif	/* _TEGRA210_AHB_H_ */
91