1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2012 Freescale Semiconductor, Inc.
4 */
5
6 #include <common.h>
7 #include <log.h>
8 #include <asm/fsl_serdes.h>
9 #include <asm/immap_85xx.h>
10 #include <asm/io.h>
11 #include <asm/processor.h>
12 #include <asm/fsl_law.h>
13 #include <linux/delay.h>
14 #include <linux/errno.h>
15 #include <fsl_errata.h>
16 #include "fsl_corenet2_serdes.h"
17
18 #ifdef CONFIG_SYS_FSL_SRDS_1
19 static u8 serdes1_prtcl_map[SERDES_PRCTL_COUNT];
20 #endif
21 #ifdef CONFIG_SYS_FSL_SRDS_2
22 static u8 serdes2_prtcl_map[SERDES_PRCTL_COUNT];
23 #endif
24 #ifdef CONFIG_SYS_FSL_SRDS_3
25 static u8 serdes3_prtcl_map[SERDES_PRCTL_COUNT];
26 #endif
27 #ifdef CONFIG_SYS_FSL_SRDS_4
28 static u8 serdes4_prtcl_map[SERDES_PRCTL_COUNT];
29 #endif
30
31 #ifdef DEBUG
32 static const char *serdes_prtcl_str[] = {
33 [NONE] = "NA",
34 [PCIE1] = "PCIE1",
35 [PCIE2] = "PCIE2",
36 [PCIE3] = "PCIE3",
37 [PCIE4] = "PCIE4",
38 [SATA1] = "SATA1",
39 [SATA2] = "SATA2",
40 [SRIO1] = "SRIO1",
41 [SRIO2] = "SRIO2",
42 [SGMII_FM1_DTSEC1] = "SGMII_FM1_DTSEC1",
43 [SGMII_FM1_DTSEC2] = "SGMII_FM1_DTSEC2",
44 [SGMII_FM1_DTSEC3] = "SGMII_FM1_DTSEC3",
45 [SGMII_FM1_DTSEC4] = "SGMII_FM1_DTSEC4",
46 [SGMII_FM1_DTSEC5] = "SGMII_FM1_DTSEC5",
47 [SGMII_FM1_DTSEC6] = "SGMII_FM1_DTSEC6",
48 [SGMII_FM2_DTSEC1] = "SGMII_FM2_DTSEC1",
49 [SGMII_FM2_DTSEC2] = "SGMII_FM2_DTSEC2",
50 [SGMII_FM2_DTSEC3] = "SGMII_FM2_DTSEC3",
51 [SGMII_FM2_DTSEC4] = "SGMII_FM2_DTSEC4",
52 [XAUI_FM1] = "XAUI_FM1",
53 [XAUI_FM2] = "XAUI_FM2",
54 [AURORA] = "DEBUG",
55 [CPRI1] = "CPRI1",
56 [CPRI2] = "CPRI2",
57 [CPRI3] = "CPRI3",
58 [CPRI4] = "CPRI4",
59 [CPRI5] = "CPRI5",
60 [CPRI6] = "CPRI6",
61 [CPRI7] = "CPRI7",
62 [CPRI8] = "CPRI8",
63 [XAUI_FM1_MAC9] = "XAUI_FM1_MAC9",
64 [XAUI_FM1_MAC10] = "XAUI_FM1_MAC10",
65 [XAUI_FM2_MAC9] = "XAUI_FM2_MAC9",
66 [XAUI_FM2_MAC10] = "XAUI_FM2_MAC10",
67 [HIGIG_FM1_MAC9] = "HiGig_FM1_MAC9",
68 [HIGIG_FM1_MAC10] = "HiGig_FM1_MAC10",
69 [HIGIG_FM2_MAC9] = "HiGig_FM2_MAC9",
70 [HIGIG_FM2_MAC10] = "HiGig_FM2_MAC10",
71 [QSGMII_FM1_A] = "QSGMII_FM1_A",
72 [QSGMII_FM1_B] = "QSGMII_FM1_B",
73 [QSGMII_FM2_A] = "QSGMII_FM2_A",
74 [QSGMII_FM2_B] = "QSGMII_FM2_B",
75 [XFI_FM1_MAC9] = "XFI_FM1_MAC9",
76 [XFI_FM1_MAC10] = "XFI_FM1_MAC10",
77 [XFI_FM2_MAC9] = "XFI_FM2_MAC9",
78 [XFI_FM2_MAC10] = "XFI_FM2_MAC10",
79 [INTERLAKEN] = "INTERLAKEN",
80 [QSGMII_SW1_A] = "QSGMII_SW1_A",
81 [QSGMII_SW1_B] = "QSGMII_SW1_B",
82 [SGMII_SW1_MAC1] = "SGMII_SW1_MAC1",
83 [SGMII_SW1_MAC2] = "SGMII_SW1_MAC2",
84 [SGMII_SW1_MAC3] = "SGMII_SW1_MAC3",
85 [SGMII_SW1_MAC4] = "SGMII_SW1_MAC4",
86 [SGMII_SW1_MAC5] = "SGMII_SW1_MAC5",
87 [SGMII_SW1_MAC6] = "SGMII_SW1_MAC6",
88 };
89 #endif
90
is_serdes_configured(enum srds_prtcl device)91 int is_serdes_configured(enum srds_prtcl device)
92 {
93 int ret = 0;
94
95 #ifdef CONFIG_SYS_FSL_SRDS_1
96 if (!serdes1_prtcl_map[NONE])
97 fsl_serdes_init();
98
99 ret |= serdes1_prtcl_map[device];
100 #endif
101 #ifdef CONFIG_SYS_FSL_SRDS_2
102 if (!serdes2_prtcl_map[NONE])
103 fsl_serdes_init();
104
105 ret |= serdes2_prtcl_map[device];
106 #endif
107 #ifdef CONFIG_SYS_FSL_SRDS_3
108 if (!serdes3_prtcl_map[NONE])
109 fsl_serdes_init();
110
111 ret |= serdes3_prtcl_map[device];
112 #endif
113 #ifdef CONFIG_SYS_FSL_SRDS_4
114 if (!serdes4_prtcl_map[NONE])
115 fsl_serdes_init();
116
117 ret |= serdes4_prtcl_map[device];
118 #endif
119
120 return !!ret;
121 }
122
serdes_get_first_lane(u32 sd,enum srds_prtcl device)123 int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
124 {
125 const ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
126 u32 cfg = in_be32(&gur->rcwsr[4]);
127 int i;
128
129 switch (sd) {
130 #ifdef CONFIG_SYS_FSL_SRDS_1
131 case FSL_SRDS_1:
132 cfg &= FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
133 cfg >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
134 break;
135 #endif
136 #ifdef CONFIG_SYS_FSL_SRDS_2
137 case FSL_SRDS_2:
138 cfg &= FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
139 cfg >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
140 break;
141 #endif
142 #ifdef CONFIG_SYS_FSL_SRDS_3
143 case FSL_SRDS_3:
144 cfg &= FSL_CORENET2_RCWSR4_SRDS3_PRTCL;
145 cfg >>= FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT;
146 break;
147 #endif
148 #ifdef CONFIG_SYS_FSL_SRDS_4
149 case FSL_SRDS_4:
150 cfg &= FSL_CORENET2_RCWSR4_SRDS4_PRTCL;
151 cfg >>= FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT;
152 break;
153 #endif
154 default:
155 printf("invalid SerDes%d\n", sd);
156 break;
157 }
158 /* Is serdes enabled at all? */
159 if (unlikely(cfg == 0))
160 return -ENODEV;
161
162 for (i = 0; i < SRDS_MAX_LANES; i++) {
163 if (serdes_get_prtcl(sd, cfg, i) == device)
164 return i;
165 }
166
167 return -ENODEV;
168 }
169
170 #define BC3_SHIFT 9
171 #define DC3_SHIFT 6
172 #define FC3_SHIFT 0
173 #define BC2_SHIFT 19
174 #define DC2_SHIFT 16
175 #define FC2_SHIFT 10
176 #define BC1_SHIFT 29
177 #define DC1_SHIFT 26
178 #define FC1_SHIFT 20
179 #define BC_MASK 0x1
180 #define DC_MASK 0x7
181 #define FC_MASK 0x3F
182
183 #define FUSE_VAL_MASK 0x00000003
184 #define FUSE_VAL_SHIFT 30
185 #define CR0_DCBIAS_SHIFT 5
186 #define CR1_FCAP_SHIFT 15
187 #define CR1_BCAP_SHIFT 29
188 #define FCAP_MASK 0x001F8000
189 #define BCAP_MASK 0x20000000
190 #define BCAP_OVD_MASK 0x10000000
191 #define BYP_CAL_MASK 0x02000000
192
serdes_init(u32 sd,u32 sd_addr,u32 sd_prctl_mask,u32 sd_prctl_shift,u8 serdes_prtcl_map[SERDES_PRCTL_COUNT])193 void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift,
194 u8 serdes_prtcl_map[SERDES_PRCTL_COUNT])
195 {
196 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
197 u32 cfg;
198 int lane;
199
200 if (serdes_prtcl_map[NONE])
201 return;
202
203 memset(serdes_prtcl_map, 0, sizeof(u8) * SERDES_PRCTL_COUNT);
204 #ifdef CONFIG_SYS_FSL_ERRATUM_A007186
205 struct ccsr_sfp_regs __iomem *sfp_regs =
206 (struct ccsr_sfp_regs __iomem *)(CONFIG_SYS_SFP_ADDR);
207 u32 pll_num, pll_status, bc, dc, fc, pll_cr_upd, pll_cr0, pll_cr1;
208 u32 bc_status, fc_status, dc_status, pll_sr2;
209 serdes_corenet_t __iomem *srds_regs = (void *)sd_addr;
210 u32 sfp_spfr0, sel;
211 #endif
212
213 cfg = in_be32(&gur->rcwsr[4]) & sd_prctl_mask;
214
215 /* Erratum A-007186
216 * Freescale Scratch Pad Fuse Register n (SFP_FSPFR0)
217 * The workaround requires factory pre-set SerDes calibration values to be
218 * read from a fuse block(Freescale Scratch Pad Fuse Register SFP_FSPFR0)
219 * These values have been shown to work across the
220 * entire temperature range for all SerDes. These values are then written into
221 * the SerDes registers to calibrate the SerDes PLL.
222 *
223 * This workaround for the protocols and rates that only have the Ring VCO.
224 */
225 #ifdef CONFIG_SYS_FSL_ERRATUM_A007186
226 sfp_spfr0 = in_be32(&sfp_regs->fsl_spfr0);
227 debug("A007186: sfp_spfr0= %x\n", sfp_spfr0);
228
229 sel = (sfp_spfr0 >> FUSE_VAL_SHIFT) & FUSE_VAL_MASK;
230
231 if (has_erratum_a007186() && (sel == 0x01 || sel == 0x02)) {
232 for (pll_num = 0; pll_num < SRDS_MAX_BANK; pll_num++) {
233 pll_status = in_be32(&srds_regs->bank[pll_num].pllcr0);
234 debug("A007186: pll_num=%x pllcr0=%x\n",
235 pll_num, pll_status);
236 /* STEP 1 */
237 /* Read factory pre-set SerDes calibration values
238 * from fuse block(SFP scratch register-sfp_spfr0)
239 */
240 switch (pll_status & SRDS_PLLCR0_FRATE_SEL_MASK) {
241 case SRDS_PLLCR0_FRATE_SEL_3_0:
242 case SRDS_PLLCR0_FRATE_SEL_3_072:
243 debug("A007186: 3.0/3.072 protocol rate\n");
244 bc = (sfp_spfr0 >> BC1_SHIFT) & BC_MASK;
245 dc = (sfp_spfr0 >> DC1_SHIFT) & DC_MASK;
246 fc = (sfp_spfr0 >> FC1_SHIFT) & FC_MASK;
247 break;
248 case SRDS_PLLCR0_FRATE_SEL_3_125:
249 debug("A007186: 3.125 protocol rate\n");
250 bc = (sfp_spfr0 >> BC2_SHIFT) & BC_MASK;
251 dc = (sfp_spfr0 >> DC2_SHIFT) & DC_MASK;
252 fc = (sfp_spfr0 >> FC2_SHIFT) & FC_MASK;
253 break;
254 case SRDS_PLLCR0_FRATE_SEL_3_75:
255 debug("A007186: 3.75 protocol rate\n");
256 bc = (sfp_spfr0 >> BC1_SHIFT) & BC_MASK;
257 dc = (sfp_spfr0 >> DC1_SHIFT) & DC_MASK;
258 fc = (sfp_spfr0 >> FC1_SHIFT) & FC_MASK;
259 break;
260 default:
261 continue;
262 }
263
264 /* STEP 2 */
265 /* Write SRDSxPLLnCR1[11:16] = FC
266 * Write SRDSxPLLnCR1[2] = BC
267 */
268 pll_cr1 = in_be32(&srds_regs->bank[pll_num].pllcr1);
269 pll_cr_upd = (((bc << CR1_BCAP_SHIFT) & BCAP_MASK) |
270 ((fc << CR1_FCAP_SHIFT) & FCAP_MASK));
271 out_be32(&srds_regs->bank[pll_num].pllcr1,
272 (pll_cr_upd | pll_cr1));
273 debug("A007186: pll_num=%x Updated PLLCR1=%x\n",
274 pll_num, (pll_cr_upd | pll_cr1));
275 /* Write SRDSxPLLnCR0[24:26] = DC
276 */
277 pll_cr0 = in_be32(&srds_regs->bank[pll_num].pllcr0);
278 out_be32(&srds_regs->bank[pll_num].pllcr0,
279 pll_cr0 | (dc << CR0_DCBIAS_SHIFT));
280 debug("A007186: pll_num=%x, Updated PLLCR0=%x\n",
281 pll_num, (pll_cr0 | (dc << CR0_DCBIAS_SHIFT)));
282 /* Write SRDSxPLLnCR1[3] = 1
283 * Write SRDSxPLLnCR1[6] = 1
284 */
285 pll_cr1 = in_be32(&srds_regs->bank[pll_num].pllcr1);
286 pll_cr_upd = (BCAP_OVD_MASK | BYP_CAL_MASK);
287 out_be32(&srds_regs->bank[pll_num].pllcr1,
288 (pll_cr_upd | pll_cr1));
289 debug("A007186: pll_num=%x Updated PLLCR1=%x\n",
290 pll_num, (pll_cr_upd | pll_cr1));
291
292 /* STEP 3 */
293 /* Read the status Registers */
294 /* Verify SRDSxPLLnSR2[8] = BC */
295 pll_sr2 = in_be32(&srds_regs->bank[pll_num].pllsr2);
296 debug("A007186: pll_num=%x pllsr2=%x\n",
297 pll_num, pll_sr2);
298 bc_status = (pll_sr2 >> 23) & BC_MASK;
299 if (bc_status != bc)
300 debug("BC mismatch\n");
301 fc_status = (pll_sr2 >> 16) & FC_MASK;
302 if (fc_status != fc)
303 debug("FC mismatch\n");
304 pll_cr0 = in_be32(&srds_regs->bank[pll_num].pllcr0);
305 out_be32(&srds_regs->bank[pll_num].pllcr0, pll_cr0 |
306 0x02000000);
307 pll_sr2 = in_be32(&srds_regs->bank[pll_num].pllsr2);
308 dc_status = (pll_sr2 >> 17) & DC_MASK;
309 if (dc_status != dc)
310 debug("DC mismatch\n");
311 pll_cr0 = in_be32(&srds_regs->bank[pll_num].pllcr0);
312 out_be32(&srds_regs->bank[pll_num].pllcr0, pll_cr0 &
313 0xfdffffff);
314
315 /* STEP 4 */
316 /* Wait 750us to verify the PLL is locked
317 * by checking SRDSxPLLnCR0[8] = 1.
318 */
319 udelay(750);
320 pll_status = in_be32(&srds_regs->bank[pll_num].pllcr0);
321 debug("A007186: pll_num=%x pllcr0=%x\n",
322 pll_num, pll_status);
323
324 if ((pll_status & SRDS_PLLCR0_PLL_LCK) == 0)
325 printf("A007186 Serdes PLL not locked\n");
326 else
327 debug("A007186 Serdes PLL locked\n");
328 }
329 }
330 #endif
331
332 cfg >>= sd_prctl_shift;
333 printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg);
334 if (!is_serdes_prtcl_valid(sd, cfg))
335 printf("SERDES%d[PRTCL] = 0x%x is not valid\n", sd + 1, cfg);
336
337 for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
338 enum srds_prtcl lane_prtcl = serdes_get_prtcl(sd, cfg, lane);
339 if (unlikely(lane_prtcl >= SERDES_PRCTL_COUNT))
340 debug("Unknown SerDes lane protocol %d\n", lane_prtcl);
341 else
342 serdes_prtcl_map[lane_prtcl] = 1;
343 }
344
345 /* Set the first element to indicate serdes has been initialized */
346 serdes_prtcl_map[NONE] = 1;
347 }
348
fsl_serdes_init(void)349 void fsl_serdes_init(void)
350 {
351
352 #ifdef CONFIG_SYS_FSL_SRDS_1
353 serdes_init(FSL_SRDS_1,
354 CONFIG_SYS_FSL_CORENET_SERDES_ADDR,
355 FSL_CORENET2_RCWSR4_SRDS1_PRTCL,
356 FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT,
357 serdes1_prtcl_map);
358 #endif
359 #ifdef CONFIG_SYS_FSL_SRDS_2
360 serdes_init(FSL_SRDS_2,
361 CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_2 * 0x1000,
362 FSL_CORENET2_RCWSR4_SRDS2_PRTCL,
363 FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT,
364 serdes2_prtcl_map);
365 #endif
366 #ifdef CONFIG_SYS_FSL_SRDS_3
367 serdes_init(FSL_SRDS_3,
368 CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_3 * 0x1000,
369 FSL_CORENET2_RCWSR4_SRDS3_PRTCL,
370 FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT,
371 serdes3_prtcl_map);
372 #endif
373 #ifdef CONFIG_SYS_FSL_SRDS_4
374 serdes_init(FSL_SRDS_4,
375 CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_4 * 0x1000,
376 FSL_CORENET2_RCWSR4_SRDS4_PRTCL,
377 FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT,
378 serdes4_prtcl_map);
379 #endif
380
381 }
382
serdes_clock_to_string(u32 clock)383 const char *serdes_clock_to_string(u32 clock)
384 {
385 switch (clock) {
386 case SRDS_PLLCR0_RFCK_SEL_100:
387 return "100";
388 case SRDS_PLLCR0_RFCK_SEL_125:
389 return "125";
390 case SRDS_PLLCR0_RFCK_SEL_156_25:
391 return "156.25";
392 case SRDS_PLLCR0_RFCK_SEL_161_13:
393 return "161.1328123";
394 default:
395 #if defined(CONFIG_TARGET_T4240QDS) || defined(CONFIG_TARGET_T4160QDS)
396 return "???";
397 #else
398 return "122.88";
399 #endif
400 }
401 }
402
403