1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * logicore_dp_tx.c
4 *
5 * Driver for XILINX LogiCore DisplayPort v6.1 TX (Source)
6 * based on Xilinx dp_v3_1 driver sources, updated to dp_v4_0
7 *
8 * (C) Copyright 2016
9 * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
10 */
11
12 #include <common.h>
13 #include <clk.h>
14 #include <display.h>
15 #include <dm.h>
16 #include <errno.h>
17 #include <linux/delay.h>
18
19 #include "axi.h"
20 #include "logicore_dp_dpcd.h"
21 #include "logicore_dp_tx.h"
22 #include "logicore_dp_tx_regif.h"
23
24 /* Default AXI clock frequency value */
25 #define S_AXI_CLK_DEFAULT 100000000
26
27 /* Default DP phy clock value */
28 #define PHY_CLOCK_SELECT_DEFAULT PHY_CLOCK_SELECT_540GBPS
29
30 /* The maximum voltage swing level is 3 */
31 #define MAXIMUM_VS_LEVEL 3
32 /* The maximum pre-emphasis level is 3 */
33 #define MAXIMUM_PE_LEVEL 3
34
35 /* Error out if an AUX request yields a defer reply more than 50 times */
36 #define AUX_MAX_DEFER_COUNT 50
37 /* Error out if an AUX request times out more than 50 times awaiting a reply */
38 #define AUX_MAX_TIMEOUT_COUNT 50
39 /* Error out if checking for a connected device times out more than 50 times */
40 #define IS_CONNECTED_MAX_TIMEOUT_COUNT 50
41
42 /**
43 * enum link_training_states - States for link training state machine
44 * @TS_CLOCK_RECOVERY: State for clock recovery
45 * @TS_CHANNEL_EQUALIZATION: State for channel equalization
46 * @TS_ADJUST_LINK_RATE: State where link rate is reduced in reaction to
47 * failed link training
48 * @TS_ADJUST_LANE_COUNT: State where lane count is reduced in reaction to
49 * failed link training
50 * @TS_FAILURE: State of link training failure
51 * @TS_SUCCESS:: State for successfully completed link training
52 */
53 enum link_training_states {
54 TS_CLOCK_RECOVERY,
55 TS_CHANNEL_EQUALIZATION,
56 TS_ADJUST_LINK_RATE,
57 TS_ADJUST_LANE_COUNT,
58 TS_FAILURE,
59 TS_SUCCESS
60 };
61
62 /**
63 * struct aux_transaction - Description of an AUX channel transaction
64 * @cmd_code: Command code of the transaction
65 * @num_bytes: The number of bytes in the transaction's payload data
66 * @address: The DPCD address of the transaction
67 * @data: Payload data of the AUX channel transaction
68 */
69 struct aux_transaction {
70 u16 cmd_code;
71 u8 num_bytes;
72 u32 address;
73 u8 *data;
74 };
75
76 /**
77 * struct main_stream_attributes - Main stream attributes
78 * @pixel_clock_hz: Pixel clock of the stream (in Hz)
79 * @misc_0: Miscellaneous stream attributes 0 as specified
80 * by the DisplayPort 1.2 specification
81 * @misc_1: Miscellaneous stream attributes 1 as specified
82 * by the DisplayPort 1.2 specification
83 * @n_vid: N value for the video stream
84 * @m_vid: M value used to recover the video clock from the
85 * link clock
86 * @user_pixel_width: Width of the user data input port
87 * @data_per_lane: Used to translate the number of pixels per line
88 * to the native internal 16-bit datapath
89 * @avg_bytes_per_tu: Average number of bytes per transfer unit,
90 * scaled up by a factor of 1000
91 * @transfer_unit_size: Size of the transfer unit in the framing logic
92 * In MST mode, this is also the number of time
93 * slots that are alloted in the payload ID table
94 * @init_wait: Number of initial wait cycles at the start of a
95 * new line by the framing logic
96 * @bits_per_color: Bits per color component
97 * @component_format: The component format currently in use by the
98 * video stream
99 * @dynamic_range: The dynamic range currently in use by the video
100 * stream
101 * @y_cb_cr_colorimetry: The YCbCr colorimetry currently in use by the
102 * video stream
103 * @synchronous_clock_mode: Synchronous clock mode is currently in use by
104 * the video stream
105 * @override_user_pixel_width: If set to 1, the value stored for
106 * user_pixel_width will be used as the pixel width
107 * @h_start: Horizontal blank start (pixels)
108 * @h_active: Horizontal active resolution (pixels)
109 * @h_sync_width: Horizontal sync width (pixels)
110 * @h_total: Horizontal total (pixels)
111 * @h_sync_polarity: Horizontal sync polarity (0=neg|1=pos)
112 * @v_start: Vertical blank start (in lines)
113 * @v_active: Vertical active resolution (lines)
114 * @v_sync_width: Vertical sync width (lines)
115 * @v_total: Vertical total (lines)
116 * @v_sync_polarity: Vertical sync polarity (0=neg|1=pos)
117 *
118 * All porch parameters have been removed, because our videodata is
119 * hstart/vstart based, and there is no benefit in keeping the porches
120 */
121 struct main_stream_attributes {
122 u32 pixel_clock_hz;
123 u32 misc_0;
124 u32 misc_1;
125 u32 n_vid;
126 //u32 m_vid;
127 u32 user_pixel_width;
128 u32 data_per_lane;
129 u32 avg_bytes_per_tu;
130 u32 transfer_unit_size;
131 u32 init_wait;
132 u32 bits_per_color;
133 u8 component_format;
134 u8 dynamic_range;
135 u8 y_cb_cr_colorimetry;
136 u8 synchronous_clock_mode;
137 u8 override_user_pixel_width;
138 u32 h_start;
139 u16 h_active;
140 u16 h_sync_width;
141 u16 h_total;
142 bool h_sync_polarity;
143 u32 v_start;
144 u16 v_active;
145 u16 v_sync_width;
146 u16 v_total;
147 bool v_sync_polarity;
148 };
149
150 /**
151 * struct link_config - Description of link configuration
152 * @lane_count: Currently selected lane count for this link
153 * @link_rate: Currently selected link rate for this link
154 * @scrambler_en: Flag to determine whether the scrambler is
155 * enabled for this link
156 * @enhanced_framing_mode: Flag to determine whether enhanced framing
157 * mode is active for this link
158 * @max_lane_count: Maximum lane count for this link
159 * @max_link_rate: Maximum link rate for this link
160 * @support_enhanced_framing_mode: Flag to indicate whether the link supports
161 * enhanced framing mode
162 * @vs_level: Voltage swing for each lane
163 * @pe_level: Pre-emphasis/cursor level for each lane
164 */
165 struct link_config {
166 u8 lane_count;
167 u8 link_rate;
168 bool scrambler_en;
169 bool enhanced_framing_mode;
170 u8 max_lane_count;
171 u8 max_link_rate;
172 bool support_enhanced_framing_mode;
173 u8 vs_level;
174 u8 pe_level;
175 };
176
177 /**
178 * struct dp_tx - Private data structure of LogiCore DP TX devices
179 *
180 * @base: Address of register base of device
181 * @s_axi_clk: The AXI clock frequency in Hz
182 * @train_adaptive: Use adaptive link trainig (i.e. successively reduce
183 * link rate and/or lane count) for this device
184 * @max_link_rate: Maximum link rate for this device
185 * @max_lane_count: Maximum lane count for this device
186 * @dpcd_rx_caps: RX device's status registers, see below
187 * @lane_status_ajd_reqs: Lane status and adjustment requests information for
188 * this device
189 * @link_config: The link configuration for this device
190 * @main_stream_attributes: MSA set for this device
191 *
192 * dpcd_rx_caps is a raw read of the RX device's status registers. The first 4
193 * bytes correspond to the lane status associated with clock recovery, channel
194 * equalization, symbol lock, and interlane alignment. The remaining 2 bytes
195 * represent the pre-emphasis and voltage swing level adjustments requested by
196 * the RX device.
197 */
198 struct dp_tx {
199 u32 base;
200 u32 s_axi_clk;
201 bool train_adaptive;
202 u8 max_link_rate;
203 u8 max_lane_count;
204 u8 dpcd_rx_caps[16];
205 u8 lane_status_ajd_reqs[6];
206 struct link_config link_config;
207 struct main_stream_attributes main_stream_attributes;
208 };
209
210 /*
211 * Internal API
212 */
213
214 /**
215 * get_reg() - Read a register of a LogiCore DP TX device
216 * @dev: The LogiCore DP TX device in question
217 * @reg: The offset of the register to read
218 *
219 * Return: The read register value
220 */
get_reg(struct udevice * dev,u32 reg)221 static u32 get_reg(struct udevice *dev, u32 reg)
222 {
223 struct dp_tx *dp_tx = dev_get_priv(dev);
224 u32 value = 0;
225 int res;
226
227 /* TODO(mario.six@gdsys.cc): error handling */
228 res = axi_read(dev->parent, dp_tx->base + reg, &value, AXI_SIZE_32);
229 if (res < 0)
230 printf("%s() failed; res = %d\n", __func__, res);
231
232 return value;
233 }
234
235 /**
236 * set_reg() - Write a register of a LogiCore DP TX device
237 * @dev: The LogiCore DP TX device in question
238 * @reg: The offset of the register to write
239 * @value: The value to write to the register
240 */
set_reg(struct udevice * dev,u32 reg,u32 value)241 static void set_reg(struct udevice *dev, u32 reg, u32 value)
242 {
243 struct dp_tx *dp_tx = dev_get_priv(dev);
244
245 axi_write(dev->parent, dp_tx->base + reg, &value, AXI_SIZE_32);
246 }
247
248 /**
249 * is_connected() - Check if there is a connected RX device
250 * @dev: The LogiCore DP TX device in question
251 *
252 * The Xilinx original calls msleep_interruptible at least once, ignoring
253 * status.
254 *
255 * Return: true if a connected RX device was detected, false otherwise
256 */
is_connected(struct udevice * dev)257 static bool is_connected(struct udevice *dev)
258 {
259 u8 retries = 0;
260
261 do {
262 int status = get_reg(dev, REG_INTERRUPT_SIG_STATE) &
263 INTERRUPT_SIG_STATE_HPD_STATE_MASK;
264 if (status)
265 return true;
266
267 udelay(1000);
268 } while (retries++ < IS_CONNECTED_MAX_TIMEOUT_COUNT);
269
270 return false;
271 }
272
273 /**
274 * wait_phy_ready() - Wait for the DisplayPort PHY to come out of reset
275 * @dev: The LogiCore DP TX device in question
276 * @mask: Bit mask specifying which bit in the status register should be waited
277 * for
278 *
279 * Return: 0 if wait succeeded, -ve if error occurred
280 */
wait_phy_ready(struct udevice * dev,u32 mask)281 static int wait_phy_ready(struct udevice *dev, u32 mask)
282 {
283 u16 timeout = 20000;
284 u32 phy_status;
285
286 /* Wait until the PHY is ready. */
287 do {
288 phy_status = get_reg(dev, REG_PHY_STATUS) & mask;
289
290 /* Protect against an infinite loop. */
291 if (!timeout--)
292 return -ETIMEDOUT;
293
294 udelay(20);
295 } while (phy_status != mask);
296
297 return 0;
298 }
299
300 /* AUX channel access */
301
302 /**
303 * aux_wait_ready() - Wait until another request is no longer in progress
304 * @dev: The LogiCore DP TX device in question
305 *
306 * Return: 0 if wait succeeded, -ve if error occurred
307 */
aux_wait_ready(struct udevice * dev)308 static int aux_wait_ready(struct udevice *dev)
309 {
310 int status;
311 u32 timeout = 100;
312
313 /* Wait until the DisplayPort TX core is ready. */
314 do {
315 status = get_reg(dev, REG_INTERRUPT_SIG_STATE);
316
317 /* Protect against an infinite loop. */
318 if (!timeout--)
319 return -ETIMEDOUT;
320 udelay(20);
321 } while (status & REPLY_STATUS_REPLY_IN_PROGRESS_MASK);
322
323 return 0;
324 }
325
326 /**
327 * aux_wait_reply() - Wait for reply on AUX channel
328 * @dev: The LogiCore DP TX device in question
329 *
330 * Wait for a reply indicating that the most recent AUX request
331 * has been received by the RX device.
332 *
333 * Return: 0 if wait succeeded, -ve if error occurred
334 */
aux_wait_reply(struct udevice * dev)335 static int aux_wait_reply(struct udevice *dev)
336 {
337 u32 timeout = 100;
338
339 while (timeout > 0) {
340 int status = get_reg(dev, REG_REPLY_STATUS);
341
342 /* Check for error. */
343 if (status & REPLY_STATUS_REPLY_ERROR_MASK)
344 return -ETIMEDOUT;
345
346 /* Check for a reply. */
347 if ((status & REPLY_STATUS_REPLY_RECEIVED_MASK) &&
348 !(status &
349 REPLY_STATUS_REQUEST_IN_PROGRESS_MASK) &&
350 !(status &
351 REPLY_STATUS_REPLY_IN_PROGRESS_MASK)) {
352 return 0;
353 }
354
355 timeout--;
356 udelay(20);
357 }
358
359 return -ETIMEDOUT;
360 }
361
362 /**
363 * aux_request_send() - Send request on the AUX channel
364 * @dev: The LogiCore DP TX device in question
365 * @request: The request to send
366 *
367 * Submit the supplied AUX request to the RX device over the AUX
368 * channel by writing the command, the destination address, (the write buffer
369 * for write commands), and the data size to the DisplayPort TX core.
370 *
371 * This is the lower-level sending routine, which is called by aux_request().
372 *
373 * Return: 0 if request was sent successfully, -ve on error
374 */
aux_request_send(struct udevice * dev,struct aux_transaction * request)375 static int aux_request_send(struct udevice *dev,
376 struct aux_transaction *request)
377 {
378 u32 timeout_count;
379 int status;
380 u8 index;
381
382 /* Ensure that any pending AUX transactions have completed. */
383 timeout_count = 0;
384 do {
385 status = get_reg(dev, REG_REPLY_STATUS);
386
387 udelay(20);
388 timeout_count++;
389 if (timeout_count >= AUX_MAX_TIMEOUT_COUNT)
390 return -ETIMEDOUT;
391 } while ((status & REPLY_STATUS_REQUEST_IN_PROGRESS_MASK) ||
392 (status & REPLY_STATUS_REPLY_IN_PROGRESS_MASK));
393
394 set_reg(dev, REG_AUX_ADDRESS, request->address);
395
396 if (request->cmd_code == AUX_CMD_WRITE ||
397 request->cmd_code == AUX_CMD_I2C_WRITE ||
398 request->cmd_code == AUX_CMD_I2C_WRITE_MOT) {
399 /* Feed write data into the DisplayPort TX core's write FIFO. */
400 for (index = 0; index < request->num_bytes; index++) {
401 set_reg(dev,
402 REG_AUX_WRITE_FIFO, request->data[index]);
403 }
404 }
405
406 /* Submit the command and the data size. */
407 set_reg(dev, REG_AUX_CMD,
408 ((request->cmd_code << AUX_CMD_SHIFT) |
409 ((request->num_bytes - 1) &
410 AUX_CMD_NBYTES_TRANSFER_MASK)));
411
412 /* Check for a reply from the RX device to the submitted request. */
413 status = aux_wait_reply(dev);
414 if (status)
415 /* Waiting for a reply timed out. */
416 return -ETIMEDOUT;
417
418 /* Analyze the reply. */
419 status = get_reg(dev, REG_AUX_REPLY_CODE);
420 if (status == AUX_REPLY_CODE_DEFER ||
421 status == AUX_REPLY_CODE_I2C_DEFER) {
422 /* The request was deferred. */
423 return -EAGAIN;
424 } else if ((status == AUX_REPLY_CODE_NACK) ||
425 (status == AUX_REPLY_CODE_I2C_NACK)) {
426 /* The request was not acknowledged. */
427 return -EIO;
428 }
429
430 /* The request was acknowledged. */
431
432 if (request->cmd_code == AUX_CMD_READ ||
433 request->cmd_code == AUX_CMD_I2C_READ ||
434 request->cmd_code == AUX_CMD_I2C_READ_MOT) {
435 /* Wait until all data has been received. */
436 timeout_count = 0;
437 do {
438 status = get_reg(dev, REG_REPLY_DATA_COUNT);
439
440 udelay(100);
441 timeout_count++;
442 if (timeout_count >= AUX_MAX_TIMEOUT_COUNT)
443 return -ETIMEDOUT;
444 } while (status != request->num_bytes);
445
446 /* Obtain the read data from the reply FIFO. */
447 for (index = 0; index < request->num_bytes; index++)
448 request->data[index] = get_reg(dev, REG_AUX_REPLY_DATA);
449 }
450
451 return 0;
452 }
453
454 /**
455 * aux_request() - Submit request on the AUX channel
456 * @dev: The LogiCore DP TX device in question
457 * @request: The request to submit
458 *
459 * Submit the supplied AUX request to the RX device over the AUX
460 * channel. If waiting for a reply times out, or if the DisplayPort TX core
461 * indicates that the request was deferred, the request is sent again (up to a
462 * maximum specified by AUX_MAX_DEFER_COUNT|AUX_MAX_TIMEOUT_COUNT).
463 *
464 * Return: 0 if request was submitted successfully, -ve on error
465 */
aux_request(struct udevice * dev,struct aux_transaction * request)466 static int aux_request(struct udevice *dev, struct aux_transaction *request)
467 {
468 u32 defer_count = 0;
469 u32 timeout_count = 0;
470
471 while ((defer_count < AUX_MAX_DEFER_COUNT) &&
472 (timeout_count < AUX_MAX_TIMEOUT_COUNT)) {
473 int status = aux_wait_ready(dev);
474
475 if (status) {
476 /* The RX device isn't ready yet. */
477 timeout_count++;
478 continue;
479 }
480
481 status = aux_request_send(dev, request);
482 if (status == -EAGAIN) {
483 /* The request was deferred. */
484 defer_count++;
485 } else if (status == -ETIMEDOUT) {
486 /* Waiting for a reply timed out. */
487 timeout_count++;
488 } else {
489 /*
490 * -EIO indicates that the request was NACK'ed,
491 * 0 indicates that the request was ACK'ed.
492 */
493 return status;
494 }
495
496 udelay(100);
497 }
498
499 /* The request was not successfully received by the RX device. */
500 return -ETIMEDOUT;
501 }
502
503 /**
504 * aux_common() - Common (read/write) AUX communication transmission
505 * @dev: The LogiCore DP TX device in question
506 * @cmd_type: Command code of the transaction
507 * @address: The DPCD address of the transaction
508 * @num_bytes: Number of bytes in the payload data
509 * @data: The payload data of the AUX command
510 *
511 * Common sequence of submitting an AUX command for AUX read, AUX write,
512 * I2C-over-AUX read, and I2C-over-AUX write transactions. If required, the
513 * reads and writes are split into multiple requests, each acting on a maximum
514 * of 16 bytes.
515 *
516 * Return: 0 if OK, -ve on error
517 */
aux_common(struct udevice * dev,u32 cmd_type,u32 address,u32 num_bytes,u8 * data)518 static int aux_common(struct udevice *dev, u32 cmd_type, u32 address,
519 u32 num_bytes, u8 *data)
520 {
521 struct aux_transaction request;
522 u32 bytes_left;
523
524 /*
525 * Set the start address for AUX transactions. For I2C transactions,
526 * this is the address of the I2C bus.
527 */
528 request.address = address;
529
530 bytes_left = num_bytes;
531 while (bytes_left) {
532 int status;
533
534 request.cmd_code = cmd_type;
535
536 if (cmd_type == AUX_CMD_READ ||
537 cmd_type == AUX_CMD_WRITE) {
538 /* Increment address for normal AUX transactions. */
539 request.address = address + (num_bytes - bytes_left);
540 }
541
542 /* Increment the pointer to the supplied data buffer. */
543 request.data = &data[num_bytes - bytes_left];
544
545 request.num_bytes = (bytes_left > 16) ? 16 : bytes_left;
546 bytes_left -= request.num_bytes;
547
548 if (cmd_type == AUX_CMD_I2C_READ && bytes_left) {
549 /*
550 * Middle of a transaction I2C read request. Override
551 * the command code that was set to cmd_type.
552 */
553 request.cmd_code = AUX_CMD_I2C_READ_MOT;
554 } else if ((cmd_type == AUX_CMD_I2C_WRITE) && bytes_left) {
555 /*
556 * Middle of a transaction I2C write request. Override
557 * the command code that was set to cmd_type.
558 */
559 request.cmd_code = AUX_CMD_I2C_WRITE_MOT;
560 }
561
562 status = aux_request(dev, &request);
563 if (status)
564 return status;
565 }
566
567 return 0;
568 }
569
570 /**
571 * aux_read() - Issue AUX read request
572 * @dev: The LogiCore DP TX device in question
573 * @dpcd_address: The DPCD address to read from
574 * @bytes_to_read: Number of bytes to read
575 * @read_data: Buffer to receive the read data
576 *
577 * Issue a read request over the AUX channel that will read from the RX
578 * device's DisplayPort Configuration data (DPCD) address space. The read
579 * message will be divided into multiple transactions which read a maximum of
580 * 16 bytes each.
581 *
582 * Return: 0 if read operation was successful, -ve on error
583 */
aux_read(struct udevice * dev,u32 dpcd_address,u32 bytes_to_read,void * read_data)584 static int aux_read(struct udevice *dev, u32 dpcd_address, u32 bytes_to_read,
585 void *read_data)
586 {
587 int status;
588
589 if (!is_connected(dev))
590 return -ENODEV;
591
592 /* Send AUX read transaction. */
593 status = aux_common(dev, AUX_CMD_READ, dpcd_address,
594 bytes_to_read, (u8 *)read_data);
595
596 return status;
597 }
598
599 /**
600 * aux_write() - Issue AUX write request
601 * @dev: The LogiCore DP TX device in question
602 * @dpcd_address: The DPCD address to write to
603 * @bytes_to_write: Number of bytes to write
604 * @write_data: Buffer containig data to be written
605 *
606 * Issue a write request over the AUX channel that will write to
607 * the RX device's DisplayPort Configuration data (DPCD) address space. The
608 * write message will be divided into multiple transactions which write a
609 * maximum of 16 bytes each.
610 *
611 * Return: 0 if write operation was successful, -ve on error
612 */
aux_write(struct udevice * dev,u32 dpcd_address,u32 bytes_to_write,void * write_data)613 static int aux_write(struct udevice *dev, u32 dpcd_address, u32 bytes_to_write,
614 void *write_data)
615 {
616 int status;
617
618 if (!is_connected(dev))
619 return -ENODEV;
620
621 /* Send AUX write transaction. */
622 status = aux_common(dev, AUX_CMD_WRITE, dpcd_address,
623 bytes_to_write, (u8 *)write_data);
624
625 return status;
626 }
627
628 /* Core initialization */
629
630 /**
631 * initialize() - Initialize a LogiCore DP TX device
632 * @dev: The LogiCore DP TX device in question
633 *
634 * Return: Always 0
635 */
initialize(struct udevice * dev)636 static int initialize(struct udevice *dev)
637 {
638 struct dp_tx *dp_tx = dev_get_priv(dev);
639 u32 val;
640 u32 phy_config;
641 unsigned int k;
642
643 /* place the PHY (and GTTXRESET) into reset. */
644 phy_config = get_reg(dev, REG_PHY_CONFIG);
645 set_reg(dev, REG_PHY_CONFIG, phy_config | PHY_CONFIG_GT_ALL_RESET_MASK);
646
647 /* reset the video streams and AUX logic. */
648 set_reg(dev, REG_SOFT_RESET,
649 SOFT_RESET_VIDEO_STREAM_ALL_MASK |
650 SOFT_RESET_AUX_MASK);
651
652 /* disable the DisplayPort TX core. */
653 set_reg(dev, REG_ENABLE, 0);
654
655 /* set the clock divider. */
656 val = get_reg(dev, REG_AUX_CLK_DIVIDER);
657 val &= ~AUX_CLK_DIVIDER_VAL_MASK;
658 val |= dp_tx->s_axi_clk / 1000000;
659 set_reg(dev, REG_AUX_CLK_DIVIDER, val);
660
661 /* set the DisplayPort TX core's clock speed. */
662 set_reg(dev, REG_PHY_CLOCK_SELECT, PHY_CLOCK_SELECT_DEFAULT);
663
664 /* bring the PHY (and GTTXRESET) out of reset. */
665 set_reg(dev, REG_PHY_CONFIG,
666 phy_config & ~PHY_CONFIG_GT_ALL_RESET_MASK);
667
668 /* enable the DisplayPort TX core. */
669 set_reg(dev, REG_ENABLE, 1);
670
671 /* Unmask Hot-Plug-Detect (HPD) interrupts. */
672 set_reg(dev, REG_INTERRUPT_MASK,
673 ~INTERRUPT_MASK_HPD_PULSE_DETECTED_MASK &
674 ~INTERRUPT_MASK_HPD_EVENT_MASK &
675 ~INTERRUPT_MASK_HPD_IRQ_MASK);
676
677 for (k = 0; k < 4; k++) {
678 /* Disable pre-cursor levels. */
679 set_reg(dev, REG_PHY_PRECURSOR_LANE_0 + 4 * k, 0);
680
681 /* Write default voltage swing levels to the TX registers. */
682 set_reg(dev, REG_PHY_VOLTAGE_DIFF_LANE_0 + 4 * k, 0);
683
684 /* Write default pre-emphasis levels to the TX registers. */
685 set_reg(dev, REG_PHY_POSTCURSOR_LANE_0 + 4 * k, 0);
686 }
687
688 return 0;
689 }
690
691 /**
692 * is_link_rate_valid() - Check if given link rate is valif for device
693 * @dev: The LogiCore DP TX device in question
694 * @link_rate: The link rate to be checked for validity
695 *
696 * Return: true if he supplied link rate is valid, false otherwise
697 */
is_link_rate_valid(struct udevice * dev,u8 link_rate)698 static bool is_link_rate_valid(struct udevice *dev, u8 link_rate)
699 {
700 struct dp_tx *dp_tx = dev_get_priv(dev);
701 bool valid = true;
702
703 if (link_rate != LINK_BW_SET_162GBPS &&
704 link_rate != LINK_BW_SET_270GBPS &&
705 link_rate != LINK_BW_SET_540GBPS)
706 valid = false;
707 else if (link_rate > dp_tx->link_config.max_link_rate)
708 valid = false;
709
710 return valid;
711 }
712
713 /**
714 * is_lane_count_valid() - Check if given lane count is valif for device
715 * @dev: The LogiCore DP TX device in question
716 * @lane_count: The lane count to be checked for validity
717 *
718 * Return: true if he supplied lane count is valid, false otherwise
719 */
is_lane_count_valid(struct udevice * dev,u8 lane_count)720 static bool is_lane_count_valid(struct udevice *dev, u8 lane_count)
721 {
722 struct dp_tx *dp_tx = dev_get_priv(dev);
723 bool valid = true;
724
725 if (lane_count != LANE_COUNT_SET_1 &&
726 lane_count != LANE_COUNT_SET_2 &&
727 lane_count != LANE_COUNT_SET_4)
728 valid = false;
729 else if (lane_count > dp_tx->link_config.max_lane_count)
730 valid = false;
731
732 return valid;
733 }
734
735 /**
736 * get_rx_capabilities() - Check if capabilities of RX device are valid for TX
737 * device
738 * @dev: The LogiCore DP TX device in question
739 *
740 * Return: 0 if the capabilities of the RX device are valid for the TX device,
741 * -ve if not, of an error occurred during capability determination
742 */
get_rx_capabilities(struct udevice * dev)743 static int get_rx_capabilities(struct udevice *dev)
744 {
745 struct dp_tx *dp_tx = dev_get_priv(dev);
746 int status;
747 u8 rx_max_link_rate;
748 u8 rx_max_lane_count;
749
750 if (!is_connected(dev))
751 return -ENODEV;
752
753 status = aux_read(dev, DPCD_RECEIVER_CAP_FIELD_START, 16,
754 dp_tx->dpcd_rx_caps);
755 if (status)
756 return -EIO;
757
758 rx_max_link_rate = dp_tx->dpcd_rx_caps[DPCD_MAX_LINK_RATE];
759 rx_max_lane_count = dp_tx->dpcd_rx_caps[DPCD_MAX_LANE_COUNT] &
760 DPCD_MAX_LANE_COUNT_MASK;
761
762 dp_tx->link_config.max_link_rate =
763 (rx_max_link_rate > dp_tx->max_link_rate) ?
764 dp_tx->max_link_rate : rx_max_link_rate;
765 if (!is_link_rate_valid(dev, rx_max_link_rate))
766 return -EINVAL;
767
768 dp_tx->link_config.max_lane_count =
769 (rx_max_lane_count > dp_tx->max_lane_count) ?
770 dp_tx->max_lane_count : rx_max_lane_count;
771 if (!is_lane_count_valid(dev, rx_max_lane_count))
772 return -EINVAL;
773
774 dp_tx->link_config.support_enhanced_framing_mode =
775 dp_tx->dpcd_rx_caps[DPCD_MAX_LANE_COUNT] &
776 DPCD_ENHANCED_FRAME_SUPPORT_MASK;
777
778 return 0;
779 }
780
781 /**
782 * enable_main_link() - Switch on main link for a device
783 * @dev: The LogiCore DP TX device in question
784 */
enable_main_link(struct udevice * dev)785 static void enable_main_link(struct udevice *dev)
786 {
787 /* reset the scrambler. */
788 set_reg(dev, REG_FORCE_SCRAMBLER_RESET, 0x1);
789
790 /* enable the main stream. */
791 set_reg(dev, REG_ENABLE_MAIN_STREAM, 0x1);
792 }
793
794 /**
795 * disable_main_link() - Switch off main link for a device
796 * @dev: The LogiCore DP TX device in question
797 */
disable_main_link(struct udevice * dev)798 static void disable_main_link(struct udevice *dev)
799 {
800 /* reset the scrambler. */
801 set_reg(dev, REG_FORCE_SCRAMBLER_RESET, 0x1);
802
803 /* Disable the main stream. */
804 set_reg(dev, REG_ENABLE_MAIN_STREAM, 0x0);
805 }
806
807 /**
808 * reset_dp_phy() - Reset a device
809 * @dev: The LogiCore DP TX device in question
810 * @reset: Bit mask determining which bits in the device's config register
811 * should be set for the reset
812 */
reset_dp_phy(struct udevice * dev,u32 reset)813 static void reset_dp_phy(struct udevice *dev, u32 reset)
814 {
815 struct dp_tx *dp_tx = dev_get_priv(dev);
816 u32 val;
817
818 set_reg(dev, REG_ENABLE, 0x0);
819
820 val = get_reg(dev, REG_PHY_CONFIG);
821
822 /* Apply reset. */
823 set_reg(dev, REG_PHY_CONFIG, val | reset);
824
825 /* Remove reset. */
826 set_reg(dev, REG_PHY_CONFIG, val);
827
828 /* Wait for the PHY to be ready. */
829 wait_phy_ready(dev, phy_status_lanes_ready_mask(dp_tx->max_lane_count));
830
831 set_reg(dev, REG_ENABLE, 0x1);
832 }
833
834 /**
835 * set_enhanced_frame_mode() - Enable/Disable enhanced frame mode
836 * @dev: The LogiCore DP TX device in question
837 * @enable: Flag to determine whether to enable (1) or disable (0) the enhanced
838 * frame mode
839 *
840 * Enable or disable the enhanced framing symbol sequence for
841 * both the DisplayPort TX core and the RX device.
842 *
843 * Return: 0 if enabling/disabling the enhanced frame mode was successful, -ve
844 * on error
845 */
set_enhanced_frame_mode(struct udevice * dev,u8 enable)846 static int set_enhanced_frame_mode(struct udevice *dev, u8 enable)
847 {
848 struct dp_tx *dp_tx = dev_get_priv(dev);
849 int status;
850 u8 val;
851
852 if (!is_connected(dev))
853 return -ENODEV;
854
855 if (dp_tx->link_config.support_enhanced_framing_mode)
856 dp_tx->link_config.enhanced_framing_mode = enable;
857 else
858 dp_tx->link_config.enhanced_framing_mode = false;
859
860 /* Write enhanced frame mode enable to the DisplayPort TX core. */
861 set_reg(dev, REG_ENHANCED_FRAME_EN,
862 dp_tx->link_config.enhanced_framing_mode);
863
864 /* Write enhanced frame mode enable to the RX device. */
865 status = aux_read(dev, DPCD_LANE_COUNT_SET, 0x1, &val);
866 if (status)
867 return -EIO;
868
869 if (dp_tx->link_config.enhanced_framing_mode)
870 val |= DPCD_ENHANCED_FRAME_EN_MASK;
871 else
872 val &= ~DPCD_ENHANCED_FRAME_EN_MASK;
873
874 status = aux_write(dev, DPCD_LANE_COUNT_SET, 0x1, &val);
875 if (status)
876 return -EIO;
877
878 return 0;
879 }
880
881 /**
882 * set_lane_count() - Set the lane count
883 * @dev: The LogiCore DP TX device in question
884 * @lane_count: Lane count to set
885 *
886 * Set the number of lanes to be used by the main link for both
887 * the DisplayPort TX core and the RX device.
888 *
889 * Return: 0 if setting the lane count was successful, -ve on error
890 */
set_lane_count(struct udevice * dev,u8 lane_count)891 static int set_lane_count(struct udevice *dev, u8 lane_count)
892 {
893 struct dp_tx *dp_tx = dev_get_priv(dev);
894 int status;
895 u8 val;
896
897 if (!is_connected(dev))
898 return -ENODEV;
899
900 printf(" set lane count to %u\n", lane_count);
901
902 dp_tx->link_config.lane_count = lane_count;
903
904 /* Write the new lane count to the DisplayPort TX core. */
905 set_reg(dev, REG_LANE_COUNT_SET, dp_tx->link_config.lane_count);
906
907 /* Write the new lane count to the RX device. */
908 status = aux_read(dev, DPCD_LANE_COUNT_SET, 0x1, &val);
909 if (status)
910 return -EIO;
911 val &= ~DPCD_LANE_COUNT_SET_MASK;
912 val |= dp_tx->link_config.lane_count;
913
914 status = aux_write(dev, DPCD_LANE_COUNT_SET, 0x1, &val);
915 if (status)
916 return -EIO;
917
918 return 0;
919 }
920
921 /**
922 * set_clk_speed() - Set DP phy clock speed
923 * @dev: The LogiCore DP TX device in question
924 * @speed: The clock frquency to set (one of PHY_CLOCK_SELECT_*)
925 *
926 * Set the clock frequency for the DisplayPort PHY corresponding to a desired
927 * data rate.
928 *
929 * Return: 0 if setting the DP phy clock speed was successful, -ve on error
930 */
set_clk_speed(struct udevice * dev,u32 speed)931 static int set_clk_speed(struct udevice *dev, u32 speed)
932 {
933 struct dp_tx *dp_tx = dev_get_priv(dev);
934 int status;
935 u32 val;
936 u32 mask;
937
938 /* Disable the DisplayPort TX core first. */
939 val = get_reg(dev, REG_ENABLE);
940 set_reg(dev, REG_ENABLE, 0x0);
941
942 /* Change speed of the feedback clock. */
943 set_reg(dev, REG_PHY_CLOCK_SELECT, speed);
944
945 /* Re-enable the DisplayPort TX core if it was previously enabled. */
946 if (val)
947 set_reg(dev, REG_ENABLE, 0x1);
948
949 /* Wait until the PHY is ready. */
950 mask = phy_status_lanes_ready_mask(dp_tx->max_lane_count);
951 status = wait_phy_ready(dev, mask);
952 if (status)
953 return -EIO;
954
955 return 0;
956 }
957
958 /**
959 * set_link_rate() - Set the link rate
960 * @dev: The LogiCore DP TX device in question
961 * @link_rate: The link rate to set (one of LINK_BW_SET_*)
962 *
963 * Set the data rate to be used by the main link for both the DisplayPort TX
964 * core and the RX device.
965 *
966 * Return: 0 if setting the link rate was successful, -ve on error
967 */
set_link_rate(struct udevice * dev,u8 link_rate)968 static int set_link_rate(struct udevice *dev, u8 link_rate)
969 {
970 struct dp_tx *dp_tx = dev_get_priv(dev);
971 int status;
972
973 /* Write a corresponding clock frequency to the DisplayPort TX core. */
974 switch (link_rate) {
975 case LINK_BW_SET_162GBPS:
976 printf(" set link rate to 1.62 Gb/s\n");
977 status = set_clk_speed(dev, PHY_CLOCK_SELECT_162GBPS);
978 break;
979 case LINK_BW_SET_270GBPS:
980 printf(" set link rate to 2.70 Gb/s\n");
981 status = set_clk_speed(dev, PHY_CLOCK_SELECT_270GBPS);
982 break;
983 case LINK_BW_SET_540GBPS:
984 printf(" set link rate to 5.40 Gb/s\n");
985 status = set_clk_speed(dev, PHY_CLOCK_SELECT_540GBPS);
986 break;
987 default:
988 return -EINVAL;
989 }
990 if (status)
991 return -EIO;
992
993 dp_tx->link_config.link_rate = link_rate;
994
995 /* Write new link rate to the DisplayPort TX core. */
996 set_reg(dev, REG_LINK_BW_SET, dp_tx->link_config.link_rate);
997
998 /* Write new link rate to the RX device. */
999 status = aux_write(dev, DPCD_LINK_BW_SET, 1,
1000 &dp_tx->link_config.link_rate);
1001 if (status)
1002 return -EIO;
1003
1004 return 0;
1005 }
1006
1007 /* Link training */
1008
1009 /**
1010 * get_training_delay() - Get training delay
1011 * @dev: The LogiCore DP TX device in question
1012 * @training_state: The training state for which the required training delay
1013 * should be queried
1014 *
1015 * Determine what the RX device's required training delay is for
1016 * link training.
1017 *
1018 * Return: The training delay in us
1019 */
get_training_delay(struct udevice * dev,int training_state)1020 static int get_training_delay(struct udevice *dev, int training_state)
1021 {
1022 struct dp_tx *dp_tx = dev_get_priv(dev);
1023 u16 delay;
1024
1025 switch (dp_tx->dpcd_rx_caps[DPCD_TRAIN_AUX_RD_INTERVAL]) {
1026 case DPCD_TRAIN_AUX_RD_INT_100_400US:
1027 if (training_state == TS_CLOCK_RECOVERY)
1028 /* delay for the clock recovery phase. */
1029 delay = 100;
1030 else
1031 /* delay for the channel equalization phase. */
1032 delay = 400;
1033 break;
1034 case DPCD_TRAIN_AUX_RD_INT_4MS:
1035 delay = 4000;
1036 break;
1037 case DPCD_TRAIN_AUX_RD_INT_8MS:
1038 delay = 8000;
1039 break;
1040 case DPCD_TRAIN_AUX_RD_INT_12MS:
1041 delay = 12000;
1042 break;
1043 case DPCD_TRAIN_AUX_RD_INT_16MS:
1044 delay = 16000;
1045 break;
1046 default:
1047 /* Default to 20 ms. */
1048 delay = 20000;
1049 break;
1050 }
1051
1052 return delay;
1053 }
1054
1055 /**
1056 * set_vswing_preemp() - Build AUX data to set voltage swing and pre-emphasis
1057 * @dev: The LogiCore DP TX device in question
1058 * @aux_data: Buffer to receive the built AUX data
1059 *
1060 * Build AUX data to set current voltage swing and pre-emphasis level settings;
1061 * the necessary data is taken from the link_config structure.
1062 */
set_vswing_preemp(struct udevice * dev,u8 * aux_data)1063 static void set_vswing_preemp(struct udevice *dev, u8 *aux_data)
1064 {
1065 struct dp_tx *dp_tx = dev_get_priv(dev);
1066 u8 data;
1067 u8 vs_level_rx = dp_tx->link_config.vs_level;
1068 u8 pe_level_rx = dp_tx->link_config.pe_level;
1069
1070 /* Set up the data buffer for writing to the RX device. */
1071 data = (pe_level_rx << DPCD_TRAINING_LANEX_SET_PE_SHIFT) | vs_level_rx;
1072 /* The maximum voltage swing has been reached. */
1073 if (vs_level_rx == MAXIMUM_VS_LEVEL)
1074 data |= DPCD_TRAINING_LANEX_SET_MAX_VS_MASK;
1075
1076 /* The maximum pre-emphasis level has been reached. */
1077 if (pe_level_rx == MAXIMUM_PE_LEVEL)
1078 data |= DPCD_TRAINING_LANEX_SET_MAX_PE_MASK;
1079 memset(aux_data, data, 4);
1080 }
1081
1082 /**
1083 * adj_vswing_preemp() - Adjust voltage swing and pre-emphasis
1084 * @dev: The LogiCore DP TX device in question
1085 *
1086 * Set new voltage swing and pre-emphasis levels using the
1087 * adjustment requests obtained from the RX device.
1088 *
1089 * Return: 0 if voltage swing and pre-emphasis could be adjusted successfully,
1090 * -ve on error
1091 */
adj_vswing_preemp(struct udevice * dev)1092 static int adj_vswing_preemp(struct udevice *dev)
1093 {
1094 struct dp_tx *dp_tx = dev_get_priv(dev);
1095 int status;
1096 u8 index;
1097 u8 vs_level_adj_req[4];
1098 u8 pe_level_adj_req[4];
1099 u8 aux_data[4];
1100 u8 *ajd_reqs = &dp_tx->lane_status_ajd_reqs[4];
1101
1102 /*
1103 * Analyze the adjustment requests for changes in voltage swing and
1104 * pre-emphasis levels.
1105 */
1106 vs_level_adj_req[0] = ajd_reqs[0] & DPCD_ADJ_REQ_LANE_0_2_VS_MASK;
1107 vs_level_adj_req[1] = (ajd_reqs[0] & DPCD_ADJ_REQ_LANE_1_3_VS_MASK) >>
1108 DPCD_ADJ_REQ_LANE_1_3_VS_SHIFT;
1109 vs_level_adj_req[2] = ajd_reqs[1] & DPCD_ADJ_REQ_LANE_0_2_VS_MASK;
1110 vs_level_adj_req[3] = (ajd_reqs[1] & DPCD_ADJ_REQ_LANE_1_3_VS_MASK) >>
1111 DPCD_ADJ_REQ_LANE_1_3_VS_SHIFT;
1112 pe_level_adj_req[0] = (ajd_reqs[0] & DPCD_ADJ_REQ_LANE_0_2_PE_MASK) >>
1113 DPCD_ADJ_REQ_LANE_0_2_PE_SHIFT;
1114 pe_level_adj_req[1] = (ajd_reqs[0] & DPCD_ADJ_REQ_LANE_1_3_PE_MASK) >>
1115 DPCD_ADJ_REQ_LANE_1_3_PE_SHIFT;
1116 pe_level_adj_req[2] = (ajd_reqs[1] & DPCD_ADJ_REQ_LANE_0_2_PE_MASK) >>
1117 DPCD_ADJ_REQ_LANE_0_2_PE_SHIFT;
1118 pe_level_adj_req[3] = (ajd_reqs[1] & DPCD_ADJ_REQ_LANE_1_3_PE_MASK) >>
1119 DPCD_ADJ_REQ_LANE_1_3_PE_SHIFT;
1120
1121 /*
1122 * Change the drive settings to match the adjustment requests. Use the
1123 * greatest level requested.
1124 */
1125 dp_tx->link_config.vs_level = 0;
1126 dp_tx->link_config.pe_level = 0;
1127 for (index = 0; index < dp_tx->link_config.lane_count; index++) {
1128 if (vs_level_adj_req[index] > dp_tx->link_config.vs_level)
1129 dp_tx->link_config.vs_level = vs_level_adj_req[index];
1130 if (pe_level_adj_req[index] > dp_tx->link_config.pe_level)
1131 dp_tx->link_config.pe_level = pe_level_adj_req[index];
1132 }
1133
1134 /*
1135 * Verify that the voltage swing and pre-emphasis combination is
1136 * allowed. Some combinations will result in a differential peak-to-peak
1137 * voltage that is outside the permissible range. See the VESA
1138 * DisplayPort v1.2 Specification, section 3.1.5.2.
1139 * The valid combinations are:
1140 * PE=0 PE=1 PE=2 PE=3
1141 * VS=0 valid valid valid valid
1142 * VS=1 valid valid valid
1143 * VS=2 valid valid
1144 * VS=3 valid
1145 *
1146 * NOTE:
1147 * Xilinix dp_v3_1 driver seems to have an off by one error when
1148 * limiting pe_level which is fixed here.
1149 */
1150 if (dp_tx->link_config.pe_level > (3 - dp_tx->link_config.vs_level))
1151 dp_tx->link_config.pe_level = 3 - dp_tx->link_config.vs_level;
1152
1153 /*
1154 * Make the adjustments to both the DisplayPort TX core and the RX
1155 * device.
1156 */
1157 set_vswing_preemp(dev, aux_data);
1158 /*
1159 * Write the voltage swing and pre-emphasis levels for each lane to the
1160 * RX device.
1161 */
1162 status = aux_write(dev, DPCD_TRAINING_LANE0_SET, 4, aux_data);
1163 if (status)
1164 return -EIO;
1165
1166 return 0;
1167 }
1168
1169 /**
1170 * get_lane_status_adj_reqs() - Read lane status and adjustment requests
1171 * information from the device
1172 * @dev: The LogiCore DP TX device in question
1173 *
1174 * Do a burst AUX read from the RX device over the AUX channel. The contents of
1175 * the status registers will be stored for later use by check_clock_recovery,
1176 * check_channel_equalization, and adj_vswing_preemp.
1177 *
1178 * Return: 0 if the status information were read successfully, -ve on error
1179 */
get_lane_status_adj_reqs(struct udevice * dev)1180 static int get_lane_status_adj_reqs(struct udevice *dev)
1181 {
1182 struct dp_tx *dp_tx = dev_get_priv(dev);
1183 int status;
1184
1185 /*
1186 * Read and store 4 bytes of lane status and 2 bytes of adjustment
1187 * requests.
1188 */
1189 status = aux_read(dev, DPCD_STATUS_LANE_0_1, 6,
1190 dp_tx->lane_status_ajd_reqs);
1191 if (status)
1192 return -EIO;
1193
1194 return 0;
1195 }
1196
1197 /**
1198 * check_clock_recovery() - Check clock recovery success
1199 * @dev: The LogiCore DP TX device in question
1200 * @lane_count: The number of lanes for which to check clock recovery success
1201 *
1202 * Check if the RX device's DisplayPort Configuration data (DPCD) indicates
1203 * that the clock recovery sequence during link training was successful - the
1204 * RX device's link clock and data recovery unit has realized and maintained
1205 * the frequency lock for all lanes currently in use.
1206 *
1207 * Return: 0 if clock recovery was successful on all lanes in question, -ve if
1208 * not
1209 */
check_clock_recovery(struct udevice * dev,u8 lane_count)1210 static int check_clock_recovery(struct udevice *dev, u8 lane_count)
1211 {
1212 struct dp_tx *dp_tx = dev_get_priv(dev);
1213 u8 *lane_status = dp_tx->lane_status_ajd_reqs;
1214
1215 /* Check that all LANEx_CR_DONE bits are set. */
1216 switch (lane_count) {
1217 case LANE_COUNT_SET_4:
1218 if (!(lane_status[1] & DPCD_STATUS_LANE_3_CR_DONE_MASK))
1219 goto out_fail;
1220 if (!(lane_status[1] & DPCD_STATUS_LANE_2_CR_DONE_MASK))
1221 goto out_fail;
1222 /* Drop through and check lane 1. */
1223 case LANE_COUNT_SET_2:
1224 if (!(lane_status[0] & DPCD_STATUS_LANE_1_CR_DONE_MASK))
1225 goto out_fail;
1226 /* Drop through and check lane 0. */
1227 case LANE_COUNT_SET_1:
1228 if (!(lane_status[0] & DPCD_STATUS_LANE_0_CR_DONE_MASK))
1229 goto out_fail;
1230 default:
1231 /* All (lane_count) lanes have achieved clock recovery. */
1232 break;
1233 }
1234
1235 return 0;
1236
1237 out_fail:
1238 return -EIO;
1239 }
1240
1241 /**
1242 * check_channel_equalization() - Check channel equalization success
1243 * @dev: The LogiCore DP TX device in question
1244 * @lane_count: The number of lanes for which to check channel equalization
1245 * success
1246 *
1247 * Check if the RX device's DisplayPort Configuration data (DPCD) indicates
1248 * that the channel equalization sequence during link training was successful -
1249 * the RX device has achieved channel equalization, symbol lock, and interlane
1250 * alignment for all lanes currently in use.
1251 *
1252 * Return: 0 if channel equalization was successful on all lanes in question,
1253 * -ve if not
1254 */
check_channel_equalization(struct udevice * dev,u8 lane_count)1255 static int check_channel_equalization(struct udevice *dev, u8 lane_count)
1256 {
1257 struct dp_tx *dp_tx = dev_get_priv(dev);
1258 u8 *lane_status = dp_tx->lane_status_ajd_reqs;
1259
1260 /* Check that all LANEx_CHANNEL_EQ_DONE bits are set. */
1261 switch (lane_count) {
1262 case LANE_COUNT_SET_4:
1263 if (!(lane_status[1] & DPCD_STATUS_LANE_3_CE_DONE_MASK))
1264 goto out_fail;
1265 if (!(lane_status[1] & DPCD_STATUS_LANE_2_CE_DONE_MASK))
1266 goto out_fail;
1267 /* Drop through and check lane 1. */
1268 case LANE_COUNT_SET_2:
1269 if (!(lane_status[0] & DPCD_STATUS_LANE_1_CE_DONE_MASK))
1270 goto out_fail;
1271 /* Drop through and check lane 0. */
1272 case LANE_COUNT_SET_1:
1273 if (!(lane_status[0] & DPCD_STATUS_LANE_0_CE_DONE_MASK))
1274 goto out_fail;
1275 default:
1276 /* All (lane_count) lanes have achieved channel equalization. */
1277 break;
1278 }
1279
1280 /* Check that all LANEx_SYMBOL_LOCKED bits are set. */
1281 switch (lane_count) {
1282 case LANE_COUNT_SET_4:
1283 if (!(lane_status[1] & DPCD_STATUS_LANE_3_SL_DONE_MASK))
1284 goto out_fail;
1285 if (!(lane_status[1] & DPCD_STATUS_LANE_2_SL_DONE_MASK))
1286 goto out_fail;
1287 /* Drop through and check lane 1. */
1288 case LANE_COUNT_SET_2:
1289 if (!(lane_status[0] & DPCD_STATUS_LANE_1_SL_DONE_MASK))
1290 goto out_fail;
1291 /* Drop through and check lane 0. */
1292 case LANE_COUNT_SET_1:
1293 if (!(lane_status[0] & DPCD_STATUS_LANE_0_SL_DONE_MASK))
1294 goto out_fail;
1295 default:
1296 /* All (lane_count) lanes have achieved symbol lock. */
1297 break;
1298 }
1299
1300 /* Check that interlane alignment is done. */
1301 if (!(lane_status[2] & DPCD_LANE_ALIGN_STATUS_UPDATED_IA_DONE_MASK))
1302 goto out_fail;
1303
1304 return 0;
1305
1306 out_fail:
1307 return -EIO;
1308 }
1309
1310 /**
1311 * set_training_pattern() - Set training pattern for link training
1312 * @dev: The LogiCore DP TX device in question
1313 * @pattern: The training pattern to set
1314 *
1315 * Set the training pattern to be used during link training for both the
1316 * DisplayPort TX core and the RX device.
1317 *
1318 * Return: 0 if the training pattern could be set successfully, -ve if not
1319 */
set_training_pattern(struct udevice * dev,u32 pattern)1320 static int set_training_pattern(struct udevice *dev, u32 pattern)
1321 {
1322 struct dp_tx *dp_tx = dev_get_priv(dev);
1323 int status;
1324 u8 aux_data[5];
1325
1326 /* Write to the DisplayPort TX core. */
1327 set_reg(dev, REG_TRAINING_PATTERN_SET, pattern);
1328
1329 aux_data[0] = pattern;
1330
1331 /* Write scrambler disable to the DisplayPort TX core. */
1332 switch (pattern) {
1333 case TRAINING_PATTERN_SET_OFF:
1334 set_reg(dev, REG_SCRAMBLING_DISABLE, 0);
1335 dp_tx->link_config.scrambler_en = 1;
1336 break;
1337 case TRAINING_PATTERN_SET_TP1:
1338 case TRAINING_PATTERN_SET_TP2:
1339 case TRAINING_PATTERN_SET_TP3:
1340 aux_data[0] |= DPCD_TP_SET_SCRAMB_DIS_MASK;
1341 set_reg(dev, REG_SCRAMBLING_DISABLE, 1);
1342 dp_tx->link_config.scrambler_en = 0;
1343 break;
1344 default:
1345 break;
1346 }
1347
1348 /*
1349 * Make the adjustments to both the DisplayPort TX core and the RX
1350 * device.
1351 */
1352 set_vswing_preemp(dev, &aux_data[1]);
1353 /*
1354 * Write the voltage swing and pre-emphasis levels for each lane to the
1355 * RX device.
1356 */
1357 if (pattern == TRAINING_PATTERN_SET_OFF)
1358 status = aux_write(dev, DPCD_TP_SET, 1, aux_data);
1359 else
1360 status = aux_write(dev, DPCD_TP_SET, 5, aux_data);
1361 if (status)
1362 return -EIO;
1363
1364 return 0;
1365 }
1366
1367 /**
1368 * training_state_clock_recovery() - Run clock recovery part of link training
1369 * @dev: The LogiCore DP TX device in question
1370 *
1371 * Run the clock recovery sequence as part of link training. The
1372 * sequence is as follows:
1373 *
1374 * 0) Start signaling at the minimum voltage swing, pre-emphasis, and
1375 * post- cursor levels.
1376 * 1) Transmit training pattern 1 over the main link with symbol
1377 * scrambling disabled.
1378 * 2) The clock recovery loop. If clock recovery is unsuccessful after
1379 * MaxIterations loop iterations, return.
1380 * 2a) Wait for at least the period of time specified in the RX device's
1381 * DisplayPort Configuration data (DPCD) register,
1382 * TRAINING_AUX_RD_INTERVAL.
1383 * 2b) Check if all lanes have achieved clock recovery lock. If so,
1384 * return.
1385 * 2c) Check if the same voltage swing level has been used 5 consecutive
1386 * times or if the maximum level has been reached. If so, return.
1387 * 2d) Adjust the voltage swing, pre-emphasis, and post-cursor levels as
1388 * requested by the RX device.
1389 * 2e) Loop back to 2a.
1390 *
1391 * For a more detailed description of the clock recovery sequence, see section
1392 * 3.5.1.2.1 of the DisplayPort 1.2a specification document.
1393 *
1394 * Return: The next state machine state to advance to
1395 */
training_state_clock_recovery(struct udevice * dev)1396 static unsigned int training_state_clock_recovery(struct udevice *dev)
1397 {
1398 struct dp_tx *dp_tx = dev_get_priv(dev);
1399 int status;
1400 u32 delay_us;
1401 u8 prev_vs_level = 0;
1402 u8 same_vs_level_count = 0;
1403
1404 /*
1405 * Obtain the required delay for clock recovery as specified by the
1406 * RX device.
1407 */
1408 delay_us = get_training_delay(dev, TS_CLOCK_RECOVERY);
1409
1410 /* Start CRLock. */
1411
1412 /* Transmit training pattern 1. */
1413 /* Disable the scrambler. */
1414 /* Start from minimal voltage swing and pre-emphasis levels. */
1415 dp_tx->link_config.vs_level = 0;
1416 dp_tx->link_config.pe_level = 0;
1417 status = set_training_pattern(dev, TRAINING_PATTERN_SET_TP1);
1418 if (status)
1419 return TS_FAILURE;
1420
1421 while (1) {
1422 /* Wait delay specified in TRAINING_AUX_RD_INTERVAL. */
1423 udelay(delay_us);
1424
1425 /* Get lane and adjustment requests. */
1426 status = get_lane_status_adj_reqs(dev);
1427 if (status)
1428 return TS_FAILURE;
1429
1430 /*
1431 * Check if all lanes have realized and maintained the frequency
1432 * lock and get adjustment requests.
1433 */
1434 status = check_clock_recovery(dev,
1435 dp_tx->link_config.lane_count);
1436 if (!status)
1437 return TS_CHANNEL_EQUALIZATION;
1438
1439 /*
1440 * Check if the same voltage swing for each lane has been used 5
1441 * consecutive times.
1442 */
1443 if (prev_vs_level == dp_tx->link_config.vs_level) {
1444 same_vs_level_count++;
1445 } else {
1446 same_vs_level_count = 0;
1447 prev_vs_level = dp_tx->link_config.vs_level;
1448 }
1449 if (same_vs_level_count >= 5)
1450 break;
1451
1452 /* Only try maximum voltage swing once. */
1453 if (dp_tx->link_config.vs_level == MAXIMUM_VS_LEVEL)
1454 break;
1455
1456 /* Adjust the drive settings as requested by the RX device. */
1457 status = adj_vswing_preemp(dev);
1458 if (status)
1459 /* The AUX write failed. */
1460 return TS_FAILURE;
1461 }
1462
1463 return TS_ADJUST_LINK_RATE;
1464 }
1465
1466 /**
1467 * training_state_channel_equalization() - Run channel equalization part of
1468 * link training
1469 * @dev: The LogiCore DP TX device in question
1470 *
1471 * Run the channel equalization sequence as part of link
1472 * training. The sequence is as follows:
1473 *
1474 * 0) Start signaling with the same drive settings used at the end of the
1475 * clock recovery sequence.
1476 * 1) Transmit training pattern 2 (or 3) over the main link with symbol
1477 * scrambling disabled.
1478 * 2) The channel equalization loop. If channel equalization is
1479 * unsuccessful after 5 loop iterations, return.
1480 * 2a) Wait for at least the period of time specified in the RX device's
1481 * DisplayPort Configuration data (DPCD) register,
1482 * TRAINING_AUX_RD_INTERVAL.
1483 * 2b) Check if all lanes have achieved channel equalization, symbol lock,
1484 * and interlane alignment. If so, return.
1485 * 2c) Check if the same voltage swing level has been used 5 consecutive
1486 * times or if the maximum level has been reached. If so, return.
1487 * 2d) Adjust the voltage swing, pre-emphasis, and post-cursor levels as
1488 * requested by the RX device.
1489 * 2e) Loop back to 2a.
1490 *
1491 * For a more detailed description of the channel equalization sequence, see
1492 * section 3.5.1.2.2 of the DisplayPort 1.2a specification document.
1493 *
1494 * Return: The next state machine state to advance to
1495 */
training_state_channel_equalization(struct udevice * dev)1496 static int training_state_channel_equalization(struct udevice *dev)
1497 {
1498 struct dp_tx *dp_tx = dev_get_priv(dev);
1499 int status;
1500 u32 delay_us;
1501 u32 iteration_count = 0;
1502
1503 /*
1504 * Obtain the required delay for channel equalization as specified by
1505 * the RX device.
1506 */
1507 delay_us = get_training_delay(dev, TS_CHANNEL_EQUALIZATION);
1508
1509 /* Start channel equalization. */
1510
1511 /* Write the current drive settings. */
1512 /* Transmit training pattern 2/3. */
1513 if (dp_tx->dpcd_rx_caps[DPCD_MAX_LANE_COUNT] & DPCD_TPS3_SUPPORT_MASK)
1514 status = set_training_pattern(dev, TRAINING_PATTERN_SET_TP3);
1515 else
1516 status = set_training_pattern(dev, TRAINING_PATTERN_SET_TP2);
1517
1518 if (status)
1519 return TS_FAILURE;
1520
1521 while (iteration_count < 5) {
1522 /* Wait delay specified in TRAINING_AUX_RD_INTERVAL. */
1523 udelay(delay_us);
1524
1525 /* Get lane and adjustment requests. */
1526 status = get_lane_status_adj_reqs(dev);
1527 if (status)
1528 /* The AUX read failed. */
1529 return TS_FAILURE;
1530
1531 /* Check that all lanes still have their clocks locked. */
1532 status = check_clock_recovery(dev,
1533 dp_tx->link_config.lane_count);
1534 if (status)
1535 break;
1536
1537 /*
1538 * Check if all lanes have accomplished channel equalization,
1539 * symbol lock, and interlane alignment.
1540 */
1541 status =
1542 check_channel_equalization(dev,
1543 dp_tx->link_config.lane_count);
1544 if (!status)
1545 return TS_SUCCESS;
1546
1547 /* Adjust the drive settings as requested by the RX device. */
1548 status = adj_vswing_preemp(dev);
1549 if (status)
1550 /* The AUX write failed. */
1551 return TS_FAILURE;
1552
1553 iteration_count++;
1554 }
1555
1556 /*
1557 * Tried 5 times with no success. Try a reduced bitrate first, then
1558 * reduce the number of lanes.
1559 */
1560 return TS_ADJUST_LINK_RATE;
1561 }
1562
1563 /**
1564 * training_state_adjust_link_rate() - Downshift data rate and/or lane count
1565 * @dev: The LogiCore DP TX device in question
1566 *
1567 * This function is reached if either the clock recovery or the channel
1568 * equalization process failed during training. As a result, the data rate will
1569 * be downshifted, and training will be re-attempted (starting with clock
1570 * recovery) at the reduced data rate. If the data rate is already at 1.62
1571 * Gbps, a downshift in lane count will be attempted.
1572 *
1573 * Return: The next state machine state to advance to
1574 */
training_state_adjust_link_rate(struct udevice * dev)1575 static int training_state_adjust_link_rate(struct udevice *dev)
1576 {
1577 struct dp_tx *dp_tx = dev_get_priv(dev);
1578 int status;
1579
1580 switch (dp_tx->link_config.link_rate) {
1581 case LINK_BW_SET_540GBPS:
1582 status = set_link_rate(dev, LINK_BW_SET_270GBPS);
1583 if (status) {
1584 status = TS_FAILURE;
1585 break;
1586 }
1587 status = TS_CLOCK_RECOVERY;
1588 break;
1589 case LINK_BW_SET_270GBPS:
1590 status = set_link_rate(dev, LINK_BW_SET_162GBPS);
1591 if (status) {
1592 status = TS_FAILURE;
1593 break;
1594 }
1595 status = TS_CLOCK_RECOVERY;
1596 break;
1597 default:
1598 /*
1599 * Already at the lowest link rate. Try reducing the lane
1600 * count next.
1601 */
1602 status = TS_ADJUST_LANE_COUNT;
1603 break;
1604 }
1605
1606 return status;
1607 }
1608
1609 /**
1610 * trainig_state_adjust_lane_count - Downshift lane count
1611 * @dev: The LogiCore DP TX device in question
1612 *
1613 * This function is reached if either the clock recovery or the channel
1614 * equalization process failed during training, and a minimal data rate of 1.62
1615 * Gbps was being used. As a result, the number of lanes in use will be
1616 * reduced, and training will be re-attempted (starting with clock recovery) at
1617 * this lower lane count.
1618 *
1619 * Return: The next state machine state to advance to
1620 */
trainig_state_adjust_lane_count(struct udevice * dev)1621 static int trainig_state_adjust_lane_count(struct udevice *dev)
1622 {
1623 struct dp_tx *dp_tx = dev_get_priv(dev);
1624 int status;
1625
1626 switch (dp_tx->link_config.lane_count) {
1627 case LANE_COUNT_SET_4:
1628 status = set_lane_count(dev, LANE_COUNT_SET_2);
1629 if (status) {
1630 status = TS_FAILURE;
1631 break;
1632 }
1633
1634 status = set_link_rate(dev, dp_tx->link_config.max_link_rate);
1635 if (status) {
1636 status = TS_FAILURE;
1637 break;
1638 }
1639 status = TS_CLOCK_RECOVERY;
1640 break;
1641 case LANE_COUNT_SET_2:
1642 status = set_lane_count(dev, LANE_COUNT_SET_1);
1643 if (status) {
1644 status = TS_FAILURE;
1645 break;
1646 }
1647
1648 status = set_link_rate(dev, dp_tx->link_config.max_link_rate);
1649 if (status) {
1650 status = TS_FAILURE;
1651 break;
1652 }
1653 status = TS_CLOCK_RECOVERY;
1654 break;
1655 default:
1656 /*
1657 * Already at the lowest lane count. Training has failed at the
1658 * lowest lane count and link rate.
1659 */
1660 status = TS_FAILURE;
1661 break;
1662 }
1663
1664 return status;
1665 }
1666
1667 /**
1668 * check_link_status() - Check status of link
1669 * @dev: The LogiCore DP TX device in question
1670 * @lane_count: The lane count to use for the check
1671 *
1672 * Check if the receiver's DisplayPort Configuration data (DPCD) indicates the
1673 * receiver has achieved and maintained clock recovery, channel equalization,
1674 * symbol lock, and interlane alignment for all lanes currently in use.
1675 *
1676 * Return: 0 if the link status is OK, -ve if a error occurred during checking
1677 */
check_link_status(struct udevice * dev,u8 lane_count)1678 static int check_link_status(struct udevice *dev, u8 lane_count)
1679 {
1680 u8 retry_count = 0;
1681
1682 if (!is_connected(dev))
1683 return -ENODEV;
1684
1685 /* Retrieve AUX info. */
1686 do {
1687 int status;
1688
1689 /* Get lane and adjustment requests. */
1690 status = get_lane_status_adj_reqs(dev);
1691 if (status)
1692 return -EIO;
1693
1694 /* Check if the link needs training. */
1695 if ((check_clock_recovery(dev, lane_count) == 0) &&
1696 (check_channel_equalization(dev, lane_count) == 0))
1697 return 0;
1698
1699 retry_count++;
1700 } while (retry_count < 5); /* Retry up to 5 times. */
1701
1702 return -EIO;
1703 }
1704
1705 /**
1706 * run_training() - Run link training
1707 * @dev: The LogiCore DP TX device in question
1708 *
1709 * Run the link training process. It is implemented as a state machine, with
1710 * each state returning the next state. First, the clock recovery sequence will
1711 * be run; if successful, the channel equalization sequence will run. If either
1712 * the clock recovery or channel equalization sequence failed, the link rate or
1713 * the number of lanes used will be reduced and training will be re-attempted.
1714 * If training fails at the minimal data rate, 1.62 Gbps with a single lane,
1715 * training will no longer re-attempt and fail.
1716 *
1717 * ### Here be dragons ###
1718 * There are undocumented timeout constraints in the link training process. In
1719 * DP v1.2a spec, Chapter 3.5.1.2.2 a 10ms limit for the complete training
1720 * process is mentioned. Which individual timeouts are derived and implemented
1721 * by sink manufacturers is unknown. So each step should be as short as
1722 * possible and link training should start as soon as possible after HPD.
1723 *
1724 * Return: 0 if the training sequence ran successfully, -ve if a error occurred
1725 * or the training failed
1726 */
run_training(struct udevice * dev)1727 static int run_training(struct udevice *dev)
1728 {
1729 struct dp_tx *dp_tx = dev_get_priv(dev);
1730 int status;
1731 int training_state = TS_CLOCK_RECOVERY;
1732
1733 while (1) {
1734 switch (training_state) {
1735 case TS_CLOCK_RECOVERY:
1736 training_state =
1737 training_state_clock_recovery(dev);
1738 break;
1739 case TS_CHANNEL_EQUALIZATION:
1740 training_state =
1741 training_state_channel_equalization(dev);
1742 break;
1743 case TS_ADJUST_LINK_RATE:
1744 training_state =
1745 training_state_adjust_link_rate(dev);
1746 break;
1747 case TS_ADJUST_LANE_COUNT:
1748 training_state =
1749 trainig_state_adjust_lane_count(dev);
1750 break;
1751 default:
1752 break;
1753 }
1754
1755 if (training_state == TS_SUCCESS)
1756 break;
1757 else if (training_state == TS_FAILURE)
1758 return -EIO;
1759
1760 if (training_state == TS_ADJUST_LINK_RATE ||
1761 training_state == TS_ADJUST_LANE_COUNT) {
1762 if (!dp_tx->train_adaptive)
1763 return -EIO;
1764
1765 status = set_training_pattern(dev,
1766 TRAINING_PATTERN_SET_OFF);
1767 if (status)
1768 return -EIO;
1769 }
1770 }
1771
1772 /* Final status check. */
1773 status = check_link_status(dev, dp_tx->link_config.lane_count);
1774 if (status)
1775 return -EIO;
1776
1777 return 0;
1778 }
1779
1780 /* Link policy maker */
1781
1782 /**
1783 * cfg_main_link_max() - Determine best common capabilities
1784 * @dev: The LogiCore DP TX device in question
1785 *
1786 * Determine the common capabilities between the DisplayPort TX core and the RX
1787 * device.
1788 *
1789 * Return: 0 if the determination succeeded, -ve on error
1790 */
cfg_main_link_max(struct udevice * dev)1791 static int cfg_main_link_max(struct udevice *dev)
1792 {
1793 struct dp_tx *dp_tx = dev_get_priv(dev);
1794 int status;
1795
1796 if (!is_connected(dev))
1797 return -ENODEV;
1798
1799 /*
1800 * Configure the main link to the maximum common link rate between the
1801 * DisplayPort TX core and the RX device.
1802 */
1803 status = set_link_rate(dev, dp_tx->link_config.max_link_rate);
1804 if (status)
1805 return status;
1806
1807 /*
1808 * Configure the main link to the maximum common lane count between the
1809 * DisplayPort TX core and the RX device.
1810 */
1811 status = set_lane_count(dev, dp_tx->link_config.max_lane_count);
1812 if (status)
1813 return status;
1814
1815 return 0;
1816 }
1817
1818 /**
1819 * establish_link() - Establish a link
1820 * @dev: The LogiCore DP TX device in question
1821 *
1822 * Check if the link needs training and run the training sequence if training
1823 * is required.
1824 *
1825 * Return: 0 if the link was established successfully, -ve on error
1826 */
establish_link(struct udevice * dev)1827 static int establish_link(struct udevice *dev)
1828 {
1829 struct dp_tx *dp_tx = dev_get_priv(dev);
1830 int status;
1831 int status2;
1832 u32 mask;
1833
1834 reset_dp_phy(dev, PHY_CONFIG_PHY_RESET_MASK);
1835
1836 /* Disable main link during training. */
1837 disable_main_link(dev);
1838
1839 /* Wait for the PHY to be ready. */
1840 mask = phy_status_lanes_ready_mask(dp_tx->max_lane_count);
1841 status = wait_phy_ready(dev, mask);
1842 if (status)
1843 return -EIO;
1844
1845 /* Train main link. */
1846 status = run_training(dev);
1847
1848 /* Turn off the training pattern and enable scrambler. */
1849 status2 = set_training_pattern(dev, TRAINING_PATTERN_SET_OFF);
1850 if (status || status2)
1851 return -EIO;
1852
1853 return 0;
1854 }
1855
1856 /*
1857 * Stream policy maker
1858 */
1859
1860 /**
1861 * cfg_msa_recalculate() - Calculate MSA parameters
1862 * @dev: The LogiCore DP TX device in question
1863 *
1864 * Calculate the following Main Stream Attributes (MSA):
1865 * - Transfer unit size
1866 * - User pixel width
1867 * - Horizontal total clock
1868 * - Vertical total clock
1869 * - misc_0
1870 * - misc_1
1871 * - Data per lane
1872 * - Average number of bytes per transfer unit
1873 * - Number of initial wait cycles
1874 *
1875 * These values are derived from:
1876 * - Bits per color
1877 * - Horizontal resolution
1878 * - Vertical resolution
1879 * - Horizontal blank start
1880 * - Vertical blank start
1881 * - Pixel clock (in KHz)
1882 * - Horizontal sync polarity
1883 * - Vertical sync polarity
1884 * - Horizontal sync pulse width
1885 * - Vertical sync pulse width
1886 */
cfg_msa_recalculate(struct udevice * dev)1887 static void cfg_msa_recalculate(struct udevice *dev)
1888 {
1889 struct dp_tx *dp_tx = dev_get_priv(dev);
1890 u32 video_bw;
1891 u32 link_bw;
1892 u32 words_per_line;
1893 u8 bits_per_pixel;
1894 struct main_stream_attributes *msa_config;
1895 struct link_config *link_config;
1896
1897 msa_config = &dp_tx->main_stream_attributes;
1898 link_config = &dp_tx->link_config;
1899
1900 /*
1901 * Set the user pixel width to handle clocks that exceed the
1902 * capabilities of the DisplayPort TX core.
1903 */
1904 if (msa_config->override_user_pixel_width == 0) {
1905 if (msa_config->pixel_clock_hz > 300000000 &&
1906 link_config->lane_count == LANE_COUNT_SET_4) {
1907 msa_config->user_pixel_width = 4;
1908 } /*
1909 * Xilinx driver used 75 MHz as a limit here, 150 MHZ should
1910 * be more sane
1911 */
1912 else if ((msa_config->pixel_clock_hz > 150000000) &&
1913 (link_config->lane_count != LANE_COUNT_SET_1)) {
1914 msa_config->user_pixel_width = 2;
1915 } else {
1916 msa_config->user_pixel_width = 1;
1917 }
1918 }
1919
1920 /* Compute the rest of the MSA values. */
1921 msa_config->n_vid = 27 * 1000 * link_config->link_rate;
1922
1923 /* Miscellaneous attributes. */
1924 if (msa_config->bits_per_color == 6)
1925 msa_config->misc_0 = MAIN_STREAMX_MISC0_BDC_6BPC;
1926 else if (msa_config->bits_per_color == 8)
1927 msa_config->misc_0 = MAIN_STREAMX_MISC0_BDC_8BPC;
1928 else if (msa_config->bits_per_color == 10)
1929 msa_config->misc_0 = MAIN_STREAMX_MISC0_BDC_10BPC;
1930 else if (msa_config->bits_per_color == 12)
1931 msa_config->misc_0 = MAIN_STREAMX_MISC0_BDC_12BPC;
1932 else if (msa_config->bits_per_color == 16)
1933 msa_config->misc_0 = MAIN_STREAMX_MISC0_BDC_16BPC;
1934
1935 msa_config->misc_0 = (msa_config->misc_0 <<
1936 MAIN_STREAMX_MISC0_BDC_SHIFT) |
1937 (msa_config->y_cb_cr_colorimetry <<
1938 MAIN_STREAMX_MISC0_YCBCR_COLORIMETRY_SHIFT) |
1939 (msa_config->dynamic_range <<
1940 MAIN_STREAMX_MISC0_DYNAMIC_RANGE_SHIFT) |
1941 (msa_config->component_format <<
1942 MAIN_STREAMX_MISC0_COMPONENT_FORMAT_SHIFT) |
1943 (msa_config->synchronous_clock_mode);
1944
1945 msa_config->misc_1 = 0;
1946
1947 /*
1948 * Determine the number of bits per pixel for the specified color
1949 * component format.
1950 */
1951 if (msa_config->component_format ==
1952 MAIN_STREAMX_MISC0_COMPONENT_FORMAT_YCBCR422)
1953 /* YCbCr422 color component format. */
1954 bits_per_pixel = msa_config->bits_per_color * 2;
1955 else
1956 /* RGB or YCbCr 4:4:4 color component format. */
1957 bits_per_pixel = msa_config->bits_per_color * 3;
1958
1959 /* Calculate the data per lane. */
1960 words_per_line = (msa_config->h_active * bits_per_pixel);
1961 if (words_per_line % 16)
1962 words_per_line += 16;
1963 words_per_line /= 16;
1964
1965 msa_config->data_per_lane = words_per_line - link_config->lane_count;
1966 if (words_per_line % link_config->lane_count)
1967 msa_config->data_per_lane += (words_per_line %
1968 link_config->lane_count);
1969
1970 /*
1971 * Allocate a fixed size for single-stream transport (SST)
1972 * operation.
1973 */
1974 msa_config->transfer_unit_size = 64;
1975
1976 /*
1977 * Calculate the average number of bytes per transfer unit.
1978 * Note: Both the integer and the fractional part is stored in
1979 * avg_bytes_per_tu.
1980 */
1981 video_bw = ((msa_config->pixel_clock_hz / 1000) * bits_per_pixel) / 8;
1982 link_bw = (link_config->lane_count * link_config->link_rate * 27);
1983 msa_config->avg_bytes_per_tu = (video_bw *
1984 msa_config->transfer_unit_size) /
1985 link_bw;
1986
1987 /*
1988 * The number of initial wait cycles at the start of a new line
1989 * by the framing logic. This allows enough data to be buffered
1990 * in the input FIFO before video is sent.
1991 */
1992 if ((msa_config->avg_bytes_per_tu / 1000) <= 4)
1993 msa_config->init_wait = 64;
1994 else
1995 msa_config->init_wait = msa_config->transfer_unit_size -
1996 (msa_config->avg_bytes_per_tu / 1000);
1997 }
1998
1999 /**
2000 * set_line_reset() - Enable/Disable end-of-line-reset
2001 * @dev: The LogiCore DP TX device in question
2002 *
2003 * Disable/enable the end-of-line-reset to the internal video pipe in case of
2004 * reduced blanking as required.
2005 */
set_line_reset(struct udevice * dev)2006 static void set_line_reset(struct udevice *dev)
2007 {
2008 struct dp_tx *dp_tx = dev_get_priv(dev);
2009 u32 reg_val;
2010 u16 h_blank;
2011 u16 h_reduced_blank;
2012 struct main_stream_attributes *msa_config =
2013 &dp_tx->main_stream_attributes;
2014
2015 h_blank = msa_config->h_total - msa_config->h_active;
2016 /* Reduced blanking starts at ceil(0.2 * HTotal). */
2017 h_reduced_blank = 2 * msa_config->h_total;
2018 if (h_reduced_blank % 10)
2019 h_reduced_blank += 10;
2020 h_reduced_blank /= 10;
2021
2022 /* CVT spec. states h_blank is either 80 or 160 for reduced blanking. */
2023 reg_val = get_reg(dev, REG_LINE_RESET_DISABLE);
2024 if (h_blank < h_reduced_blank &&
2025 (h_blank == 80 || h_blank == 160)) {
2026 reg_val |= LINE_RESET_DISABLE_MASK;
2027 } else {
2028 reg_val &= ~LINE_RESET_DISABLE_MASK;
2029 }
2030 set_reg(dev, REG_LINE_RESET_DISABLE, reg_val);
2031 }
2032
2033 /**
2034 * clear_msa_values() - Clear MSA values
2035 * @dev: The LogiCore DP TX device in question
2036 *
2037 * Clear the main stream attributes registers of the DisplayPort TX core.
2038 */
clear_msa_values(struct udevice * dev)2039 static void clear_msa_values(struct udevice *dev)
2040 {
2041 set_reg(dev, REG_MAIN_STREAM_HTOTAL, 0);
2042 set_reg(dev, REG_MAIN_STREAM_VTOTAL, 0);
2043 set_reg(dev, REG_MAIN_STREAM_POLARITY, 0);
2044 set_reg(dev, REG_MAIN_STREAM_HSWIDTH, 0);
2045 set_reg(dev, REG_MAIN_STREAM_VSWIDTH, 0);
2046 set_reg(dev, REG_MAIN_STREAM_HRES, 0);
2047 set_reg(dev, REG_MAIN_STREAM_VRES, 0);
2048 set_reg(dev, REG_MAIN_STREAM_HSTART, 0);
2049 set_reg(dev, REG_MAIN_STREAM_VSTART, 0);
2050 set_reg(dev, REG_MAIN_STREAM_MISC0, 0);
2051 set_reg(dev, REG_MAIN_STREAM_MISC1, 0);
2052 set_reg(dev, REG_USER_PIXEL_WIDTH, 0);
2053 set_reg(dev, REG_USER_DATA_COUNT_PER_LANE, 0);
2054 set_reg(dev, REG_M_VID, 0);
2055 set_reg(dev, REG_N_VID, 0);
2056
2057 set_reg(dev, REG_STREAM1, 0);
2058 set_reg(dev, REG_TU_SIZE, 0);
2059 set_reg(dev, REG_MIN_BYTES_PER_TU, 0);
2060 set_reg(dev, REG_FRAC_BYTES_PER_TU, 0);
2061 set_reg(dev, REG_INIT_WAIT, 0);
2062 }
2063
2064 /**
2065 * set_msa_values() - Set MSA values
2066 * @dev: The LogiCore DP TX device in question
2067 *
2068 * Set the main stream attributes registers of the DisplayPort TX
2069 * core with the values specified in the main stream attributes configuration
2070 * structure.
2071 */
set_msa_values(struct udevice * dev)2072 static void set_msa_values(struct udevice *dev)
2073 {
2074 struct dp_tx *dp_tx = dev_get_priv(dev);
2075 struct main_stream_attributes *msa_config =
2076 &dp_tx->main_stream_attributes;
2077
2078 printf(" set MSA %u x %u\n", msa_config->h_active,
2079 msa_config->v_active);
2080
2081 set_reg(dev, REG_MAIN_STREAM_HTOTAL, msa_config->h_total);
2082 set_reg(dev, REG_MAIN_STREAM_VTOTAL, msa_config->v_total);
2083 set_reg(dev, REG_MAIN_STREAM_POLARITY,
2084 msa_config->h_sync_polarity |
2085 (msa_config->v_sync_polarity <<
2086 MAIN_STREAMX_POLARITY_VSYNC_POL_SHIFT));
2087 set_reg(dev, REG_MAIN_STREAM_HSWIDTH, msa_config->h_sync_width);
2088 set_reg(dev, REG_MAIN_STREAM_VSWIDTH, msa_config->v_sync_width);
2089 set_reg(dev, REG_MAIN_STREAM_HRES, msa_config->h_active);
2090 set_reg(dev, REG_MAIN_STREAM_VRES, msa_config->v_active);
2091 set_reg(dev, REG_MAIN_STREAM_HSTART, msa_config->h_start);
2092 set_reg(dev, REG_MAIN_STREAM_VSTART, msa_config->v_start);
2093 set_reg(dev, REG_MAIN_STREAM_MISC0, msa_config->misc_0);
2094 set_reg(dev, REG_MAIN_STREAM_MISC1, msa_config->misc_1);
2095 set_reg(dev, REG_USER_PIXEL_WIDTH, msa_config->user_pixel_width);
2096
2097 set_reg(dev, REG_M_VID, msa_config->pixel_clock_hz / 1000);
2098 set_reg(dev, REG_N_VID, msa_config->n_vid);
2099 set_reg(dev, REG_USER_DATA_COUNT_PER_LANE, msa_config->data_per_lane);
2100
2101 set_line_reset(dev);
2102
2103 set_reg(dev, REG_TU_SIZE, msa_config->transfer_unit_size);
2104 set_reg(dev, REG_MIN_BYTES_PER_TU, msa_config->avg_bytes_per_tu / 1000);
2105 set_reg(dev, REG_FRAC_BYTES_PER_TU,
2106 (msa_config->avg_bytes_per_tu % 1000) * 1024 / 1000);
2107 set_reg(dev, REG_INIT_WAIT, msa_config->init_wait);
2108 }
2109
2110 /*
2111 * external API
2112 */
2113
2114 /**
2115 * logicore_dp_tx_set_msa() - Set given MSA values on device
2116 * @dev: The LogiCore DP TX device in question
2117 * @msa: The MSA values to set for the device
2118 */
logicore_dp_tx_set_msa(struct udevice * dev,struct logicore_dp_tx_msa * msa)2119 static void logicore_dp_tx_set_msa(struct udevice *dev,
2120 struct logicore_dp_tx_msa *msa)
2121 {
2122 struct dp_tx *dp_tx = dev_get_priv(dev);
2123
2124 memset(&dp_tx->main_stream_attributes, 0,
2125 sizeof(struct main_stream_attributes));
2126
2127 dp_tx->main_stream_attributes.pixel_clock_hz = msa->pixel_clock_hz;
2128 dp_tx->main_stream_attributes.bits_per_color = msa->bits_per_color;
2129 dp_tx->main_stream_attributes.h_active = msa->h_active;
2130 dp_tx->main_stream_attributes.h_start = msa->h_start;
2131 dp_tx->main_stream_attributes.h_sync_polarity = msa->h_sync_polarity;
2132 dp_tx->main_stream_attributes.h_sync_width = msa->h_sync_width;
2133 dp_tx->main_stream_attributes.h_total = msa->h_total;
2134 dp_tx->main_stream_attributes.v_active = msa->v_active;
2135 dp_tx->main_stream_attributes.v_start = msa->v_start;
2136 dp_tx->main_stream_attributes.v_sync_polarity = msa->v_sync_polarity;
2137 dp_tx->main_stream_attributes.v_sync_width = msa->v_sync_width;
2138 dp_tx->main_stream_attributes.v_total = msa->v_total;
2139 dp_tx->main_stream_attributes.override_user_pixel_width =
2140 msa->override_user_pixel_width;
2141 dp_tx->main_stream_attributes.user_pixel_width = msa->user_pixel_width;
2142 dp_tx->main_stream_attributes.synchronous_clock_mode = 0;
2143 }
2144
2145 /**
2146 * logicore_dp_tx_video_enable() - Enable video output
2147 * @dev: The LogiCore DP TX device in question
2148 * @msa: The MSA values to set for the device
2149 *
2150 * Return: 0 if the video was enabled successfully, -ve on error
2151 */
logicore_dp_tx_video_enable(struct udevice * dev,struct logicore_dp_tx_msa * msa)2152 static int logicore_dp_tx_video_enable(struct udevice *dev,
2153 struct logicore_dp_tx_msa *msa)
2154 {
2155 struct dp_tx *dp_tx = dev_get_priv(dev);
2156 int res;
2157 u8 power = 0x01;
2158
2159 if (!is_connected(dev)) {
2160 printf(" no DP sink connected\n");
2161 return -EIO;
2162 }
2163
2164 initialize(dev);
2165
2166 disable_main_link(dev);
2167
2168 logicore_dp_tx_set_msa(dev, msa);
2169
2170 get_rx_capabilities(dev);
2171
2172 printf(" DP sink connected\n");
2173 aux_write(dev, DPCD_SET_POWER_DP_PWR_VOLTAGE, 1, &power);
2174 set_enhanced_frame_mode(dev, true);
2175 cfg_main_link_max(dev);
2176 res = establish_link(dev);
2177 printf(" establish_link: %s, vs: %d, pe: %d\n",
2178 res ? "failed" : "ok", dp_tx->link_config.vs_level,
2179 dp_tx->link_config.pe_level);
2180
2181 cfg_msa_recalculate(dev);
2182
2183 clear_msa_values(dev);
2184 set_msa_values(dev);
2185
2186 enable_main_link(dev);
2187
2188 return 0;
2189 }
2190
2191 /*
2192 * Driver functions
2193 */
2194
logicore_dp_tx_enable(struct udevice * dev,int panel_bpp,const struct display_timing * timing)2195 static int logicore_dp_tx_enable(struct udevice *dev, int panel_bpp,
2196 const struct display_timing *timing)
2197 {
2198 struct clk pixclock;
2199 struct logicore_dp_tx_msa *msa;
2200 struct logicore_dp_tx_msa mode_640_480_60 = {
2201 .pixel_clock_hz = 25175000,
2202 .bits_per_color = 8,
2203 .h_active = 640,
2204 .h_start = 144,
2205 .h_sync_polarity = false,
2206 .h_sync_width = 96,
2207 .h_total = 800,
2208 .v_active = 480,
2209 .v_start = 35,
2210 .v_sync_polarity = false,
2211 .v_sync_width = 2,
2212 .v_total = 525,
2213 .override_user_pixel_width = false,
2214 .user_pixel_width = 0,
2215 };
2216
2217 struct logicore_dp_tx_msa mode_720_400_70 = {
2218 .pixel_clock_hz = 28300000,
2219 .bits_per_color = 8,
2220 .h_active = 720,
2221 .h_start = 162,
2222 .h_sync_polarity = false,
2223 .h_sync_width = 108,
2224 .h_total = 900,
2225 .v_active = 400,
2226 .v_start = 37,
2227 .v_sync_polarity = true,
2228 .v_sync_width = 2,
2229 .v_total = 449,
2230 .override_user_pixel_width = false,
2231 .user_pixel_width = 0,
2232 };
2233
2234 struct logicore_dp_tx_msa mode_1024_768_60 = {
2235 .pixel_clock_hz = 65000000,
2236 .bits_per_color = 8,
2237 .h_active = 1024,
2238 .h_start = 296,
2239 .h_sync_polarity = false,
2240 .h_sync_width = 136,
2241 .h_total = 1344,
2242 .v_active = 768,
2243 .v_start = 35,
2244 .v_sync_polarity = false,
2245 .v_sync_width = 2,
2246 .v_total = 806,
2247 .override_user_pixel_width = false,
2248 .user_pixel_width = 0,
2249 };
2250
2251 if (timing->hactive.typ == 1024 && timing->vactive.typ == 768)
2252 msa = &mode_1024_768_60;
2253 else if (timing->hactive.typ == 720 && timing->vactive.typ == 400)
2254 msa = &mode_720_400_70;
2255 else
2256 msa = &mode_640_480_60;
2257
2258 if (clk_get_by_index(dev, 0, &pixclock)) {
2259 printf("%s: Could not get pixelclock\n", dev->name);
2260 return -1;
2261 }
2262 clk_set_rate(&pixclock, msa->pixel_clock_hz);
2263
2264 return logicore_dp_tx_video_enable(dev, msa);
2265 }
2266
logicore_dp_tx_probe(struct udevice * dev)2267 static int logicore_dp_tx_probe(struct udevice *dev)
2268 {
2269 struct dp_tx *dp_tx = dev_get_priv(dev);
2270
2271 dp_tx->s_axi_clk = S_AXI_CLK_DEFAULT;
2272 dp_tx->train_adaptive = false;
2273 dp_tx->max_link_rate = DPCD_MAX_LINK_RATE_540GBPS;
2274 dp_tx->max_lane_count = DPCD_MAX_LANE_COUNT_4;
2275
2276 dp_tx->base = dev_read_u32_default(dev, "reg", -1);
2277
2278 return 0;
2279 }
2280
2281 static const struct dm_display_ops logicore_dp_tx_ops = {
2282 .enable = logicore_dp_tx_enable,
2283 };
2284
2285 static const struct udevice_id logicore_dp_tx_ids[] = {
2286 { .compatible = "gdsys,logicore_dp_tx" },
2287 { /* sentinel */ }
2288 };
2289
2290 U_BOOT_DRIVER(logicore_dp_tx) = {
2291 .name = "logicore_dp_tx",
2292 .id = UCLASS_DISPLAY,
2293 .of_match = logicore_dp_tx_ids,
2294 .probe = logicore_dp_tx_probe,
2295 .priv_auto = sizeof(struct dp_tx),
2296 .ops = &logicore_dp_tx_ops,
2297 };
2298