1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2017, Fuzhou Rockchip Electronics Co., Ltd
4 * Author: Eric Gao <eric.gao@rock-chips.com>
5 */
6
7 #include <common.h>
8 #include <clk.h>
9 #include <display.h>
10 #include <dm.h>
11 #include <log.h>
12 #include <panel.h>
13 #include <regmap.h>
14 #include "rk_mipi.h"
15 #include <syscon.h>
16 #include <asm/gpio.h>
17 #include <asm/io.h>
18 #include <dm/uclass-internal.h>
19 #include <linux/err.h>
20 #include <linux/kernel.h>
21 #include <asm/arch-rockchip/clock.h>
22 #include <asm/arch-rockchip/cru.h>
23 #include <asm/arch-rockchip/grf_rk3399.h>
24 #include <asm/arch-rockchip/hardware.h>
25 #include <asm/arch-rockchip/rockchip_mipi_dsi.h>
26
27 /* Select mipi dsi source, big or little vop */
rk_mipi_dsi_source_select(struct udevice * dev)28 static int rk_mipi_dsi_source_select(struct udevice *dev)
29 {
30 struct rk_mipi_priv *priv = dev_get_priv(dev);
31 struct rk3399_grf_regs *grf = priv->grf;
32 struct display_plat *disp_uc_plat = dev_get_uclass_plat(dev);
33
34 /* Select the video source */
35 switch (disp_uc_plat->source_id) {
36 case VOP_B:
37 rk_clrsetreg(&grf->soc_con20, GRF_DSI0_VOP_SEL_MASK,
38 GRF_DSI0_VOP_SEL_B << GRF_DSI0_VOP_SEL_SHIFT);
39 break;
40 case VOP_L:
41 rk_clrsetreg(&grf->soc_con20, GRF_DSI0_VOP_SEL_MASK,
42 GRF_DSI0_VOP_SEL_L << GRF_DSI0_VOP_SEL_SHIFT);
43 break;
44 default:
45 debug("%s: Invalid VOP id\n", __func__);
46 return -EINVAL;
47 }
48
49 return 0;
50 }
51
52 /* Setup mipi dphy working mode */
rk_mipi_dphy_mode_set(struct udevice * dev)53 static void rk_mipi_dphy_mode_set(struct udevice *dev)
54 {
55 struct rk_mipi_priv *priv = dev_get_priv(dev);
56 struct rk3399_grf_regs *grf = priv->grf;
57 int val;
58
59 /* Set Controller as TX mode */
60 val = GRF_DPHY_TX0_RXMODE_DIS << GRF_DPHY_TX0_RXMODE_SHIFT;
61 rk_clrsetreg(&grf->soc_con22, GRF_DPHY_TX0_RXMODE_MASK, val);
62
63 /* Exit tx stop mode */
64 val |= GRF_DPHY_TX0_TXSTOPMODE_DIS << GRF_DPHY_TX0_TXSTOPMODE_SHIFT;
65 rk_clrsetreg(&grf->soc_con22, GRF_DPHY_TX0_TXSTOPMODE_MASK, val);
66
67 /* Disable turnequest */
68 val |= GRF_DPHY_TX0_TURNREQUEST_DIS << GRF_DPHY_TX0_TURNREQUEST_SHIFT;
69 rk_clrsetreg(&grf->soc_con22, GRF_DPHY_TX0_TURNREQUEST_MASK, val);
70 }
71
72 /*
73 * This function is called by rk_display_init() using rk_mipi_dsi_enable() and
74 * rk_mipi_phy_enable() to initialize mipi controller and dphy. If success,
75 * enable backlight.
76 */
rk_display_enable(struct udevice * dev,int panel_bpp,const struct display_timing * timing)77 static int rk_display_enable(struct udevice *dev, int panel_bpp,
78 const struct display_timing *timing)
79 {
80 int ret;
81 struct rk_mipi_priv *priv = dev_get_priv(dev);
82
83 /* Fill the mipi controller parameter */
84 priv->ref_clk = 24 * MHz;
85 priv->sys_clk = priv->ref_clk;
86 priv->pix_clk = timing->pixelclock.typ;
87 priv->phy_clk = priv->pix_clk * 6;
88 priv->txbyte_clk = priv->phy_clk / 8;
89 priv->txesc_clk = 20 * MHz;
90
91 /* Select vop port, big or little */
92 rk_mipi_dsi_source_select(dev);
93
94 /* Set mipi dphy work mode */
95 rk_mipi_dphy_mode_set(dev);
96
97 /* Config and enable mipi dsi according to timing */
98 ret = rk_mipi_dsi_enable(dev, timing);
99 if (ret) {
100 debug("%s: rk_mipi_dsi_enable() failed (err=%d)\n",
101 __func__, ret);
102 return ret;
103 }
104
105 /* Config and enable mipi phy */
106 ret = rk_mipi_phy_enable(dev);
107 if (ret) {
108 debug("%s: rk_mipi_phy_enable() failed (err=%d)\n",
109 __func__, ret);
110 return ret;
111 }
112
113 /* Enable backlight */
114 ret = panel_enable_backlight(priv->panel);
115 if (ret) {
116 debug("%s: panel_enable_backlight() failed (err=%d)\n",
117 __func__, ret);
118 return ret;
119 }
120
121 return 0;
122 }
123
rk_mipi_of_to_plat(struct udevice * dev)124 static int rk_mipi_of_to_plat(struct udevice *dev)
125 {
126 struct rk_mipi_priv *priv = dev_get_priv(dev);
127
128 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
129 if (IS_ERR_OR_NULL(priv->grf)) {
130 debug("%s: Get syscon grf failed (ret=%p)\n",
131 __func__, priv->grf);
132 return -ENXIO;
133 }
134 priv->regs = dev_read_addr(dev);
135 if (priv->regs == FDT_ADDR_T_NONE) {
136 debug("%s: Get MIPI dsi address failed\n", __func__);
137 return -ENXIO;
138 }
139
140 return 0;
141 }
142
143 /*
144 * Probe function: check panel existence and readingit's timing. Then config
145 * mipi dsi controller and enable it according to the timing parameter.
146 */
rk_mipi_probe(struct udevice * dev)147 static int rk_mipi_probe(struct udevice *dev)
148 {
149 int ret;
150 struct rk_mipi_priv *priv = dev_get_priv(dev);
151
152 ret = uclass_get_device_by_phandle(UCLASS_PANEL, dev, "rockchip,panel",
153 &priv->panel);
154 if (ret) {
155 debug("%s: Can not find panel (err=%d)\n", __func__, ret);
156 return ret;
157 }
158
159 return 0;
160 }
161
162 static const struct dm_display_ops rk_mipi_dsi_ops = {
163 .read_timing = rk_mipi_read_timing,
164 .enable = rk_display_enable,
165 };
166
167 static const struct udevice_id rk_mipi_dsi_ids[] = {
168 { .compatible = "rockchip,rk3399_mipi_dsi" },
169 { }
170 };
171
172 U_BOOT_DRIVER(rk_mipi_dsi) = {
173 .name = "rk_mipi_dsi",
174 .id = UCLASS_DISPLAY,
175 .of_match = rk_mipi_dsi_ids,
176 .of_to_plat = rk_mipi_of_to_plat,
177 .probe = rk_mipi_probe,
178 .ops = &rk_mipi_dsi_ops,
179 .priv_auto = sizeof(struct rk_mipi_priv),
180 };
181