1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2011 Andes Technology Corporation 4 * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com> 5 * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> 6 */ 7 8 #ifndef __CONFIG_H 9 #define __CONFIG_H 10 11 #include <asm/arch-ag101/ag101.h> 12 13 /* 14 * CPU and Board Configuration Options 15 */ 16 #define CONFIG_USE_INTERRUPT 17 18 #define CONFIG_SKIP_LOWLEVEL_INIT 19 20 #define CONFIG_ARCH_MAP_SYSMEM 21 22 #define CONFIG_BOOTP_SERVERIP 23 24 #ifndef CONFIG_SKIP_LOWLEVEL_INIT 25 #define CONFIG_MEM_REMAP 26 #endif 27 28 #ifdef CONFIG_SKIP_LOWLEVEL_INIT 29 #ifdef CONFIG_OF_CONTROL 30 #undef CONFIG_OF_SEPARATE 31 #define CONFIG_OF_EMBED 32 #endif 33 #endif 34 35 /* 36 * Timer 37 */ 38 #define CONFIG_SYS_CLK_FREQ 39062500 39 #define VERSION_CLOCK CONFIG_SYS_CLK_FREQ 40 41 /* 42 * Use Externel CLOCK or PCLK 43 */ 44 #undef CONFIG_FTRTC010_EXTCLK 45 46 #ifndef CONFIG_FTRTC010_EXTCLK 47 #define CONFIG_FTRTC010_PCLK 48 #endif 49 50 #ifdef CONFIG_FTRTC010_EXTCLK 51 #define TIMER_CLOCK 32768 /* CONFIG_FTRTC010_EXTCLK */ 52 #else 53 #define TIMER_CLOCK CONFIG_SYS_HZ /* CONFIG_FTRTC010_PCLK */ 54 #endif 55 56 #define TIMER_LOAD_VAL 0xffffffff 57 58 /* 59 * Real Time Clock 60 */ 61 #define CONFIG_RTC_FTRTC010 62 63 /* 64 * Real Time Clock Divider 65 * RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ) 66 */ 67 #define OSC_5MHZ (5*1000000) 68 #define OSC_CLK (4*OSC_5MHZ) 69 #define RTC_DIV_COUNT (0.5) /* Why?? */ 70 71 /* 72 * Serial console configuration 73 */ 74 75 /* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */ 76 #define CONFIG_SYS_NS16550_SERIAL 77 #define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_02_BASE 78 #ifndef CONFIG_DM_SERIAL 79 #define CONFIG_SYS_NS16550_REG_SIZE -4 80 #endif 81 #define CONFIG_SYS_NS16550_CLK ((18432000 * 20) / 25) /* AG101P */ 82 83 /* 84 * Miscellaneous configurable options 85 */ 86 87 /* 88 * Size of malloc() pool 89 */ 90 /* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */ 91 #define CONFIG_SYS_MALLOC_LEN (512 << 10) 92 93 /* 94 * AHB Controller configuration 95 */ 96 #define CONFIG_FTAHBC020S 97 98 #ifdef CONFIG_FTAHBC020S 99 #include <faraday/ftahbc020s.h> 100 101 /* Address of PHYS_SDRAM_0 before memory remap is at 0x(100)00000 */ 102 #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE 0x100 103 104 /* 105 * CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6: this define is used in lowlevel_init.S, 106 * hence we cannot use FTAHBC020S_BSR_SIZE(2048) since it will use ffs() wrote 107 * in C language. 108 */ 109 #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 \ 110 (FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) | \ 111 FTAHBC020S_SLAVE_BSR_SIZE(0xb)) 112 #endif 113 114 /* 115 * Watchdog 116 */ 117 #define CONFIG_FTWDT010_WATCHDOG 118 119 /* 120 * PMU Power controller configuration 121 */ 122 #define CONFIG_PMU 123 #define CONFIG_FTPMU010_POWER 124 125 #ifdef CONFIG_FTPMU010_POWER 126 #include <faraday/ftpmu010.h> 127 #define CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS 0x0E 128 #define CONFIG_SYS_FTPMU010_SDRAMHTC (FTPMU010_SDRAMHTC_EBICTRL_DCSR | \ 129 FTPMU010_SDRAMHTC_EBIDATA_DCSR | \ 130 FTPMU010_SDRAMHTC_SDRAMCS_DCSR | \ 131 FTPMU010_SDRAMHTC_SDRAMCTL_DCSR | \ 132 FTPMU010_SDRAMHTC_CKE_DCSR | \ 133 FTPMU010_SDRAMHTC_DQM_DCSR | \ 134 FTPMU010_SDRAMHTC_SDCLK_DCSR) 135 #endif 136 137 /* 138 * SDRAM controller configuration 139 */ 140 #define CONFIG_FTSDMC021 141 142 #ifdef CONFIG_FTSDMC021 143 #include <faraday/ftsdmc021.h> 144 145 #define CONFIG_SYS_FTSDMC021_TP1 (FTSDMC021_TP1_TRAS(2) | \ 146 FTSDMC021_TP1_TRP(1) | \ 147 FTSDMC021_TP1_TRCD(1) | \ 148 FTSDMC021_TP1_TRF(3) | \ 149 FTSDMC021_TP1_TWR(1) | \ 150 FTSDMC021_TP1_TCL(2)) 151 152 #define CONFIG_SYS_FTSDMC021_TP2 (FTSDMC021_TP2_INI_PREC(4) | \ 153 FTSDMC021_TP2_INI_REFT(8) | \ 154 FTSDMC021_TP2_REF_INTV(0x180)) 155 156 /* 157 * CONFIG_SYS_FTSDMC021_CR1: this define is used in lowlevel_init.S, 158 * hence we cannot use FTSDMC021_BANK_SIZE(64) since it will use ffs() wrote in 159 * C language. 160 */ 161 #define CONFIG_SYS_FTSDMC021_CR1 (FTSDMC021_CR1_DDW(2) | \ 162 FTSDMC021_CR1_DSZ(3) | \ 163 FTSDMC021_CR1_MBW(2) | \ 164 FTSDMC021_CR1_BNKSIZE(6)) 165 166 #define CONFIG_SYS_FTSDMC021_CR2 (FTSDMC021_CR2_IPREC | \ 167 FTSDMC021_CR2_IREF | \ 168 FTSDMC021_CR2_ISMR) 169 170 #define CONFIG_SYS_FTSDMC021_BANK0_BASE CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE 171 #define CONFIG_SYS_FTSDMC021_BANK0_BSR (FTSDMC021_BANK_ENABLE | \ 172 CONFIG_SYS_FTSDMC021_BANK0_BASE) 173 174 #define CONFIG_SYS_FTSDMC021_BANK1_BASE \ 175 (CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE + (PHYS_SDRAM_0_SIZE >> 20)) 176 #define CONFIG_SYS_FTSDMC021_BANK1_BSR (FTSDMC021_BANK_ENABLE | \ 177 CONFIG_SYS_FTSDMC021_BANK1_BASE) 178 #endif 179 180 /* 181 * Physical Memory Map 182 */ 183 #ifdef CONFIG_SKIP_LOWLEVEL_INIT 184 #define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */ 185 #else 186 #ifdef CONFIG_MEM_REMAP 187 #define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */ 188 #else 189 #define PHYS_SDRAM_0 0x80000000 /* SDRAM Bank #1 */ 190 #endif 191 #endif 192 193 #define PHYS_SDRAM_1 \ 194 (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */ 195 196 #ifdef CONFIG_SKIP_LOWLEVEL_INIT 197 #define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */ 198 #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */ 199 #else 200 #ifdef CONFIG_MEM_REMAP 201 #define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */ 202 #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */ 203 #else 204 #define PHYS_SDRAM_0_SIZE 0x08000000 /* 128 MB */ 205 #define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ 206 #endif 207 #endif 208 209 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0 210 211 #ifdef CONFIG_MEM_REMAP 212 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \ 213 GENERATED_GBL_DATA_SIZE) 214 #else 215 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \ 216 GENERATED_GBL_DATA_SIZE) 217 #endif /* CONFIG_MEM_REMAP */ 218 219 /* 220 * Load address and memory test area should agree with 221 * arch/nds32/config.mk. Be careful not to overwrite U-Boot itself. 222 */ 223 #define CONFIG_SYS_LOAD_ADDR 0x300000 224 225 /* memtest works on 63 MB in DRAM */ 226 227 /* 228 * Static memory controller configuration 229 */ 230 #define CONFIG_FTSMC020 231 232 #ifdef CONFIG_FTSMC020 233 #include <faraday/ftsmc020.h> 234 235 #define CONFIG_SYS_FTSMC020_CONFIGS { \ 236 { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \ 237 { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \ 238 } 239 240 #ifndef CONFIG_SKIP_LOWLEVEL_INIT /* FLASH is on BANK 0 */ 241 #define FTSMC020_BANK0_LOWLV_CONFIG (FTSMC020_BANK_ENABLE | \ 242 FTSMC020_BANK_SIZE_32M | \ 243 FTSMC020_BANK_MBW_32) 244 245 #define FTSMC020_BANK0_LOWLV_TIMING (FTSMC020_TPR_RBE | \ 246 FTSMC020_TPR_AST(1) | \ 247 FTSMC020_TPR_CTW(1) | \ 248 FTSMC020_TPR_ATI(1) | \ 249 FTSMC020_TPR_AT2(1) | \ 250 FTSMC020_TPR_WTC(1) | \ 251 FTSMC020_TPR_AHT(1) | \ 252 FTSMC020_TPR_TRNA(1)) 253 #endif 254 255 /* 256 * FLASH on ADP_AG101P is connected to BANK0 257 * Just disalbe the other BANK to avoid detection error. 258 */ 259 #define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \ 260 FTSMC020_BANK_BASE(PHYS_FLASH_1) | \ 261 FTSMC020_BANK_SIZE_32M | \ 262 FTSMC020_BANK_MBW_32) 263 264 #define FTSMC020_BANK0_TIMING (FTSMC020_TPR_AST(3) | \ 265 FTSMC020_TPR_CTW(3) | \ 266 FTSMC020_TPR_ATI(0xf) | \ 267 FTSMC020_TPR_AT2(3) | \ 268 FTSMC020_TPR_WTC(3) | \ 269 FTSMC020_TPR_AHT(3) | \ 270 FTSMC020_TPR_TRNA(0xf)) 271 272 #define FTSMC020_BANK1_CONFIG (0x00) 273 #define FTSMC020_BANK1_TIMING (0x00) 274 #endif /* CONFIG_FTSMC020 */ 275 276 /* 277 * FLASH and environment organization 278 */ 279 /* use CFI framework */ 280 281 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 282 #define CONFIG_SYS_CFI_FLASH_STATUS_POLL 283 284 /* support JEDEC */ 285 286 /* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */ 287 #ifdef CONFIG_SKIP_LOWLEVEL_INIT 288 #define PHYS_FLASH_1 0x80000000 /* BANK 0 */ 289 #else 290 #ifdef CONFIG_MEM_REMAP 291 #define PHYS_FLASH_1 0x80000000 /* BANK 0 */ 292 #else 293 #define PHYS_FLASH_1 0x00000000 /* BANK 0 */ 294 #endif 295 #endif /* CONFIG_MEM_REMAP */ 296 297 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 298 #define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, } 299 #define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 300 301 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */ 302 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */ 303 304 /* max number of memory banks */ 305 /* 306 * There are 4 banks supported for this Controller, 307 * but we have only 1 bank connected to flash on board 308 */ 309 #ifndef CONFIG_SYS_MAX_FLASH_BANKS_DETECT 310 #define CONFIG_SYS_MAX_FLASH_BANKS 1 311 #endif 312 #define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000} 313 314 /* max number of sectors on one chip */ 315 #define CONFIG_FLASH_SECTOR_SIZE (0x10000*2) 316 #define CONFIG_SYS_MAX_FLASH_SECT 512 317 318 /* environments */ 319 320 /* 321 * For booting Linux, the board info and command line data 322 * have to be in the first 16 MB of memory, since this is 323 * the maximum mapped by the Linux kernel during initialization. 324 */ 325 326 /* Initial Memory map for Linux*/ 327 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) 328 /* Increase max gunzip size */ 329 #define CONFIG_SYS_BOOTM_LEN (64 << 20) 330 331 #endif /* __CONFIG_H */ 332