1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2013 Boundary Devices Inc. 4 */ 5 #ifndef __ASM_ARCH_MX6Q_DDR_H__ 6 #define __ASM_ARCH_MX6Q_DDR_H__ 7 8 #ifndef CONFIG_MX6Q 9 #error "wrong CPU" 10 #endif 11 12 #define MX6_IOM_DRAM_DQM0 0x020e05ac 13 #define MX6_IOM_DRAM_DQM1 0x020e05b4 14 #define MX6_IOM_DRAM_DQM2 0x020e0528 15 #define MX6_IOM_DRAM_DQM3 0x020e0520 16 #define MX6_IOM_DRAM_DQM4 0x020e0514 17 #define MX6_IOM_DRAM_DQM5 0x020e0510 18 #define MX6_IOM_DRAM_DQM6 0x020e05bc 19 #define MX6_IOM_DRAM_DQM7 0x020e05c4 20 21 #define MX6_IOM_DRAM_CAS 0x020e056c 22 #define MX6_IOM_DRAM_RAS 0x020e0578 23 #define MX6_IOM_DRAM_RESET 0x020e057c 24 #define MX6_IOM_DRAM_SDCLK_0 0x020e0588 25 #define MX6_IOM_DRAM_SDCLK_1 0x020e0594 26 #define MX6_IOM_DRAM_SDBA2 0x020e058c 27 #define MX6_IOM_DRAM_SDCKE0 0x020e0590 28 #define MX6_IOM_DRAM_SDCKE1 0x020e0598 29 #define MX6_IOM_DRAM_SDODT0 0x020e059c 30 #define MX6_IOM_DRAM_SDODT1 0x020e05a0 31 32 #define MX6_IOM_DRAM_SDQS0 0x020e05a8 33 #define MX6_IOM_DRAM_SDQS1 0x020e05b0 34 #define MX6_IOM_DRAM_SDQS2 0x020e0524 35 #define MX6_IOM_DRAM_SDQS3 0x020e051c 36 #define MX6_IOM_DRAM_SDQS4 0x020e0518 37 #define MX6_IOM_DRAM_SDQS5 0x020e050c 38 #define MX6_IOM_DRAM_SDQS6 0x020e05b8 39 #define MX6_IOM_DRAM_SDQS7 0x020e05c0 40 41 #define MX6_IOM_GRP_B0DS 0x020e0784 42 #define MX6_IOM_GRP_B1DS 0x020e0788 43 #define MX6_IOM_GRP_B2DS 0x020e0794 44 #define MX6_IOM_GRP_B3DS 0x020e079c 45 #define MX6_IOM_GRP_B4DS 0x020e07a0 46 #define MX6_IOM_GRP_B5DS 0x020e07a4 47 #define MX6_IOM_GRP_B6DS 0x020e07a8 48 #define MX6_IOM_GRP_B7DS 0x020e0748 49 #define MX6_IOM_GRP_ADDDS 0x020e074c 50 #define MX6_IOM_DDRMODE_CTL 0x020e0750 51 #define MX6_IOM_GRP_DDRPKE 0x020e0758 52 #define MX6_IOM_GRP_DDRMODE 0x020e0774 53 #define MX6_IOM_GRP_CTLDS 0x020e078c 54 #define MX6_IOM_GRP_DDR_TYPE 0x020e0798 55 56 #endif /*__ASM_ARCH_MX6Q_DDR_H__ */ 57