1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * [origin: Linux kernel linux/arch/arm/mach-at91/clock.c]
4 *
5 * Copyright (C) 2005 David Brownell
6 * Copyright (C) 2005 Ivan Kokshaysky
7 * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
8 * Copyright (C) 2013 Bo Shen <voice.shen@atmel.com>
9 * Copyright (C) 2015 Wenyou Yang <wenyou.yang@atmel.com>
10 */
11
12 #include <common.h>
13 #include <asm/global_data.h>
14 #include <linux/delay.h>
15 #include <linux/errno.h>
16 #include <asm/io.h>
17 #include <asm/arch/hardware.h>
18 #include <asm/arch/at91_pmc.h>
19 #include <asm/arch/clk.h>
20
21 #if !defined(CONFIG_AT91FAMILY)
22 # error You need to define CONFIG_AT91FAMILY in your board config!
23 #endif
24
25 DECLARE_GLOBAL_DATA_PTR;
26
at91_css_to_rate(unsigned long css)27 static unsigned long at91_css_to_rate(unsigned long css)
28 {
29 switch (css) {
30 case AT91_PMC_MCKR_CSS_SLOW:
31 return CONFIG_SYS_AT91_SLOW_CLOCK;
32 case AT91_PMC_MCKR_CSS_MAIN:
33 return gd->arch.main_clk_rate_hz;
34 case AT91_PMC_MCKR_CSS_PLLA:
35 return gd->arch.plla_rate_hz;
36 }
37
38 return 0;
39 }
40
at91_pll_rate(u32 freq,u32 reg)41 static u32 at91_pll_rate(u32 freq, u32 reg)
42 {
43 unsigned mul, div;
44
45 div = reg & 0xff;
46 mul = (reg >> 18) & 0x7f;
47 if (div && mul) {
48 freq /= div;
49 freq *= mul + 1;
50 } else {
51 freq = 0;
52 }
53
54 return freq;
55 }
56
at91_clock_init(unsigned long main_clock)57 int at91_clock_init(unsigned long main_clock)
58 {
59 unsigned freq, mckr;
60 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
61 #ifndef CONFIG_SYS_AT91_MAIN_CLOCK
62 unsigned tmp;
63 /*
64 * When the bootloader initialized the main oscillator correctly,
65 * there's no problem using the cycle counter. But if it didn't,
66 * or when using oscillator bypass mode, we must be told the speed
67 * of the main clock.
68 */
69 if (!main_clock) {
70 do {
71 tmp = readl(&pmc->mcfr);
72 } while (!(tmp & AT91_PMC_MCFR_MAINRDY));
73 tmp &= AT91_PMC_MCFR_MAINF_MASK;
74 main_clock = tmp * (CONFIG_SYS_AT91_SLOW_CLOCK / 16);
75 }
76 #endif
77 gd->arch.main_clk_rate_hz = main_clock;
78
79 /* report if PLLA is more than mildly overclocked */
80 gd->arch.plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar));
81
82 /*
83 * MCK and CPU derive from one of those primary clocks.
84 * For now, assume this parentage won't change.
85 */
86 mckr = readl(&pmc->mckr);
87
88 /* plla divisor by 2 */
89 if (mckr & (1 << 12))
90 gd->arch.plla_rate_hz >>= 1;
91
92 gd->arch.mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK);
93 freq = gd->arch.mck_rate_hz;
94
95 /* prescale */
96 freq >>= mckr & AT91_PMC_MCKR_PRES_MASK;
97
98 switch (mckr & AT91_PMC_MCKR_MDIV_MASK) {
99 case AT91_PMC_MCKR_MDIV_2:
100 gd->arch.mck_rate_hz = freq / 2;
101 break;
102 case AT91_PMC_MCKR_MDIV_3:
103 gd->arch.mck_rate_hz = freq / 3;
104 break;
105 case AT91_PMC_MCKR_MDIV_4:
106 gd->arch.mck_rate_hz = freq / 4;
107 break;
108 default:
109 break;
110 }
111
112 gd->arch.cpu_clk_rate_hz = freq;
113
114 return 0;
115 }
116
at91_plla_init(u32 pllar)117 void at91_plla_init(u32 pllar)
118 {
119 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
120
121 writel(pllar, &pmc->pllar);
122 while (!(readl(&pmc->sr) & (AT91_PMC_LOCKA | AT91_PMC_MCKRDY)))
123 ;
124 }
125
at91_mck_init(u32 mckr)126 void at91_mck_init(u32 mckr)
127 {
128 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
129 u32 tmp;
130
131 tmp = readl(&pmc->mckr);
132 tmp &= ~(AT91_PMC_MCKR_CSS_MASK |
133 AT91_PMC_MCKR_PRES_MASK |
134 AT91_PMC_MCKR_MDIV_MASK |
135 AT91_PMC_MCKR_PLLADIV_2);
136 #ifdef CPU_HAS_H32MXDIV
137 tmp &= ~AT91_PMC_MCKR_H32MXDIV;
138 #endif
139
140 tmp |= mckr & (AT91_PMC_MCKR_CSS_MASK |
141 AT91_PMC_MCKR_PRES_MASK |
142 AT91_PMC_MCKR_MDIV_MASK |
143 AT91_PMC_MCKR_PLLADIV_2);
144 #ifdef CPU_HAS_H32MXDIV
145 tmp |= mckr & AT91_PMC_MCKR_H32MXDIV;
146 #endif
147
148 writel(tmp, &pmc->mckr);
149
150 while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
151 ;
152 }
153
154 /*
155 * For the Master Clock Controller Register(MCKR), while switching
156 * to a lower clock source, we must switch the clock source first
157 * instead of last. Otherwise, we could end up with too high frequency
158 * on the internal bus and peripherals.
159 */
at91_mck_init_down(u32 mckr)160 void at91_mck_init_down(u32 mckr)
161 {
162 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
163 u32 tmp;
164
165 tmp = readl(&pmc->mckr);
166 tmp &= (~AT91_PMC_MCKR_CSS_MASK);
167 tmp |= (mckr & AT91_PMC_MCKR_CSS_MASK);
168 writel(tmp, &pmc->mckr);
169
170 while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
171 ;
172
173 #ifdef CPU_HAS_H32MXDIV
174 tmp = readl(&pmc->mckr);
175 tmp &= (~AT91_PMC_MCKR_H32MXDIV);
176 tmp |= (mckr & AT91_PMC_MCKR_H32MXDIV);
177 writel(tmp, &pmc->mckr);
178 #endif
179
180 tmp = readl(&pmc->mckr);
181 tmp &= (~AT91_PMC_MCKR_PLLADIV_MASK);
182 tmp |= (mckr & AT91_PMC_MCKR_PLLADIV_MASK);
183 writel(tmp, &pmc->mckr);
184
185 tmp = readl(&pmc->mckr);
186 tmp &= (~AT91_PMC_MCKR_MDIV_MASK);
187 tmp |= (mckr & AT91_PMC_MCKR_MDIV_MASK);
188 writel(tmp, &pmc->mckr);
189
190 tmp = readl(&pmc->mckr);
191 tmp &= (~AT91_PMC_MCKR_PRES_MASK);
192 tmp |= (mckr & AT91_PMC_MCKR_PRES_MASK);
193 writel(tmp, &pmc->mckr);
194 }
195
at91_enable_periph_generated_clk(u32 id,u32 clk_source,u32 div)196 int at91_enable_periph_generated_clk(u32 id, u32 clk_source, u32 div)
197 {
198 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
199 u32 regval, status;
200 u32 timeout = 1000;
201
202 if (id > AT91_PMC_PCR_PID_MASK)
203 return -EINVAL;
204
205 if (div > 0xff)
206 return -EINVAL;
207
208 if (clk_source == GCK_CSS_UPLL_CLK) {
209 if (at91_upll_clk_enable())
210 return -ENODEV;
211 }
212
213 writel(id, &pmc->pcr);
214 regval = readl(&pmc->pcr);
215 regval &= ~AT91_PMC_PCR_GCKCSS;
216 regval &= ~AT91_PMC_PCR_GCKDIV;
217
218 switch (clk_source) {
219 case GCK_CSS_SLOW_CLK:
220 regval |= AT91_PMC_PCR_GCKCSS_SLOW_CLK;
221 break;
222 case GCK_CSS_MAIN_CLK:
223 regval |= AT91_PMC_PCR_GCKCSS_MAIN_CLK;
224 break;
225 case GCK_CSS_PLLA_CLK:
226 regval |= AT91_PMC_PCR_GCKCSS_PLLA_CLK;
227 break;
228 case GCK_CSS_UPLL_CLK:
229 regval |= AT91_PMC_PCR_GCKCSS_UPLL_CLK;
230 break;
231 case GCK_CSS_MCK_CLK:
232 regval |= AT91_PMC_PCR_GCKCSS_MCK_CLK;
233 break;
234 case GCK_CSS_AUDIO_CLK:
235 regval |= AT91_PMC_PCR_GCKCSS_AUDIO_CLK;
236 break;
237 default:
238 printf("Error GCK clock source selection!\n");
239 return -EINVAL;
240 }
241
242 regval |= AT91_PMC_PCR_CMD_WRITE |
243 AT91_PMC_PCR_GCKDIV_(div) |
244 AT91_PMC_PCR_GCKEN;
245
246 writel(regval, &pmc->pcr);
247
248 do {
249 udelay(1);
250 status = readl(&pmc->sr);
251 } while ((!!(--timeout)) && (!(status & AT91_PMC_GCKRDY)));
252
253 if (!timeout)
254 printf("Timeout waiting for GCK ready!\n");
255
256 return 0;
257 }
258
at91_get_periph_generated_clk(u32 id)259 u32 at91_get_periph_generated_clk(u32 id)
260 {
261 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
262 u32 regval, clk_source, div;
263 u32 freq;
264
265 if (id > AT91_PMC_PCR_PID_MASK)
266 return 0;
267
268 writel(id, &pmc->pcr);
269 regval = readl(&pmc->pcr);
270
271 clk_source = regval & AT91_PMC_PCR_GCKCSS;
272 switch (clk_source) {
273 case AT91_PMC_PCR_GCKCSS_SLOW_CLK:
274 freq = CONFIG_SYS_AT91_SLOW_CLOCK;
275 break;
276 case AT91_PMC_PCR_GCKCSS_MAIN_CLK:
277 freq = gd->arch.main_clk_rate_hz;
278 break;
279 case AT91_PMC_PCR_GCKCSS_PLLA_CLK:
280 freq = gd->arch.plla_rate_hz;
281 break;
282 case AT91_PMC_PCR_GCKCSS_UPLL_CLK:
283 freq = AT91_UTMI_PLL_CLK_FREQ;
284 break;
285 case AT91_PMC_PCR_GCKCSS_MCK_CLK:
286 freq = gd->arch.mck_rate_hz;
287 break;
288 default:
289 printf("Improper GCK clock source selection!\n");
290 freq = 0;
291 break;
292 }
293
294 div = ((regval & AT91_PMC_PCR_GCKDIV) >> AT91_PMC_PCR_GCKDIV_OFFSET);
295 div += 1;
296
297 return freq / div;
298 }
299