1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright 2014 Freescale Semiconductor, Inc.
4 */
5
6 #include <common.h>
7 #include <i2c.h>
8 #include <hwconfig.h>
9 #include <init.h>
10 #include <log.h>
11 #include <asm/global_data.h>
12 #include <asm/mmu.h>
13 #include <fsl_ddr_sdram.h>
14 #include <fsl_ddr_dimm_params.h>
15 #include <asm/fsl_law.h>
16 #include "ddr.h"
17
18 DECLARE_GLOBAL_DATA_PTR;
19
fsl_ddr_board_options(memctl_options_t * popts,dimm_params_t * pdimm,unsigned int ctrl_num)20 void fsl_ddr_board_options(memctl_options_t *popts,
21 dimm_params_t *pdimm,
22 unsigned int ctrl_num)
23 {
24 const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
25 ulong ddr_freq;
26
27 if (ctrl_num > 1) {
28 printf("Not supported controller number %d\n", ctrl_num);
29 return;
30 }
31 if (!pdimm->n_ranks)
32 return;
33
34 pbsp = udimms[0];
35
36 /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
37 * freqency and n_banks specified in board_specific_parameters table.
38 */
39 ddr_freq = get_ddr_freq(0) / 1000000;
40 while (pbsp->datarate_mhz_high) {
41 if (pbsp->n_ranks == pdimm->n_ranks &&
42 (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
43 if (ddr_freq <= pbsp->datarate_mhz_high) {
44 popts->clk_adjust = pbsp->clk_adjust;
45 popts->wrlvl_start = pbsp->wrlvl_start;
46 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
47 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
48 goto found;
49 }
50 pbsp_highest = pbsp;
51 }
52 pbsp++;
53 }
54
55 if (pbsp_highest) {
56 printf("Error: board specific timing not found");
57 printf("for data rate %lu MT/s\n", ddr_freq);
58 printf("Trying to use the highest speed (%u) parameters\n",
59 pbsp_highest->datarate_mhz_high);
60 popts->clk_adjust = pbsp_highest->clk_adjust;
61 popts->wrlvl_start = pbsp_highest->wrlvl_start;
62 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
63 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
64 } else {
65 panic("DIMM is not supported by this board");
66 }
67 found:
68 debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
69 "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, "
70 "wrlvl_ctrl_3 0x%x\n",
71 pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
72 pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
73 pbsp->wrlvl_ctl_3);
74
75 /*
76 * Factors to consider for half-strength driver enable:
77 * - number of DIMMs installed
78 */
79 popts->half_strength_driver_enable = 0;
80 /*
81 * Write leveling override
82 */
83 popts->wrlvl_override = 1;
84 popts->wrlvl_sample = 0xf;
85
86 /*
87 * Rtt and Rtt_WR override
88 */
89 popts->rtt_override = 0;
90
91 /* Enable ZQ calibration */
92 popts->zq_en = 1;
93
94 /* DHC_EN =1, ODT = 75 Ohm */
95 popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
96 popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
97
98 /* optimize cpo for erratum A-009942 */
99 popts->cpo_sample = 0x54;
100 }
101
dram_init(void)102 int dram_init(void)
103 {
104 phys_size_t dram_size;
105
106 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
107 puts("Initializing....using SPD\n");
108 dram_size = fsl_ddr_sdram();
109 #else
110 /* DDR has been initialised by first stage boot loader */
111 dram_size = fsl_ddr_sdram_size();
112 #endif
113 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
114 dram_size *= 0x100000;
115
116 gd->ram_size = dram_size;
117
118 return 0;
119 }
120