1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2011, 2013 Renesas Solutions Corp.
4 * Copyright (C) 2011, 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
5 *
6 * NOTE: This driver should be converted to driver model before June 2017.
7 * Please see doc/driver-model/i2c-howto.rst for instructions.
8 */
9
10 #include <common.h>
11 #include <i2c.h>
12 #include <log.h>
13 #include <asm/global_data.h>
14 #include <asm/io.h>
15 #include <linux/delay.h>
16
17 DECLARE_GLOBAL_DATA_PTR;
18
19 /* Every register is 32bit aligned, but only 8bits in size */
20 #define ureg(name) u8 name; u8 __pad_##name##0; u16 __pad_##name##1;
21 struct sh_i2c {
22 ureg(icdr);
23 ureg(iccr);
24 ureg(icsr);
25 ureg(icic);
26 ureg(iccl);
27 ureg(icch);
28 };
29 #undef ureg
30
31 /* ICCR */
32 #define SH_I2C_ICCR_ICE (1 << 7)
33 #define SH_I2C_ICCR_RACK (1 << 6)
34 #define SH_I2C_ICCR_RTS (1 << 4)
35 #define SH_I2C_ICCR_BUSY (1 << 2)
36 #define SH_I2C_ICCR_SCP (1 << 0)
37
38 /* ICSR / ICIC */
39 #define SH_IC_BUSY (1 << 4)
40 #define SH_IC_TACK (1 << 2)
41 #define SH_IC_WAIT (1 << 1)
42 #define SH_IC_DTE (1 << 0)
43
44 #ifdef CONFIG_SH_I2C_8BIT
45 /* store 8th bit of iccl and icch in ICIC register */
46 #define SH_I2C_ICIC_ICCLB8 (1 << 7)
47 #define SH_I2C_ICIC_ICCHB8 (1 << 6)
48 #endif
49
50 static const struct sh_i2c *i2c_dev[CONFIG_SYS_I2C_SH_NUM_CONTROLLERS] = {
51 (struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE0,
52 #ifdef CONFIG_SYS_I2C_SH_BASE1
53 (struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE1,
54 #endif
55 #ifdef CONFIG_SYS_I2C_SH_BASE2
56 (struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE2,
57 #endif
58 #ifdef CONFIG_SYS_I2C_SH_BASE3
59 (struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE3,
60 #endif
61 #ifdef CONFIG_SYS_I2C_SH_BASE4
62 (struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE4,
63 #endif
64 };
65
66 static u16 iccl, icch;
67
68 #define IRQ_WAIT 1000
69
sh_irq_dte(struct sh_i2c * dev)70 static void sh_irq_dte(struct sh_i2c *dev)
71 {
72 int i;
73
74 for (i = 0; i < IRQ_WAIT; i++) {
75 if (SH_IC_DTE & readb(&dev->icsr))
76 break;
77 udelay(10);
78 }
79 }
80
sh_irq_dte_with_tack(struct sh_i2c * dev)81 static int sh_irq_dte_with_tack(struct sh_i2c *dev)
82 {
83 int i;
84
85 for (i = 0; i < IRQ_WAIT; i++) {
86 if (SH_IC_DTE & readb(&dev->icsr))
87 break;
88 if (SH_IC_TACK & readb(&dev->icsr))
89 return -1;
90 udelay(10);
91 }
92 return 0;
93 }
94
sh_irq_busy(struct sh_i2c * dev)95 static void sh_irq_busy(struct sh_i2c *dev)
96 {
97 int i;
98
99 for (i = 0; i < IRQ_WAIT; i++) {
100 if (!(SH_IC_BUSY & readb(&dev->icsr)))
101 break;
102 udelay(10);
103 }
104 }
105
sh_i2c_set_addr(struct sh_i2c * dev,u8 chip,u8 addr,int stop)106 static int sh_i2c_set_addr(struct sh_i2c *dev, u8 chip, u8 addr, int stop)
107 {
108 u8 icic = SH_IC_TACK;
109
110 debug("%s: chip: %x, addr: %x iccl: %x, icch %x\n",
111 __func__, chip, addr, iccl, icch);
112 clrbits_8(&dev->iccr, SH_I2C_ICCR_ICE);
113 setbits_8(&dev->iccr, SH_I2C_ICCR_ICE);
114
115 writeb(iccl & 0xff, &dev->iccl);
116 writeb(icch & 0xff, &dev->icch);
117 #ifdef CONFIG_SH_I2C_8BIT
118 if (iccl > 0xff)
119 icic |= SH_I2C_ICIC_ICCLB8;
120 if (icch > 0xff)
121 icic |= SH_I2C_ICIC_ICCHB8;
122 #endif
123 writeb(icic, &dev->icic);
124
125 writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), &dev->iccr);
126 sh_irq_dte(dev);
127
128 clrbits_8(&dev->icsr, SH_IC_TACK);
129 writeb(chip << 1, &dev->icdr);
130 if (sh_irq_dte_with_tack(dev) != 0)
131 return -1;
132
133 writeb(addr, &dev->icdr);
134 if (stop)
135 writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS), &dev->iccr);
136
137 if (sh_irq_dte_with_tack(dev) != 0)
138 return -1;
139 return 0;
140 }
141
sh_i2c_finish(struct sh_i2c * dev)142 static void sh_i2c_finish(struct sh_i2c *dev)
143 {
144 writeb(0, &dev->icsr);
145 clrbits_8(&dev->iccr, SH_I2C_ICCR_ICE);
146 }
147
148 static int
sh_i2c_raw_write(struct sh_i2c * dev,u8 chip,uint addr,u8 val)149 sh_i2c_raw_write(struct sh_i2c *dev, u8 chip, uint addr, u8 val)
150 {
151 int ret = -1;
152 if (sh_i2c_set_addr(dev, chip, addr, 0) != 0)
153 goto exit0;
154 udelay(10);
155
156 writeb(val, &dev->icdr);
157 if (sh_irq_dte_with_tack(dev) != 0)
158 goto exit0;
159
160 writeb((SH_I2C_ICCR_ICE | SH_I2C_ICCR_RTS), &dev->iccr);
161 if (sh_irq_dte_with_tack(dev) != 0)
162 goto exit0;
163 sh_irq_busy(dev);
164 ret = 0;
165
166 exit0:
167 sh_i2c_finish(dev);
168 return ret;
169 }
170
sh_i2c_raw_read(struct sh_i2c * dev,u8 chip,u8 addr)171 static int sh_i2c_raw_read(struct sh_i2c *dev, u8 chip, u8 addr)
172 {
173 int ret = -1;
174
175 #if defined(CONFIG_SH73A0)
176 if (sh_i2c_set_addr(dev, chip, addr, 0) != 0)
177 goto exit0;
178 #else
179 if (sh_i2c_set_addr(dev, chip, addr, 1) != 0)
180 goto exit0;
181 udelay(100);
182 #endif
183
184 writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), &dev->iccr);
185 sh_irq_dte(dev);
186
187 writeb(chip << 1 | 0x01, &dev->icdr);
188 if (sh_irq_dte_with_tack(dev) != 0)
189 goto exit0;
190
191 writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_SCP), &dev->iccr);
192 if (sh_irq_dte_with_tack(dev) != 0)
193 goto exit0;
194
195 ret = readb(&dev->icdr) & 0xff;
196
197 writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RACK), &dev->iccr);
198 readb(&dev->icdr); /* Dummy read */
199 sh_irq_busy(dev);
200
201 exit0:
202 sh_i2c_finish(dev);
203
204 return ret;
205 }
206
207 static void
sh_i2c_init(struct i2c_adapter * adap,int speed,int slaveadd)208 sh_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
209 {
210 int num, denom, tmp;
211
212 /* No i2c support prior to relocation */
213 if (!(gd->flags & GD_FLG_RELOC))
214 return;
215
216 /*
217 * Calculate the value for iccl. From the data sheet:
218 * iccl = (p-clock / transfer-rate) * (L / (L + H))
219 * where L and H are the SCL low and high ratio.
220 */
221 num = CONFIG_SH_I2C_CLOCK * CONFIG_SH_I2C_DATA_LOW;
222 denom = speed * (CONFIG_SH_I2C_DATA_HIGH + CONFIG_SH_I2C_DATA_LOW);
223 tmp = num * 10 / denom;
224 if (tmp % 10 >= 5)
225 iccl = (u16)((num/denom) + 1);
226 else
227 iccl = (u16)(num/denom);
228
229 /* Calculate the value for icch. From the data sheet:
230 icch = (p clock / transfer rate) * (H / (L + H)) */
231 num = CONFIG_SH_I2C_CLOCK * CONFIG_SH_I2C_DATA_HIGH;
232 tmp = num * 10 / denom;
233 if (tmp % 10 >= 5)
234 icch = (u16)((num/denom) + 1);
235 else
236 icch = (u16)(num/denom);
237
238 debug("clock: %d, speed %d, iccl: %x, icch: %x\n",
239 CONFIG_SH_I2C_CLOCK, speed, iccl, icch);
240 }
241
sh_i2c_read(struct i2c_adapter * adap,uint8_t chip,uint addr,int alen,u8 * data,int len)242 static int sh_i2c_read(struct i2c_adapter *adap, uint8_t chip,
243 uint addr, int alen, u8 *data, int len)
244 {
245 int ret, i;
246 struct sh_i2c *dev = (struct sh_i2c *)i2c_dev[adap->hwadapnr];
247
248 for (i = 0; i < len; i++) {
249 ret = sh_i2c_raw_read(dev, chip, addr + i);
250 if (ret < 0)
251 return -1;
252
253 data[i] = ret & 0xff;
254 debug("%s: data[%d]: %02x\n", __func__, i, data[i]);
255 }
256
257 return 0;
258 }
259
sh_i2c_write(struct i2c_adapter * adap,uint8_t chip,uint addr,int alen,u8 * data,int len)260 static int sh_i2c_write(struct i2c_adapter *adap, uint8_t chip, uint addr,
261 int alen, u8 *data, int len)
262 {
263 struct sh_i2c *dev = (struct sh_i2c *)i2c_dev[adap->hwadapnr];
264 int i;
265
266 for (i = 0; i < len; i++) {
267 debug("%s: data[%d]: %02x\n", __func__, i, data[i]);
268 if (sh_i2c_raw_write(dev, chip, addr + i, data[i]) != 0)
269 return -1;
270 }
271 return 0;
272 }
273
274 static int
sh_i2c_probe(struct i2c_adapter * adap,u8 dev)275 sh_i2c_probe(struct i2c_adapter *adap, u8 dev)
276 {
277 u8 dummy[1];
278
279 return sh_i2c_read(adap, dev, 0, 0, dummy, sizeof dummy);
280 }
281
sh_i2c_set_bus_speed(struct i2c_adapter * adap,unsigned int speed)282 static unsigned int sh_i2c_set_bus_speed(struct i2c_adapter *adap,
283 unsigned int speed)
284 {
285 struct sh_i2c *dev = (struct sh_i2c *)i2c_dev[adap->hwadapnr];
286
287 sh_i2c_finish(dev);
288 sh_i2c_init(adap, speed, 0);
289
290 return 0;
291 }
292
293 /*
294 * Register RCAR i2c adapters
295 */
296 U_BOOT_I2C_ADAP_COMPLETE(sh_0, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
297 sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED0, 0, 0)
298 #ifdef CONFIG_SYS_I2C_SH_BASE1
299 U_BOOT_I2C_ADAP_COMPLETE(sh_1, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
300 sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED1, 0, 1)
301 #endif
302 #ifdef CONFIG_SYS_I2C_SH_BASE2
303 U_BOOT_I2C_ADAP_COMPLETE(sh_2, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
304 sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED2, 0, 2)
305 #endif
306 #ifdef CONFIG_SYS_I2C_SH_BASE3
307 U_BOOT_I2C_ADAP_COMPLETE(sh_3, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
308 sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED3, 0, 3)
309 #endif
310 #ifdef CONFIG_SYS_I2C_SH_BASE4
311 U_BOOT_I2C_ADAP_COMPLETE(sh_4, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
312 sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED4, 0, 4)
313 #endif
314