1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Meson GXL Internal PHY Driver
4 *
5 * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
6 * Copyright (C) 2016 BayLibre, SAS. All rights reserved.
7 * Author: Neil Armstrong <narmstrong@baylibre.com>
8 */
9 #include <config.h>
10 #include <common.h>
11 #include <linux/bitops.h>
12 #include <dm.h>
13 #include <phy.h>
14
15 /* This function is provided to cope with the possible failures of this phy
16 * during aneg process. When aneg fails, the PHY reports that aneg is done
17 * but the value found in MII_LPA is wrong:
18 * - Early failures: MII_LPA is just 0x0001. if MII_EXPANSION reports that
19 * the link partner (LP) supports aneg but the LP never acked our base
20 * code word, it is likely that we never sent it to begin with.
21 * - Late failures: MII_LPA is filled with a value which seems to make sense
22 * but it actually is not what the LP is advertising. It seems that we
23 * can detect this using a magic bit in the WOL bank (reg 12 - bit 12).
24 * If this particular bit is not set when aneg is reported being done,
25 * it means MII_LPA is likely to be wrong.
26 *
27 * In both case, forcing a restart of the aneg process solve the problem.
28 * When this failure happens, the first retry is usually successful but,
29 * in some cases, it may take up to 6 retries to get a decent result
30 */
meson_gxl_startup(struct phy_device * phydev)31 int meson_gxl_startup(struct phy_device *phydev)
32 {
33 unsigned int retries = 10;
34 int ret, wol, lpa, exp;
35
36 restart_aneg:
37 ret = genphy_update_link(phydev);
38 if (ret)
39 return ret;
40
41 if (phydev->autoneg == AUTONEG_ENABLE) {
42 /* Need to access WOL bank, make sure the access is open */
43 ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000);
44 if (ret)
45 return ret;
46 ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400);
47 if (ret)
48 return ret;
49 ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000);
50 if (ret)
51 return ret;
52 ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400);
53 if (ret)
54 return ret;
55
56 /* Request LPI_STATUS WOL register */
57 ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x8D80);
58 if (ret)
59 return ret;
60
61 /* Read LPI_STATUS value */
62 wol = phy_read(phydev, MDIO_DEVAD_NONE, 0x15);
63 if (wol < 0)
64 return wol;
65
66 lpa = phy_read(phydev, MDIO_DEVAD_NONE, MII_LPA);
67 if (lpa < 0)
68 return lpa;
69
70 exp = phy_read(phydev, MDIO_DEVAD_NONE, MII_EXPANSION);
71 if (exp < 0)
72 return exp;
73
74 if (!(wol & BIT(12)) ||
75 ((exp & EXPANSION_NWAY) && !(lpa & LPA_LPACK))) {
76
77 /* Looks like aneg failed after all */
78 if (!retries) {
79 printf("%s LPA corruption max attempts\n",
80 phydev->dev->name);
81 return -ETIMEDOUT;
82 }
83
84 printf("%s LPA corruption - aneg restart\n",
85 phydev->dev->name);
86
87 ret = genphy_restart_aneg(phydev);
88 if (ret)
89 return ret;
90
91 --retries;
92
93 goto restart_aneg;
94 }
95 }
96
97 return genphy_parse_link(phydev);
98 }
99
meson_gxl_phy_config(struct phy_device * phydev)100 static int meson_gxl_phy_config(struct phy_device *phydev)
101 {
102 /* Enable Analog and DSP register Bank access by */
103 phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000);
104 phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400);
105 phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000);
106 phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400);
107
108 /* Write Analog register 23 */
109 phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x8E0D);
110 phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x4417);
111
112 /* Enable fractional PLL */
113 phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x0005);
114 phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1B);
115
116 /* Program fraction FR_PLL_DIV1 */
117 phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x029A);
118 phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1D);
119
120 /* Program fraction FR_PLL_DIV1 */
121 phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0xAAAA);
122 phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1C);
123
124 return genphy_config(phydev);
125 }
126
127 static struct phy_driver meson_gxl_phy_driver = {
128 .name = "Meson GXL Internal PHY",
129 .uid = 0x01814400,
130 .mask = 0xfffffff0,
131 .features = PHY_BASIC_FEATURES,
132 .config = &meson_gxl_phy_config,
133 .startup = &meson_gxl_startup,
134 .shutdown = &genphy_shutdown,
135 };
136
phy_meson_gxl_init(void)137 int phy_meson_gxl_init(void)
138 {
139 phy_register(&meson_gxl_phy_driver);
140
141 return 0;
142 }
143