1// SPDX-License-Identifier: GPL-2.0+ OR X11 2/* 3 * NXP ls1088a SOC common device tree source 4 * 5 * Copyright 2017, 2020-2021 NXP 6 */ 7 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9/ { 10 compatible = "fsl,ls1088a"; 11 interrupt-parent = <&gic>; 12 #address-cells = <2>; 13 #size-cells = <2>; 14 15 memory@80000000 { 16 device_type = "memory"; 17 reg = <0x00000000 0x80000000 0 0x80000000>; 18 /* DRAM space - 1, size : 2 GB DRAM */ 19 }; 20 21 gic: interrupt-controller@6000000 { 22 compatible = "arm,gic-v3"; 23 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */ 24 <0x0 0x06100000 0 0x100000>; /* GICR (RD_base + SGI_base) */ 25 #interrupt-cells = <3>; 26 interrupt-controller; 27 interrupts = <1 9 0x4>; 28 }; 29 30 gic_lpi_base: syscon@0x80000000 { 31 compatible = "gic-lpi-base"; 32 reg = <0x0 0x80000000 0x0 0x100000>; 33 max-gic-redistributors = <8>; 34 }; 35 36 timer { 37 compatible = "arm,armv8-timer"; 38 interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */ 39 <1 14 0x8>, /* Physical Non-Secure PPI, active-low */ 40 <1 11 0x8>, /* Virtual PPI, active-low */ 41 <1 10 0x8>; /* Hypervisor PPI, active-low */ 42 }; 43 44 i2c0: i2c@2000000 { 45 compatible = "fsl,vf610-i2c"; 46 #address-cells = <1>; 47 #size-cells = <0>; 48 reg = <0x0 0x2000000 0x0 0x10000>; 49 interrupts = <0 34 4>; 50 }; 51 52 i2c1: i2c@2010000 { 53 compatible = "fsl,vf610-i2c"; 54 #address-cells = <1>; 55 #size-cells = <0>; 56 reg = <0x0 0x2010000 0x0 0x10000>; 57 interrupts = <0 34 4>; 58 }; 59 60 i2c2: i2c@2020000 { 61 compatible = "fsl,vf610-i2c"; 62 #address-cells = <1>; 63 #size-cells = <0>; 64 reg = <0x0 0x2020000 0x0 0x10000>; 65 interrupts = <0 35 4>; 66 }; 67 68 i2c3: i2c@2030000 { 69 compatible = "fsl,vf610-i2c"; 70 #address-cells = <1>; 71 #size-cells = <0>; 72 reg = <0x0 0x2030000 0x0 0x10000>; 73 interrupts = <0 35 4>; 74 }; 75 76 serial0: serial@21c0500 { 77 device_type = "serial"; 78 compatible = "fsl,ns16550", "ns16550a"; 79 reg = <0x0 0x21c0500 0x0 0x100>; 80 clock-frequency = <0>; /* Updated by bootloader */ 81 interrupts = <0 32 0x1>; /* edge triggered */ 82 }; 83 84 serial1: serial@21c0600 { 85 device_type = "serial"; 86 compatible = "fsl,ns16550", "ns16550a"; 87 reg = <0x0 0x21c0600 0x0 0x100>; 88 clock-frequency = <0>; /* Updated by bootloader */ 89 interrupts = <0 32 0x1>; /* edge triggered */ 90 }; 91 92 dspi: dspi@2100000 { 93 compatible = "fsl,vf610-dspi"; 94 #address-cells = <1>; 95 #size-cells = <0>; 96 reg = <0x0 0x2100000 0x0 0x10000>; 97 interrupts = <0 26 0x4>; /* Level high type */ 98 num-cs = <6>; 99 }; 100 101 qspi: quadspi@1550000 { 102 compatible = "fsl,ls1088a-qspi"; 103 #address-cells = <1>; 104 #size-cells = <0>; 105 reg = <0x0 0x20c0000 0x0 0x10000>, 106 <0x0 0x20000000 0x0 0x10000000>; 107 reg-names = "QuadSPI", "QuadSPI-memory"; 108 num-cs = <4>; 109 }; 110 111 esdhc: esdhc@2140000 { 112 compatible = "fsl,esdhc"; 113 reg = <0x0 0x2140000 0x0 0x10000>; 114 interrupts = <0 28 0x4>; /* Level high type */ 115 little-endian; 116 bus-width = <4>; 117 }; 118 119 gpio0: gpio@2300000 { 120 compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; 121 reg = <0x0 0x2300000 0x0 0x10000>; 122 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 123 little-endian; 124 gpio-controller; 125 #gpio-cells = <2>; 126 interrupt-controller; 127 #interrupt-cells = <2>; 128 }; 129 130 gpio1: gpio@2310000 { 131 compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; 132 reg = <0x0 0x2310000 0x0 0x10000>; 133 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 134 little-endian; 135 gpio-controller; 136 #gpio-cells = <2>; 137 interrupt-controller; 138 #interrupt-cells = <2>; 139 }; 140 141 gpio2: gpio@2320000 { 142 compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; 143 reg = <0x0 0x2320000 0x0 0x10000>; 144 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 145 little-endian; 146 gpio-controller; 147 #gpio-cells = <2>; 148 interrupt-controller; 149 #interrupt-cells = <2>; 150 }; 151 152 gpio3: gpio@2330000 { 153 compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; 154 reg = <0x0 0x2330000 0x0 0x10000>; 155 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 156 little-endian; 157 gpio-controller; 158 #gpio-cells = <2>; 159 interrupt-controller; 160 #interrupt-cells = <2>; 161 }; 162 163 ifc: ifc@1530000 { 164 compatible = "fsl,ifc", "simple-bus"; 165 reg = <0x0 0x2240000 0x0 0x20000>; 166 interrupts = <0 21 0x4>; /* Level high type */ 167 }; 168 169 usb0: usb3@3100000 { 170 compatible = "fsl,layerscape-dwc3"; 171 reg = <0x0 0x3100000 0x0 0x10000>; 172 interrupts = <0 80 0x4>; /* Level high type */ 173 dr_mode = "host"; 174 }; 175 176 usb1: usb3@3110000 { 177 compatible = "fsl,layerscape-dwc3"; 178 reg = <0x0 0x3110000 0x0 0x10000>; 179 interrupts = <0 81 0x4>; /* Level high type */ 180 dr_mode = "host"; 181 }; 182 183 pcie1: pcie@3400000 { 184 compatible = "fsl,ls-pcie", "snps,dw-pcie"; 185 reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */ 186 0x00 0x03480000 0x0 0x80000 /* lut registers */ 187 0x00 0x034c0000 0x0 0x40000 /* pf controls registers */ 188 0x20 0x00000000 0x0 0x20000>; /* configuration space */ 189 reg-names = "dbi", "lut", "ctrl", "config"; 190 #address-cells = <3>; 191 #size-cells = <2>; 192 device_type = "pci"; 193 num-lanes = <4>; 194 bus-range = <0x0 0xff>; 195 ranges = <0x81000000 0x0 0x00000000 0x20 0x00020000 0x0 0x00010000 /* downstream I/O */ 196 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 197 }; 198 199 pcie2: pcie@3500000 { 200 compatible = "fsl,ls-pcie", "snps,dw-pcie"; 201 reg = <0x00 0x03500000 0x0 0x80000 /* dbi registers */ 202 0x00 0x03580000 0x0 0x80000 /* lut registers */ 203 0x00 0x035c0000 0x0 0x40000 /* pf controls registers */ 204 0x28 0x00000000 0x0 0x20000>; /* configuration space */ 205 reg-names = "dbi", "lut", "ctrl", "config"; 206 #address-cells = <3>; 207 #size-cells = <2>; 208 device_type = "pci"; 209 num-lanes = <4>; 210 bus-range = <0x0 0xff>; 211 ranges = <0x81000000 0x0 0x00000000 0x28 0x00020000 0x0 0x00010000 /* downstream I/O */ 212 0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 213 }; 214 215 pcie3: pcie@3600000 { 216 compatible = "fsl,ls-pcie", "snps,dw-pcie"; 217 reg = <0x00 0x03600000 0x0 0x80000 /* dbi registers */ 218 0x00 0x03680000 0x0 0x80000 /* lut registers */ 219 0x00 0x036c0000 0x0 0x40000 /* pf controls registers */ 220 0x30 0x00000000 0x0 0x20000>; /* configuration space */ 221 reg-names = "dbi", "lut", "ctrl", "config"; 222 #address-cells = <3>; 223 #size-cells = <2>; 224 device_type = "pci"; 225 num-lanes = <8>; 226 bus-range = <0x0 0xff>; 227 ranges = <0x81000000 0x0 0x00000000 0x30 0x00020000 0x0 0x00010000 /* downstream I/O */ 228 0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 229 }; 230 231 sata: sata@3200000 { 232 compatible = "fsl,ls1088a-ahci"; 233 reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */ 234 0x7 0x100520 0x0 0x4>; /* ecc sata addr*/ 235 reg-names = "sata-base", "ecc-addr"; 236 interrupts = <0 133 4>; 237 status = "disabled"; 238 }; 239 240 psci { 241 compatible = "arm,psci-0.2"; 242 method = "smc"; 243 }; 244 245 fsl_mc: fsl-mc@80c000000 { 246 compatible = "fsl,qoriq-mc", "simple-mfd"; 247 reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */ 248 <0x00000000 0x08340000 0 0x40000>; /* MC control reg */ 249 #address-cells = <3>; 250 #size-cells = <1>; 251 252 /* 253 * Region type 0x0 - MC portals 254 * Region type 0x1 - QBMAN portals 255 */ 256 ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000 257 0x1 0x0 0x0 0x8 0x18000000 0x8000000>; 258 259 dpmacs { 260 compatible = "simple-mfd"; 261 #address-cells = <1>; 262 #size-cells = <0>; 263 264 dpmac1: dpmac@1 { 265 compatible = "fsl,qoriq-mc-dpmac"; 266 reg = <0x1>; 267 status = "disabled"; 268 }; 269 270 dpmac2: dpmac@2 { 271 compatible = "fsl,qoriq-mc-dpmac"; 272 reg = <0x2>; 273 status = "disabled"; 274 }; 275 276 dpmac3: dpmac@3 { 277 compatible = "fsl,qoriq-mc-dpmac"; 278 reg = <0x3>; 279 status = "disabled"; 280 }; 281 282 dpmac4: dpmac@4 { 283 compatible = "fsl,qoriq-mc-dpmac"; 284 reg = <0x4>; 285 status = "disabled"; 286 }; 287 288 dpmac5: dpmac@5 { 289 compatible = "fsl,qoriq-mc-dpmac"; 290 reg = <0x5>; 291 status = "disabled"; 292 }; 293 294 dpmac6: dpmac@6 { 295 compatible = "fsl,qoriq-mc-dpmac"; 296 reg = <0x6>; 297 status = "disabled"; 298 }; 299 300 dpmac7: dpmac@7 { 301 compatible = "fsl,qoriq-mc-dpmac"; 302 reg = <0x7>; 303 status = "disabled"; 304 }; 305 306 dpmac8: dpmac@8 { 307 compatible = "fsl,qoriq-mc-dpmac"; 308 reg = <0x8>; 309 status = "disabled"; 310 }; 311 312 dpmac9: dpmac@9 { 313 compatible = "fsl,qoriq-mc-dpmac"; 314 reg = <0x9>; 315 status = "disabled"; 316 }; 317 318 dpmac10: dpmac@a { 319 compatible = "fsl,qoriq-mc-dpmac"; 320 reg = <0xa>; 321 status = "disabled"; 322 }; 323 }; 324 }; 325 326 emdio1: mdio@8B96000 { 327 compatible = "fsl,ls-mdio"; 328 reg = <0x0 0x8B96000 0x0 0x1000>; 329 #address-cells = <1>; 330 #size-cells = <0>; 331 status = "disabled"; 332 }; 333 334 emdio2: mdio@8B97000 { 335 compatible = "fsl,ls-mdio"; 336 reg = <0x0 0x8B97000 0x0 0x1000>; 337 #address-cells = <1>; 338 #size-cells = <0>; 339 status = "disabled"; 340 }; 341}; 342